CD40162BMS

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS December 1992 File Number 3358 CMOS Synchronous Programmable 4-Bit Counters CD40160BMS, CD40161BMS, CD40162BMS and CD40163BMS are 4-bit synchronous programmable counters. The CLEAR function of the CD40162BMS and CD40163BMS is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the CD40160BMS and CD40161BMS is asychronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output (COUT). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enabled output produces a positive output pulses with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low. The CD40160BMS through CD40163BMS types are functionally equivalent to and pin-compatible with the TTL counter series 74LS160 through 74LS163 respectively. The CD40160BMS, CD40161BMS, CD40162BMS and CD40163BMS are supplied in these 16 lead outline packages: CD40160 CD40161 CD40162 CD40163 Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H1F H6P H4X H1F H6W H4X H1L H6P H4W H1F H6W Features • High-Voltage Types (20V Rating) • CD40160BMS Decade with Asynchronous Clear • CD40161BMS Binary with Asynchronous Clear • CD40162BMS Decade with Synchronous Clear • CD40163BMS Binary with Synchronous Clear • Internal Look-Ahead for Fast Counting • Carry Output for Cascading • Synchronously Programmable • Clear Asynchronous Input (CD40160BMS, CD40161BMS) • Clear Synchronous Input (CD40162BMS, CD40163BMS) • Synchronous Load Control Input • Low Power TTL Compatibility • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Programmable Binary and Decade Counting • Counter Control/Timers • Frequency Dividing Pinout CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS TOP VIEW Functional Diagram PE CLEAR 1 CLOCK 2 P1 3 P2 4 P3 5 P4 6 PE 7 VSS 8 16 VDD 15 CARRY OUT 14 Q1 13 Q2 12 Q3 11 Q4 10 TE 9 LOAD VDD = 16 VSS = 8 TE CLEAR LOAD CLOCK P1 P2 P3 P4 7 10 1 9 2 3 4 5 6 15 CARRY OUT 11 Q4 12 Q3 13 Q2 14 Q1 4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance. . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K). . . . . . .500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VOH > VOL < VDD/2 VDD/2 NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 4-2 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH FCL VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2 1.48 MAX 400 540 450 608 250 338 500 675 200 270 UNITS ns ns ns ns ns ns ns ns ns ns MHz MHz PARAMETER Propagation Delay Clock to Q Propagation Delay Clock to COut Propagation Delay TE to COut Propagation Delay CD40160BMS, CD40161BMS Clear to Q Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA VDD = 10V, VIN = VDD or GND 1, 2 VDD = 15V, VIN = VDD or GND 1, 2 Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 4-3 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES 1, 2 TEMPERATURE +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Clock to Q Propagation Delay Clock to C Out Propagation Delay TE to C Out Propagation Delay CD40160BMS, CD40161BMS Clear to Q Transition Time VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TRCL TFCL VDD = 5V VDD = 10V VDD = 15V Minimum Data Hold Time Clock Operation TH VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width Clock Operation Minimum Setup Time Data to Clock TW VDD = 5V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V Minimum Setup Time Load to Clock TS VDD = 5V VDD = 10V VDD = 15V Minimum Setup Time PE to TE to Clock TS VDD = 5V VDD = 10V VDD = 15V Minimum Clear Pulse Width (CD40160BMS, CD40161BMS) Minimum Setup Time Clear to Clock (CD40162BMS, CD40163BMS) Minimum Hold Time Clear to Clock (CD40162BMS, CD40163BMS) TW VDD = 5V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V TH VDD = 5V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 7 5.5 8 MAX -2.4 -4.2 3 160 120 190 140 110 80 220 160 100 80 200 70 15 0 0 0 170 70 50 240 90 60 240 90 60 340 140 100 170 70 50 340 140 100 0 0 0 UNITS mA mA V V ns ns ns ns ns ns ns ns ns ns MHz MHz µs µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Maximum Clock Input Frequency Maximum Clock Rise or Fall Time 4-4 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clear Removal Time (CD40160BMS, CD40161BMS) NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V SYMBOL TREM CONDITIONS VDD = 5V VDD = 10V VDD = 15V NOTES 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE +25oC +25oC +25oC MIN MAX 200 100 70 UNITS ns ns ns ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Group D Subgroup B-5 Subgroup B-6 MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. 4-5 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic Burn-In Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V OPEN 11 - 15 11 - 15 11 - 15 GROUND 1 - 10 8 8 8 VDD 16 1 - 7, 9, 10, 16 1, 7, 9, 10, 16 1 - 7, 9, 10, 16 11 - 15 2-6 9V ± -0.5V 50kHz 25kHz Logic Diagrams CD40160BMS AND CD40162BMS BCD DECADE COUNTERS * CD40160BMS ASYNCHRONOUS CLEAR LOAD* 9 7 PE * 10 TE * 3 P1 Q1 Q4 * 4 P2 Q1 Q4 * 5 P3 * 16 VDD Q1 * 6 P4 CLOCK* 2 CLEAR* 1 Q1 LOAD* 9 CLOCK* 2 CLEAR* 1 CD40162BMS SYNCHRONOUS CLEAR LD PI T CL CLR Q1 Q1 LD PI T CL CLR Q2 Q2 LD PI T CL CLR Q3 LD PI T CL CLR Q4 Q3 Q4 *INPUTS PROTECTED BY CMOS PROTECTION NETWORK VDD 14 Q1 VSS 13 Q2 12 Q3 11 Q4 15 COUT FIGURE 1. LOGIC DIAGRAM FOR CD40160BMS AND CD40162BMS BCD DECADE COUNTERS 4-6 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS Logic Diagrams (Continued) CD40161BMS AND CD40163BMS BINARY COUNTERS * CD40161BMS ASYNCHRONOUS CLEAR LOAD* 9 7 PE * 10 TE * 3 P1 16 VDD * 4 P2 Q1 Q2 * 5 P3 Q1 Q2 Q2 * 6 P4 Q1 CLOCK* 2 CLEAR* 1 Q2 Q4 Q3 LOAD* 9 CD40163BMS SYNCHRONOUS CLEAR Q1 LD PI CLOCK* 2 CLEAR* 1 T CL CLR Q1 LD PI T CL CLR Q2 LD PI T CL CLR Q3 LD PI T CL CLR Q4 Q1 Q2 Q3 Q4 *INPUTS PROTECTED BY CMOS PROTECTION NETWORK VDD 14 Q1 13 Q2 12 Q3 11 Q4 15 COUT VSS FIGURE 2. LOGIC DIAGRAM FOR CD40161BMS AND CD40163BMS BINARY COUNTERS TRUTH TABLE CLOCK CLR 1 1 1 1 X 0 0 1 1 = High Level 0 = Low Level LOAD 0 1 1 1 X X X PE X 0 X 1 X X X TE X X 0 1 X X X Preset NC NC Count Reset (CD40160BMS, CD40161BMS) Reset (CD40162BMS, CD40163BMS) NC (CD40162BMS, CD40163BMS) OPERATION X = Don’t Care NC = No Change 4-7 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 FIGURE 4. MIMIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -10 -10V -10 -15V -15 -15V -15 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) 300 200 SUPPLY VOLTAGE (VDD) = 5V SUPPLY VOLTAGE (VDD) = 5V 200 150 10V 100 15V 100 10V 50 15V 0 20 40 60 80 100 0 0 20 LOAD CAPACITANCE (CL) (pF) 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q) FIGURE 8. TYPICAL TRANSISTION TIME AS A FUNCTION OF LOAD CAPACITANCE 4-8 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS Typical Performance Characteristics (Continued) 105 8 AMBIENT TEMPERATURE (TA) 6 o 4 = +25 C POWER DISSIPATION (PD) (µW) 104 2 8 6 4 SUPPLY VOLTAGE (VDD) = 15V 103 2 8 6 4 10V 10V 5V CL = 50pF CL = 15pF 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 102 2 8 6 4 2 10 1 103 10 102 CLOCK FREQUENCY (fCL) (kHz) 104 FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY CLEAR (CD40160BMS) CLEAR (CD40162BMS) SYNCHRONOUS LOAD ASYNCHRONOUS P1 P2 DATA INPUTS P3 P4 CLOCK (CD40160BMS) CLOCK (CD40162BMS) PE ENABLES TE Q1 Q2 OUTPUTS Q3 Q4 CARRY OUT 0 7 8 9 0 1 2 3 INHIBIT COUNT CLEAR PRESET FIGURE 10. TIMING DIAGRAM FOR CD40160BMS, CD40162BMS 4-9 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS CLEAR (CD40161BMS) CLEAR (CD40163BMS) SYNCHRONOUS LOAD ASYNCHRONOUS P1 P2 DATA INPUTS P3 P4 CLOCK (CD40161BMS) CLOCK (CD40163BMS) PE ENABLES TE Q1 Q2 OUTPUTS Q3 Q4 CARRY OUT 0 12 13 14 15 0 1 2 INHIBIT COUNT CLEAR PRESET FIGURE 11. TIMING DIAGRAM FOR CD40161BMS AND CD40163BMS 4-10 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS TN PN LD p n CL CL CLR CL p n CL p n p n CL p n CL CL p n CL QN QN CL p n FIGURE 12. DETAIL OF FLIP-FLOPS OF CD40160BMS AND CD40161BMS (ASYNCHRONOUS CLEAR) TN CLR PN LD p n CL CL CL p n CL p n CL p n p n CL CL p n CL QN QN CL p n FIGURE 13. DETAIL OF FLIP-FLOPS OF CD40162BMS AND CD40163BMS (SYNCHRONOUS CLEAR) 4-11 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS LOAD VDD P1 P2 P3 P4 VDD PE TE CLK CLR LD CD PE TE CLK CLR LD CD PE TE CLK CLR LD CD P1 P2 P3 P4 P1 P2 P3 P4 Q1 Q2 Q3 CLOCK CLEAR Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FIGURE 14. CASCADED COUNTER PACKAGES IN THE PARALLEL-CLOCKED MODE LOAD VDD P1 P2 P3 P4 VDD P1 P2 P3 P4 VDD P1 P2 P3 P4 PE TE LD CD PE TE LD CD PE TE LD CD CLK CLR CLK CLR CLK CLR CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLEAR FIGURE 15. CASCADED COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE Chip Dimensions and Pad Layout Dimensions and pad layout for CD40160BMSH. Dimensions and pad layout for CD40161BMS, CD40162BMSH, and CD40163BMSH are identical. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 4-12 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-13