ICL3232

® ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Data Sheet March 1, 2006 FN4805.21 One Microamp Supply-Current, +3V to +5.5V, 250kbps, RS-232 Transmitters/Receivers The Intersil ICL32XX devices are 3.0V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic powerdown functions (except for the ICL3232), reduce the standby supply current to a 1µA trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. This family is fully compatible with 3.3V only systems, mixed 3.3V and 5.0V systems, and 5.0V only systems. The ICL324X are 3-driver, 5-receiver devices that provide a complete serial port suitable for laptop or notebook computers. Both devices also include noninverting alwaysactive receivers for “wake-up” capability. The ICL3221, ICL3223 and ICL3243, feature an automatic powerdown function which powers down the on-chip power-supply and driver circuits. This occurs when an attached peripheral device is shut off or the RS-232 cable is removed, conserving system power automatically without changes to the hardware or operating system. These devices power up again when a valid RS-232 voltage is applied to any receiver input. Table 1 summarizes the features of the devices represented by this data sheet, while Application Note AN9863 summarizes the features of each device comprising the ICL32XX 3V family. Features • Pb-Free Plus Anneal Available as an Option (RoHS Compliant) (See Ordering Info) • 15kV ESD Protected (Human Body Model) • Drop in Replacements for MAX3221, MAX3222, MAX3223, MAX3232, MAX3241, MAX3243, SP3243 • ICL3221 is Low Power, Pin Compatible Upgrade for 5V MAX221 • ICL3222 is Low Power, Pin Compatible Upgrade for 5V MAX242, and SP312A • ICL3232 is Low Power Upgrade for HIN232/ICL232 and Pin Compatible Competitor Devices • RS-232 Compatible with VCC = 2.7V • Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V • Latch-Up Free • On-Chip Voltage Converters Require Only Four External 0.1µF Capacitors • Manual and Automatic Powerdown Features (Except ICL3232) • Guaranteed Mouse Driveability (ICL324X Only) • Receiver Hysteresis For Improved Noise Immunity • Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps • Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/µs • Wide Power Supply Range . . . . . . . Single +3V to +5.5V • Low Supply Current in Powerdown State. . . . . . . . . . .1µA Applications • Any System Requiring RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Modems, Printers and other Peripherals - Digital Cameras - Cellular/Mobile Phones TABLE 1. SUMMARY OF FEATURES NO. OF NO. OF PART NUMBER Tx. Rx. ICL3221 ICL3222 ICL3223 ICL3232 ICL3241 ICL3243 1 2 2 2 3 3 1 2 2 2 5 5 NO. OF MONITOR Rx. (ROUTB) 0 0 0 0 2 1 DATA RATE (kbps) 250 250 250 250 250 250 Rx. ENABLE FUNCTION? Yes Yes Yes No Yes No READY OUTPUT? No No No No No No MANUAL POWERDOWN? Yes Yes Yes No Yes Yes AUTOMATIC POWERDOWN FUNCTION? Yes No Yes No No Yes 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Ordering Information PART NUMBER (NOTE 1) ICL3221CA ICL3221CAZ (Note 2) ICL3221CV ICL3221CVZ (Note 2) ICL3221IA ICL3221IAZ (Note 2) ICL3222CA ICL3222CAZ (Note 2) ICL3222CB ICL3222CBZ (Note 2) ICL3222CP ICL3222CPZ (Note 2) ICL3222CV ICL3222CVZ (Note 2) ICL3222IA ICL3222IAZ (Note 2) ICL3222IB ICL3222IV ICL3222IVZ (Note 2) ICL3223CA ICL3223CAZ (Note 2) ICL3223CP ICL3223CPZ (Note 2) ICL3223CV ICL3223IA ICL3223IAZ (Note 2) ICL3223IV ICL3223IVZ (Note 2) ICL3232CA ICL3232CAZ (Note 2) ICL3232CB ICL3232CBZ (Note 2) ICL3232CBN ICL3232CBNZ (Note 2) ICL3232CP ICL3232CPZ (Note 2) ICL3232CV PART MARKING ICL3221CA ICL3221CAZ ICL3221CV 3221CVZ ICL3221IA ICL3221IAZ ICL3222CA ICL3222CAZ ICL3222CB 3222CBZ ICL3222CP ICL3222CPZ ICL3222CV ICL3222CVZ ICL3222IA ICL3222IAZ ICL3222IB ICL3222IV ICL3222IVZ ICL3223CA ICL3223CAZ ICL3223CP ICL3223CPZ ICL3223CV ICL3223IA ICL3223IAZ ICL3223IV ICL3223IVZ ICL3232CA 3232CAZ ICL3232CB 3232CBZ 3232CBN 3232CBNZ ICL3232CP ICL3232CPZ ICL3232CV TEMP. RANGE (°C) 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld TSSOP 16 Ld TSSOP (Pb-free) 16 Ld SSOP 16 Ld SSOP (Pb-free) 20 Ld SSOP 20 Ld SSOP (Pb-free) 18 Ld SOIC 18 Ld SOIC (Pb-free) 18 Ld PDIP 18 Ld PDIP* (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld SSOP 20 Ld SSOP (Pb-free) 18 Ld SOIC 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld SSOP 20 Ld SSOP (Pb-free) 20 Ld PDIP 20 Ld PDIP* (Pb-free) 20 Ld TSSOP 20 Ld SSOP 20 Ld SSOP (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld SOIC (N) 16 Ld SOIC (N) (Pb-free) 16 Ld PDIP 16 Ld PDIP* (Pb-free) 16 Ld TSSOP PKG. DWG. # M16.209 M16.209 M16.173 M16.173 M16.209 M16.209 M20.209 M20.209 M18.3 M18.3 E18.3 E18.3 M20.173 M20.173 M20.209 M20.209 M18.3 M20.173 M20.173 M20.209 M20.209 E20.3 E20.3 M20.173 M20.209 M20.209 M20.173 M20.173 M16.209 M16.209 M16.3 M16.3 M16.15 M16.15 E16.3 E16.3 M16.173 2 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Ordering Information PART NUMBER (NOTE 1) ICL3232CVZ (Note 2) ICL3232IA ICL3232IAZ (Note 2) ICL3232IB ICL3232IBZ (Note 2) ICL3232IBN ICL3232IBNZ (Note 2) ICL3232IV ICL3232IVZ (Note 2) ICL3241CA ICL3241CAZ (Note 2) ICL3241CB ICL3241CBZ (Note 2) ICL3241CV ICL3241CVZ (Note 2) ICL3241IA ICL3241IAZ (Note 2) ICL3241IB ICL3241IBZ (Note 2) ICL3241IV ICL3241IVZ (Note 2) ICL3243CA ICL3243CAZ (Note 2) ICL3243CB ICL3243CBZ (Note 2) ICL3243CV ICL3243CVZ (Note 2) ICL3243IA ICL3243IAZ (Note 2) (Continued) PART MARKING 3232CVZ ICL3232IA 3232IAZ ICL3232IB 3232IBZ 3232IBN 3232IBNZ ICL3232IV 3232IVZ ICL3241CA ICL3241CAZ ICL3241CB ICL3241CBZ ICL3241CV ICL3241CVZ ICL3241IA ICL3241IAZ ICL3241IB ICL3241IBZ ICL3241IV ICL3241IVZ ICL3243CA ICL3243CAZ ICL3243CB ICL3243CBZ ICL3243CV ICL3243CVZ ICL3243IA ICL3243IAZ TEMP. RANGE (°C) 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 16 Ld TSSOP (Pb-free) 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld SOIC (N) 16 Ld SOIC (N) (Pb-free) 16 Ld TSSOP 16 Ld TSSOP (Pb-free) 28 Ld SSOP 28 Ld SSOP (Pb-free) 28 Ld SOIC 28 Ld SOIC (Pb-free) 28 Ld TSSOP 28 Ld TSSOP (Pb-free) 28 Ld SSOP 28 Ld SSOP (Pb-free) 28 Ld SOIC 28 Ld SOIC (Pb-free) 28 Ld TSSOP 28 Ld TSSOP (Pb-free) 28 Ld SSOP 28 Ld SSOP (Pb-free) 28 Ld SOIC 28 Ld SOIC (Pb-free) 28 Ld TSSOP 28 Ld TSSOP (Pb-free) 28 Ld SSOP 28 Ld SSOP (Pb-free) PKG. DWG. # M16.173 M16.209 M16.209 M16.3 M16.3 M16.15 M16.15 M16.173 M16.173 M28.209 M28.209 M28.3 M28.3 M28.173 M28.173 M28.209 M28.209 M28.3 M28.3 M28.173 M28.173 M28.209 M28.209 M28.3 M28.3 M28.173 M28.173 M28.209 M28.209 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES: 1. Most surface mount devices are available on tape and reel; add “-T” to suffix. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Pinouts ICL3221 (SSOP, TSSOP) TOP VIEW ICL3222 (PDIP, SOIC) TOP VIEW EN 1 C1+ 2 V+ 3 18 SHDN 17 VCC 16 GND 15 T1OUT 14 R1IN 13 R1OUT 12 T1IN 11 T2IN 10 R2OUT EN 1 C1+ 2 V+ 3 16 FORCEOFF 15 VCC 14 GND 13 T1OUT 12 FORCEON 11 T1IN 10 INVALID 9 R1OUT C1- 4 C2+ 5 C2- 6 V- 7 R1IN 8 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 ICL3222 (SSOP, TSSOP) TOP VIEW EN 1 C1+ 2 V+ 3 20 SHDN 19 VCC 18 GND 17 T1OUT 16 R1IN 15 R1OUT 14 NC 13 T1IN 12 T2IN 11 NC ICL3223 (PDIP, SSOP, TSSOP) TOP VIEW EN 1 C1+ 2 V+ 3 20 FORCEOFF 19 VCC 18 GND 17 T1OUT 16 R1IN 15 R1OUT 14 FORCEON 13 T1IN 12 T2IN 11 INVALID C1- 4 C2+ 5 C2- 6 V7 C1- 4 C2+ 5 C2- 6 V7 T2OUT 8 R2IN 9 R2OUT 10 T2OUT 8 R2IN 9 R2OUT 10 ICL3232 (PDIP, SOIC, SSOP, TSSOP) TOP VIEW C1+ 1 V+ 2 C13 16 VCC 15 GND 14 T1OUT 13 R1IN 12 R1OUT 11 T1IN 10 T2IN 9 R2OUT ICL3241 (SOIC, SSOP, TSSOP) TOP VIEW C2+ 1 C2- 2 V3 28 C1+ 27 V+ 26 VCC 25 GND 24 C123 EN 22 SHDN 21 R1OUTB 20 R2OUTB 19 R1OUT 18 R2OUT 17 R3OUT 16 R4OUT 15 R5OUT C2+ 4 C2- 5 V6 R1IN 4 R2IN 5 R3IN 6 R4IN 7 R5IN 8 T1OUT 9 T2OUT 10 T3OUT 11 T3IN 12 T2IN 13 T1IN 14 T2OUT 7 R2IN 8 4 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Pinouts (Continued) ICL3243 (SOIC, SSOP, TSSOP) TOP VIEW C2+ 1 C2- 2 V3 28 C1+ 27 V+ 26 VCC 25 GND 24 C123 FORCEON 22 FORCEOFF 21 INVALID 20 R2OUTB 19 R1OUT 18 R2OUT 17 R3OUT 16 R4OUT 15 R5OUT R1IN 4 R2IN 5 R3IN 6 R4IN 7 R5IN 8 T1OUT 9 T2OUT 10 T3OUT 11 T3IN 12 T2IN 13 T1IN 14 Pin Descriptions PIN VCC V+ VGND C1+ C1C2+ C2TIN TOUT RIN ROUT ROUTB INVALID EN SHDN System power supply input (3.0V to 5.5V). Internally generated positive transmitter supply (+5.5V). Internally generated negative transmitter supply (-5.5V). Ground connection. External capacitor (voltage doubler) is connected to this lead. External capacitor (voltage doubler) is connected to this lead. External capacitor (voltage inverter) is connected to this lead. External capacitor (voltage inverter) is connected to this lead. TTL/CMOS compatible transmitter Inputs. RS-232 level (nominally ±5.5V) transmitter outputs. RS-232 compatible receiver inputs. TTL/CMOS level receiver outputs. TTL/CMOS level, noninverting, always enabled receiver outputs. Active low output that indicates if no valid RS-232 levels are present on any receiver input. Active low receiver enable control; doesn’t disable ROUTB outputs. Active low input to shut down transmitters and on-board power supply, to place device in low power mode. FUNCTION FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See Table 2). FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high). 5 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Typical Operating Circuits ICL3221 C3 (OPTIONAL CONNECTION, NOTE) +3.3V + + +3.3V 0.1µF C1+ 15 VCC V+ 3 + C3 0.1µF C4 + 0.1µF RS-232 LEVELS T1OUT R1IN C1 0.1µF C2 0.1µF + 0.1µF + 2 4 5 + 6 12 11 C1+ C1C2+ C2T1 T2 V15 8 ICL3222 C3 (OPTIONAL CONNECTION, NOTE) + 17 VCC 3 V+ 7 + + C3 0.1µF C4 0.1µF T1OUT T2OUT RS-232 LEVELS RS-232 LEVELS 14 R1 R2OUT 10 1 EN R2 5kΩ 18 5kΩ 9 R2IN R1IN GND 16 SHDN VCC C1 0.1µF C2 0.1µF TTL/CMOS LOGIC LEVELS C15 + C2+ 6 C211 T1 2 + 4 V- 7 13 T1IN R1OUT T1IN TTL/CMOS LOGIC LEVELS T2IN 9 R1 1 EN FORCEOFF 12 FORCEON GND 14 INVALID 5kΩ 8 16 10 R1OUT 13 VCC TO POWER CONTROL LOGIC NOTE: The negative terminal of C3 can be connected to either VCC or GND NOTE: The negative terminal of C3 can be connected to either VCC or GND ICL3223 +3.3V + 0.1µF 2 + 4 5 + 6 13 12 C1+ C1C2+ C2T1 T2 19 VCC V+ 3 + C3 0.1µF C4 0.1µF + T1OUT T1IN RS-232 LEVELS T2OUT TTL/CMOS LOGIC LEVELS T2IN +3.3V ICL3232 C3 (OPTIONAL CONNECTION, NOTE) + 16 VCC V+ 2 + C3 0.1µF C4 0.1µF + T1OUT T2OUT VT1 T2 6 14 7 13 R1 R2OUT VCC TO POWER CONTROL LOGIC 9 R2 GND 15 5kΩ 5kΩ 8 R2IN R1IN + 0.1µF 1 + + 3 4 5 11 10 C1+ C1C2+ C2- C1 0.1µF C2 0.1µF V- 7 17 8 C1 0.1µF C2 0.1µF T1IN TTL/CMOS LOGIC LEVELS T2IN R1OUT 15 R1 5kΩ 16 R1IN R2OUT 10 1 EN R2 5kΩ 9 R1OUT 12 R2IN FORCEOFF 14 FORCEON GND 18 INVALID 20 11 NOTE: The negative terminal of C3 can be connected to either VCC or GND 6 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Typical Operating Circuits ICL3241 +3.3V +3.3V + 0.1µF 26 VCC V+ 27 + C3 0.1µF C4 0.1µF + T1OUT RS-232 LEVELS T2OUT T3OUT 21 20 TTL/CMOS LOGIC LEVELS 19 R1 R2OUT 18 R2 17 R3OUT R3 16 R4OUT R4 15 R5OUT 23 22 EN R5 5kΩ 5kΩ 8 R5IN R5OUT 5kΩ 7 R4IN 15 23 R5 FORCEON 5kΩ 5kΩ RS-232 LEVELS 6 R3IN 17 R3OUT R3 R4OUT 16 R4 5kΩ 8 R5IN 5kΩ 7 R4IN 5kΩ 5 R2IN 4 R2OUTB 19 R1IN R1OUT R1 18 R2 5kΩ RS-232 LEVELS 6 R3IN 5kΩ 5 R2IN 4 R1IN + (Continued) ICL3243 0.1µF 28 C1+ C1C2+ C2- 26 VCC 27 V+ 3 + C3 0.1µF C1 0.1µF C2 0.1µF 28 C1+ + 24 C11 C2+ + 2 C214 13 12 C1 0.1µF C2 0.1µF + 24 1 2 14 VT1 T2 T3 3 9 10 11 + VT1 C4 0.1µF + T1OUT RS-232 LEVELS T1IN T2IN T3IN R1OUTB TTL/CMOS LOGIC LEVELS R2OUTB R1OUT T1IN 9 T2IN T3IN 13 12 T2 10 11 T2OUT T3OUT T3 20 R2OUT TO POWER CONTROL LOGIC VCC 22 21 FORCEOFF INVALID GND 25 VCC SHDN GND 25 7 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Absolute Maximum Ratings VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V ROUT, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Information Thermal Resistance (Typical, Note 3) θJA (°C/W) Operating Conditions Temperature Range ICL32XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C ICL32XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C 16 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 90 18 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 80 20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 77 16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . . 100 16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . . 115 18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75 28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75 16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135 20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 122 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 145 20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140 28 Ld SSOP and TSSOP Packages . . . . . . . . . . . . 100 Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC, SSOP, TSSOP - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = 25°C TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS PARAMETER DC CHARACTERISTICS Supply Current, Automatic Powerdown Supply Current, Powerdown Supply Current, Automatic Powerdown Disabled All RIN Open, FORCEON = GND, FORCEOFF = VCC (ICL3221, ICL3223, ICL3243 Only) FORCEOFF = SHDN = GND (Except ICL3232) All Outputs Unloaded, FORCEON = FORCEOFF = SHDN = VCC VCC = 3.15V, ICL3221-32 VCC = 3.0V, ICL3241-43 25 25 25 25 - 1.0 1.0 0.3 0.3 10 10 1.0 1.0 µA µA mA mA LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low Input Logic Threshold High TIN, FORCEON, FORCEOFF, EN, SHDN TIN, FORCEON, FORCEOFF, EN, VCC = 3.3V SHDN VCC = 5.0V TIN, FORCEON, FORCEOFF, EN, SHDN FORCEOFF = GND or EN = VCC IOUT = 1.6mA IOUT = -1.0mA ICL32XX Powers Up (See Figure 6) ICL32XX Powers Down (See Figure 6) IOUT = 1.6mA IOUT = -1.0mA Full Full Full Full Full Full Full 2.0 2.4 ±0.01 ±0.05 0.8 ±1.0 ±10 0.4 V V V µA µA V V Input Leakage Current Output Leakage Current (Except ICL3232) Output Voltage Low Output Voltage High VCC -0.6 VCC -0.1 -2.7 -0.3 VCC-0.6 - AUTOMATIC POWERDOWN (ICL3221, ICL3223, ICL3243 Only, FORCEON = GND, FORCEOFF = VCC) Receiver Input Thresholds to Enable Transmitters Receiver Input Thresholds to Disable Transmitters INVALID Output Voltage Low INVALID Output Voltage High Full Full Full Full 2.7 0.3 0.4 V V V V 8 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified. Typicals are at TA = 25°C (Continued) TEST CONDITIONS TEMP (°C) 25 25 MIN TYP 100 1 MAX UNITS µs µs PARAMETER Receiver Threshold to Transmitters Enabled Delay (tWU) Receiver Positive or Negative Threshold to INVALID High Delay (tINVH) Receiver Positive or Negative Threshold to INVALID Low Delay (tINVL) RECEIVER INPUTS Input Voltage Range Input Threshold Low VCC = 3.3V VCC = 5.0V Input Threshold High VCC = 3.3V VCC = 5.0V Input Hysteresis Input Resistance TRANSMITTER OUTPUTS Output Voltage Swing Output Resistance Output Short-Circuit Current Output Leakage Current 25 - 30 - µs Full 25 25 25 25 25 25 -25 0.6 0.8 3 1.2 1.5 1.5 1.8 0.3 5 25 2.4 2.4 7 V V V V V V kΩ All Transmitter Outputs Loaded with 3kΩ to Ground VCC = V+ = V- = 0V, Transmitter Output = ±2V VOUT = ±12V, VCC = 0V or 3V to 5.5V Automatic Powerdown or FORCEOFF = SHDN = GND Full Full Full Full ±5.0 300 - ±5.4 10M ±35 - ±60 ±25 V Ω mA µA MOUSE DRIVEABILITY (ICL324X Only) Transmitter Output Voltage (See Figure 9) TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay RL = 3kΩ, CL = 1000pF, One Transmitter Switching Receiver Input to Receiver Output, CL = 150pF tPHL tPLH Full 25 25 25 25 Full Full CL = 200pF to 2500pF CL = 200pF to 1000pF 25 25 250 4 6 500 0.3 0.3 200 200 200 100 8.0 1000 500 30 30 kbps µs µs ns ns ns ns V/µs V/µs T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kΩ to GND, T1OUT and T2OUT Loaded with 2.5mA Each Full ±5 V Receiver Output Enable Time Receiver Output Disable Time Transmitter Skew Receiver Skew Transition Region Slew Rate Normal Operation (Except ICL3232) Normal Operation (Except ICL3232) tPHL - tPLH tPHL - tPLH VCC = 3.3V, RL = 3kΩ to 7kΩ, Measured From 3V to -3V or -3V to 3V ESD PERFORMANCE RS-232 Pins (TOUT, RIN) Human Body Model ICL3221 - ICL3243 25 25 25 25 25 ±15 ±8 ±8 ±6 ±2 kV kV kV kV kV IEC61000-4-2 Contact Discharge ICL3221 - ICL3243 IEC61000-4-2 Air Gap Discharge ICL3221 - ICL3232 ICL3241 - ICL3243 All Other Pins Human Body Model ICL3221 - ICL3243 9 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Detailed Description ICL32XX interface ICs operate from a single +3V to +5.5V supply, guarantee a 250kbps minimum data rate, require only four small external 0.1µF capacitors, feature low power consumption, and meet all ElA RS-232C and V.28 specifications. The circuit is divided into three sections: charge pump, transmitters and receivers. The ICL3221/22/23/41 inverting receivers disable only when EN is driven high. ICL3243 receivers disable during forced (manual) powerdown, but not during automatic powerdown (See Table 2). ICL324X monitor receivers remain active even during manual powerdown and forced receiver disable, making them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral’s protection diodes (See Figures 2 and 3). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure 3. VCC RXIN -25V ≤ VRIN ≤ +25V GND 5kΩ RXOUT GND ≤ VROUT ≤ VCC Charge-Pump Intersil’s new ICL32XX family utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions at VCC = 3.3V. See the Capacitor Selection section, and Table 3 for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings. FIGURE 1. INVERTING RECEIVER CONNECTIONS Low Power Operation These 3V devices require a nominal supply current of 0.3mA, even at VCC = 5.5V, during normal operation (not in powerdown mode). This is considerably less than the 5mA to 11mA current required by comparable 5V RS-232 devices, allowing users to reduce system power simply by switching to this new family. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 output levels. Coupled with the on-chip ±5.5V supplies, these transmitters deliver true RS-232 levels over a wide range of single supply system voltages. Except for the ICL3232, all transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (See Table 2). These outputs may be driven to ±12V when disabled. All devices guarantee a 250kbps data rate for full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one transmitter operating at full speed. Under more typical conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one transmitter easily operates at 900kbps. Transmitter inputs float if left unconnected, and may cause ICC increases. Connect unused inputs to GND for the best performance. Pin Compatible Replacements For 5V Devices The ICL3221/22/32 are pin compatible with existing 5V RS-232 transceivers - see the Features section on the front page for details. This pin compatibility coupled with the low Icc and wide operating supply range, make the ICL32XX potential lower power, higher performance drop-in replacements for existing 5V applications. As long as the ±5V RS-232 output swings are acceptable, and transmitter input pull-up resistors aren’t required, the ICL32XX should work in most 5V applications. When replacing a device in an existing 5V application, it is acceptable to terminate C3 to VCC as shown on the Typical Operating Circuit. Nevertheless, terminate C3 to GND if possible, as slightly better performance results from this configuration. Receivers All the ICL32XX devices contain standard inverting receivers that three-state (except for the ICL3232) via the EN or FORCEOFF control lines. Additionally, the two ICL324X products include noninverting (monitor) receivers (denoted by the ROUTB label) that are always active, regardless of the state of any control lines. All the receivers convert RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ input impedance (See Figure 1) even if the power is off (VCC = 0V). The receivers’ Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. 10 Powerdown Functionality (Except ICL3232) The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to VCC, V- collapses to GND), and the transmitter outputs three-state. Inverting receiver outputs may or may not disable in powerdown; refer to Table 2 for details. This micro-power mode makes these devices ideal for battery powered and portable applications. FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Software Controlled (Manual) Powerdown Most devices in the ICL32XX family provide pins that allow the user to force the IC into the low power, standby state. On the ICL3222 and ICL3241, the powerdown control is via a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into its powerdown state. Connect SHDN to VCC if the powerdown function isn’t needed. Note that all the receiver outputs remain enabled during shutdown (See Table 2). For the lowest power consumption during powerdown, the receivers should also be disabled by driving the EN input high (See next section, and Figures 2 and 3). The ICL3221, ICL3223, and ICL3243 utilize a two pin approach where the FORCEON and FORCEOFF inputs determine the IC’s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high. To switch between active and powerdown modes, under logic or software control, only the FORCEOFF input need be driven. The FORCEON state isn’t critical, as FORCEOFF dominates over FORCEON. Nevertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the automatic powerdown circuitry. ICL3243 inverting (standard) receiver outputs also disable when the device is in manual powerdown, thereby eliminating the possible current path through a shutdown peripheral’s input protection diode (See Figures 2 and 3). TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE RS-232 SIGNAL PRESENT AT RECEIVER INPUT? FORCEOFF (NOTE 4) ROUTB OR SHDN FORCEON EN TRANSMITTER RECEIVER INVALID INPUT INPUT INPUT OUTPUTS OUTPUTS OUTPUTS OUTPUT MODE OF OPERATION ICL3222, ICL3241 N.A. N.A. N.A. N.A. ICL3221, ICL3223 No No Yes Yes No No Yes Yes No No ICL3243 No Yes No Yes No NOTE: 4. Applies only to the ICL3241 and ICL3243. H H H L L H L L X X N.A. N.A. N.A. N.A. N.A. Active Active High-Z High-Z High-Z Active Active Active High-Z High-Z Active Active Active Active Active L H L H L Normal Operation (Auto Powerdown Disabled) Normal Operation (Auto Powerdown Enabled) Powerdown Due to Auto Powerdown Logic Manual Powerdown Manual Powerdown H H H H H H L L L L H H L L L L X X X X L H L H L H L H L H Active Active Active Active High-Z High-Z High-Z High-Z High-Z High-Z Active High-Z Active High-Z Active High-Z Active High-Z Active High-Z N.A. N.A. N.A. N.A. N.A. N.A. N.A. N.A. N.A. N.A. L L H H L L H H L L Normal Operation (Auto Powerdown Disabled) Normal Operation (Auto Powerdown Enabled) Powerdown Due to Auto Powerdown Logic Manual Powerdown Manual Powerdown w/Rcvr. Disabled Manual Powerdown Manual Powerdown w/Rcvr. Disabled L L H H N.A. N.A. N.A. N.A. L H L H High-Z High-Z Active Active Active High-Z Active High-Z Active Active Active Active N.A. N.A. N.A. N.A. Manual Powerdown Manual Powerdown w/Rcvr. Disabled Normal Operation Normal Operation w/Rcvr. Disabled 11 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 The INVALID output always indicates whether or not a valid RS-232 signal is present at any of the receiver inputs (See Table 2), giving the user an easy way to determine when the interface block should power down. In the case of a disconnected interface cable where all the receiver inputs are floating (but pulled to GND by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to GND (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the automatic powerdown feature, enabling them to function as a manual SHUTDOWN input (See Figure 4). VCC VCC CURRENT FLOW VOUT = VCC Rx POWERED DOWN UART Tx GND SHDN = GND OLD RS-232 CHIP POWER MANAGEMENT UNIT MASTER POWERDOWN LINE 0.1µF 1MΩ FORCEOFF PWR MGT LOGIC FORCEON INVALID ICL3221/23/43 I/O UART CPU FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT VCC With any of the above control schemes, the time required to exit powerdown, and resume transmission is only 100µs. A mouse, or other application, may need more time to wake up from shutdown. If automatic powerdown is being utilized, the RS-232 device will reenter powerdown if valid receiver levels aren’t reestablished within 30µs of the ICL32XX powering up. Figure 5 illustrates a circuit that keeps the ICL32XX from initiating automatic powerdown for 100ms after powering up. This gives the slow-to-wake peripheral circuit time to reestablish valid RS-232 output levels. FIGURE 2. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL VCC TRANSITION DETECTOR TO WAKE-UP LOGIC VCC R2OUTB RX POWERED DOWN UART VOUT = HI-Z R2OUT TX T1IN T1OUT FORCEOFF = GND OR SHDN = GND, EN = VCC R2IN ICL324X FORCEOFF FORCEON ICL3221/23/43 FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR 100ms AFTER FORCED POWERUP Automatic Powerdown (ICL3221/23/43 Only) Even greater power savings is available by using the devices which feature an automatic powerdown function. When no valid RS-232 voltages (See Figure 6) are sensed on any receiver input for 30µs, the charge pump and transmitters powerdown, thereby reducing supply current to 1µA. Invalid receiver levels occur whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is disconnected. The ICL32XX powers back up whenever it detects a valid RS-232 voltage level on any receiver input. This automatic powerdown feature provides additional system power savings without changes to the existing operating system. FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN 12 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 VALID RS-232 LEVEL - ICL32XX IS ACTIVE INDETERMINATE - POWERDOWN MAY OR MAY NOT OCCUR 0.3V INVALID LEVEL - POWERDOWN OCCURS AFTER 30ms -0.3V INDETERMINATE - POWERDOWN MAY OR MAY NOT OCCUR -2.7V VALID RS-232 LEVEL - ICL32XX IS ACTIVE 2.7V (standard) receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down (VCC = GND) peripheral (See Figure 2). The enable input has no effect on transmitter nor monitor (ROUTB) outputs. Capacitor Selection The charge pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages refer to Table 3 for capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without increasing C1’s value, however, do not increase C1 without also increasing C2, C3, and C4 to maintain the proper ratios (C1 to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-. TABLE 3. REQUIRED CAPACITOR VALUES VCC (V) 3.0 to 3.6 4.5 to 5.5 3.0 to 5.5 C1 (µF) 0.1 0.047 0.1 C2, C3, C4 (µF) 0.1 0.33 0.47 FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS Automatic powerdown operates when the FORCEON input is low, and the FORCEOFF input is high. Tying FORCEON high disables automatic powerdown, but manual powerdown is always available via the overriding FORCEOFF input. Table 2 summarizes the automatic powerdown functionality. Devices with the automatic powerdown feature include an INVALID output signal, which switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 30µs (See Figure 7). INVALID switches high 1µs after detecting a valid RS-232 level on a receiver input. INVALID operates in all modes (forced or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry. When automatic powerdown is utilized, INVALID = 0 indicates that the ICL32XX is in powerdown mode. RECEIVER INPUTS TRANSMITTER OUTPUTS VCC 0 V+ VCC 0 VINVALID } REGION Power Supply Decoupling In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect the bypass capacitor as close as possible to the IC. INVALID OUTPUT tINVL AUTOPWDN tINVH PWR UP Operation Down to 2.7V ICL32XX transmitter outputs meet RS-562 levels (±3.7V), at full data rate, with VCC as low as 2.7V. RS-562 levels typically ensure interoperability with RS-232 devices. FIGURE 7. AUTOMATIC POWERDOWN AND INVALID TIMING DIAGRAMS Transmitter Outputs when Exiting Powerdown Figure 8 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V. The time to recover from automatic powerdown mode is typically 100µs. Receiver ENABLE Control (ICL3221/22/23/41 Only) Several devices also feature an EN input to control the receiver outputs. Driving EN high disables all the inverting 13 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver. VCC 0.1µF 2V/DIV + C1 C1+ C1T2 VCC = +3.3V C1 - C4 = 0.1µF TIME (20µs/DIV) C2 + ICL32XX C2+ C2TIN ROUT EN VCC SHDN OR FORCEOFF TOUT RIN 5K 1000pF VVCC V+ + C3 + 5V/DIV FORCEOFF T1 C4 + FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN Mouse Driveability The ICL324X have been specifically designed to power a serial mouse while operating from low voltage supplies. Figure 9 shows the transmitter output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least ±5V during worst case conditions (15mA for paralleled V+ transmitters, 7.3mA for single V- transmitter). The Automatic Powerdown feature does not work with a mouse, so FORCEOFF and FORCEON should be connected to VCC. 6 TRANSMITTER OUTPUT VOLTAGE (V) 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0 1 2 3 4 5 6 7 8 9 10 5V/DIV. T1IN VCC VCC = 3.0V T1 VOUT+ T2 ICL3241/43 T3 VOUT VOUT VOUT+ FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT 5V/DIV T1IN T1OUT R1OUT VCC = +3.3V C1 - C4 = 0.1µF 5µs/DIV FIGURE 11. LOOPBACK TEST AT 120kbps LOAD CURRENT PER TRANSMITTER (mA) FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL VOUT+ CURRENT) T1OUT High Data Rates The ICL32XX maintain the RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 10 details a transmitter loopback test circuit, and Figure 11 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 12 shows the loopback results R1OUT VCC = +3.3V C1 - C4 = 0.1µF 2µs/DIV. FIGURE 12. LOOPBACK TEST AT 250kbps FN4805.21 March 1, 2006 14 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Interconnection with 3V and 5V Logic The ICL32XX directly interface with 5V CMOS and TTL logic families. Nevertheless, with the ICL32XX at 3.3V, and the logic supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX inputs, but ICL32XX outputs do not reach the minimum VIH for these logic families. See Table 4 for more information. TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES VCC SYSTEM POWER-SUPPLY SUPPLY VOLTAGE VOLTAGE (V) (V) 3.3 5 5 3.3 5 3.3 COMPATIBILITY Compatible with all CMOS families. Compatible with all TTL and CMOS logic families. Compatible with ACT and HCT CMOS, and with TTL. ICL32XX outputs are incompatible with AC, HC, and CD4000 CMOS inputs. Typical Performance Curves 6 TRANSMITTER OUTPUT VOLTAGE (V) VCC = 3.3V, TA = 25°C 25 VOUT+ 4 20 2 0 -2 -4 -6 VOUT 5 1 TRANSMITTER AT 250kbps 1 OR 2 TRANSMITTERS AT 30kbps SLEW RATE (V/µs) 15 -SLEW +SLEW 10 0 1000 2000 3000 4000 5000 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE FIGURE 14. SLEW RATE vs LOAD CAPACITANCE 45 40 SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 0 0 1000 2000 3000 4000 5000 20kbps 120kbps ICL3221 SUPPLY CURRENT (mA) 45 40 250kbps 35 30 25 20 15 10 5 0 0 1000 2000 3000 4000 5000 20kbps 120kbps ICL3222 - ICL3232 250kbps LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA 15 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Typical Performance Curves 45 40 SUPPLY CURRENT (mA) 35 30 25 20 20kbps 15 10 5 0 0 1000 2000 3000 4000 5000 120kbps VCC = 3.3V, TA = 25°C (Continued) 3.5 ICL324X 250kbps SUPPLY CURRENT (mA) 3.0 ICL3221 - ICL3232 2.5 2.0 1.5 1.0 0.5 ICL324X 0 2.5 3.0 3.5 4.0 4.5 NO LOAD ALL OUTPUTS STATIC ICL324X 5.0 5.5 6.0 LOAD CAPACITANCE (pF) SUPPLY VOLTAGE (V) FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ICL3221: 286 ICL3222: 338 ICL3223: 357 ICL3232: 296 ICL324X: 464 PROCESS: Si Gate CMOS 16 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 17 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Dual-In-Line Plastic Packages (PDIP) N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E E18.3 (JEDEC MS-001-BC ISSUE D) 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.115 0.014 0.045 0.008 0.845 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.880 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 21.47 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 22.35 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 2 11/03 eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3 may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 18 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 18 2.93 18 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 5.80 0.25 0.40 16 8° 0° 8° MAX 1.75 0.25 0.51 0.25 10.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 0.2284 0.0099 0.016 16 0° MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 0.2440 0.0196 0.050 A1 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 19 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D E1 A2 c 0.10(0.004) C AM BS MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8o Rev. 1 2/02 MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 e b 0.10(0.004) M α A1 e E L N 0.026 BSC 0.246 0.020 16 0o 8o 0.256 0.028 0.65 BSC 6.25 0.50 16 0o 6.50 0.70 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α 20 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Small Outline Plastic Packages (SSOP) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 L GAUGE PLANE 0.25(0.010) M BM M16.209 (JEDEC MO-150-AC ISSUE B) 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E A2 C 0.10(0.004) C AM BS MILLIMETERS MIN 0.05 1.65 0.22 0.09 5.90 5.00 7.40 0.55 16 8° 0° 8° Rev. 3 MAX 2.00 1.85 0.38 0.25 6.50 5.60 8.20 0.95 NOTES 9 3 4 6 7 6/05 MIN 0.002 0.065 0.009 0.004 0.233 0.197 0.292 0.022 16 0° MAX 0.078 0.072 0.014 0.009 0.255 0.220 0.322 0.037 α A1 e B 0.25(0.010) M e H L N 0.026 BSC 0.65 BSC NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 21 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 10.00 0.25 0.40 16 8° 0° 8° MAX 2.65 0.30 0.51 0.32 10.50 7.60 10.65 0.75 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914 0.394 0.010 0.016 16 0° MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992 0.419 0.029 0.050 A1 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 22 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45° 0.25(0.010) M BM M18.3 (JEDEC MS-013-AB ISSUE C) 18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 11.35 7.40 10.00 0.25 0.40 18 8° 0° 8° MAX 2.65 0.30 0.51 0.32 11.75 7.60 10.65 0.75 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0926 0.0040 0.013 0.0091 0.4469 0.2914 0.394 0.010 0.016 18 0° MAX 0.1043 0.0118 0.0200 0.0125 0.4625 0.2992 0.419 0.029 0.050 A1 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 23 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 NOTES 9 3 4 6 7 8o Rev. 1 6/98 α A1 0.10(0.004) A2 c e b 0.10(0.004) M C AM BS E1 e E L N 0.026 BSC 0.246 0.0177 20 0o 8o 0.256 0.0295 0.65 BSC 6.25 0.45 20 0o 6.50 0.75 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α 24 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M20.209 (JEDEC MO-150-AE ISSUE B) 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E A2 C 0.10(0.004) C AM BS MILLIMETERS MIN 1.73 0.05 1.68 0.25 0.09 7.07 5.20’ MAX 1.99 0.21 1.78 0.38 0.20’ 7.33 5.38 3 4 9 NOTES MIN 0.068 0.002 0.066 0.010’ 0.004 0.278 0.205 MAX 0.078 0.008’ 0.070’ 0.015 0.008 0.289 0.212 e B 0.25(0.010) M α A1 e H L N 0.026 BSC 0.301 0.025 20 0 deg. 8 deg. 0.311 0.037 0.65 BSC 7.65 0.63 20 0 deg. 8 deg. Rev. 3 11/02 7.90’ 0.95 6 7 α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 25 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 MAX 0.047 0.006 0.051 0.0118 0.0079 0.386 0.177 MILLIMETERS MIN 0.05 0.80 0.19 0.09 9.60 4.30 MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 NOTES 9 3 4 6 7 8o Rev. 0 6/98 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c E1 e E L N 0.026 BSC 0.246 0.0177 28 0o 8o 0.256 0.0295 0.65 BSC 6.25 0.45 28 0o 6.50 0.75 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α 26 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 L GAUGE PLANE 0.25(0.010) M BM M28.209 (JEDEC MO-150-AH ISSUE B) 28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E A2 C 0.10(0.004) C AM BS MILLIMETERS MIN 0.05 1.65 0.22 0.09 9.90 5.00 7.40 0.55 28 8° 0° 8° MAX 2.00 1.85 0.38 0.25 10.50 5.60 8.20 0.95 NOTES 9 3 4 6 7 Rev. 2 6/05 MIN 0.002 0.065 0.009 0.004 0.390 0.197 0.292 0.022 28 0° MAX 0.078 0.072 0.014 0.009 0.413 0.220 0.322 0.037 α A1 e B 0.25(0.010) M e H L N 0.026 BSC 0.65 BSC NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 27 FN4805.21 March 1, 2006 ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 28 FN4805.21 March 1, 2006