ISL22429

® ISL22449 Quad Digitally Controlled Potentiometer (XDCP™) Data Sheet July 17, 2009 FN6333.3 Low Noise, Low Power, SPI® Bus, 128 Taps, Wiper Only The ISL22449 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the DCP’s IVR to the corresponding WR. The DCP can be used as a voltage divider in a wide variety of applications including control, parameter adjustments, AC measurement and signal processing. Features • Four potentiometers in one package • 128 resistor taps • SPI serial interface • Non-volatile storage of wiper position • Wiper resistance: 70Ω typical • Shutdown mode • Shutdown current 6.5µA max • Power supply: 2.7V to 5.5V • 50kΩ or 10kΩ total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 14 Lead TSSOP • Pb-free (RoHS compliant) Pinout ISL22449 (14 LD TSSOP) TOP VIEW RW3 NC SCK SDO GND RW2 RW1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 RW0 SHDN VCC NC SDI CS NC Ordering Information PART NUMBER (Note) ISL22449UFV14Z* ISL22449WFV14Z* PART MARKING 22449 UFVZ 22449 WFVZ RESISTANCE OPTION (kΩ) 50 10 TEMP. RANGE (°C) -40 to +125 -40 to +125 PACKAGE (Pb-free) 14 Ld TSSOP 14 Ld TSSOP PKG. DWG. # M14.173 M14.173 *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22449 Block Diagram VCC VCC SCK SDI SDO CS SPI INTERFACE POWER UP INTERFACE, CONTROL AND STATUS LOGIC WR3 VCC RW3 WR2 VCC RW2 WR1 SHDN NONVOLATILE REGISTERS VCC RW1 WR0 RW0 GND Pin Descriptions TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL RW3 NC SCK SDO GND RW2 RW1 NC CS SDI NC VCC SHDN RW0 Power supply pin and the RH connection for each DCP Shutdown active low input “Wiper” terminal of DCP0 SPI Chip Select active low input SPI data input SPI clock input SPI open drain data output Device ground pin and the RL connection for each DCP “Wiper” terminal of DCP2 “Wiper” terminal of DCP1 “Wiper” terminal of DCP3 DESCRIPTION 2 FN6333.3 July 17, 2009 ISL22449 Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 2) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) 14 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +100 Maximum Junction Temperature (Plastic Package) . . . . . . . .+150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins. Analog Specifications Over recommended operating conditions unless otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEST CONDITIONS W option U option MIN TYP (Note 3) 10 50 -20 ±50 ±80 70 25 200 +20 MAX UNIT kΩ kΩ % ppm/°C (Note 13) ppm/°C (Note 13) Ω pF SYMBOL RTOTAL PARAMETER End-to-End resistance End-to-End resistance tolerance End-to-End Temperature Coefficient W and U option W option U option RW CW (Note 13) Wiper resistance Wiper capacitance VCC = 3.3V @ +25°C, wiper current = VCC/RTOTAL VOLTAGE DIVIDER MODE (measured at RWi, unloaded; i = 0, 1, 2 or 3) INL (Note 8) DNL (Note 7) ZSerror (Note 5) Integral non-linearity Differential non-linearity Zero-scale error Monotonic over all tap positions W option U option FSerror (Note 6) Full-scale error W option U option VMATCH (Note 9) TCV (Note 10) DCP to DCP matching Ratiometric temperature coefficient Any two DCPs at same tap position DCP register set to 40 hex -1 -0.5 0 0 -5 -2 -2 ±4 1 0.5 -1 -1 1 0.5 5 2 0 0 2 LSB (Note 4) LSB (Note 4) LSB (Note 4) LSB (Note 4) LSB (Note 4) LSB (Note 4) LSB (Note 4) ppm/°C 3 FN6333.3 July 17, 2009 ISL22449 Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL ICC1 PARAMETER VCC Supply Current (volatile write/read) VCC Supply Current (volatile write/read) ICC2 VCC Supply Current ( non-volatile write/read) VCC Supply Current ( non-volatile write/read) ISB VCC Current (standby) TEST CONDITIONS VCC = +3.6V, 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) VCC = +3.6V, 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) VCC = +5.5V, 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) VCC = +5.5V, 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) VCC = +5.5V, 10k DCP, SPI interface in standby state VCC = +5.5V, 50k DCP, SPI interface in standby state VCC = +3.6V, 10k DCP, SPI interface in standby state VCC = +3.6V, 50k DCP, SPI interface in standby state ISD VCC Current (shutdown) VCC = +5.5V @ +85°C, SPI interface in standby state VCC = +5.5V@ +125°C, SPI interface in standby state VCC = +3.6V @ +85°C, SPI interface in standby state VCC = +3.6V @ +125°C, SPI interface in standby state ILkgDig tWRT (Note 13) tShdnRec (Note 13) Leakage current, at pins SHDN, SCK, Voltage at pin from GND to VCC SDI, SDO and CS DCP wiper response time SCK falling edge of last bit of DCP data byte to wiper new position -1 1.5 1.5 1.5 2.0 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state 3 2.6 MIN TYP (Note 3) MAX 2.5 0.65 4.0 3.0 2.4 525 1.6 350 5 6.5 4 5.5 1 UNIT mA mA mA mA mA µA mA µA µA µA µA µA µA µs µs µs V V/ms ms DCP recall time from shutdown mode From rising edge of SHDN signal to wiper stored position and RH connection SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection Vpor VccRamp tD Power-on recall voltage Vcc ramp rate Power-up delay Minimum VCC at which memory recall occurs EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 11) Non-volatile Write cycle time Temperature T < +55°C 1,000,000 50 12 20 Cycles Years ms SERIAL INTERFACE SPECIFICATIONS VIL SHDN, SCK, SDI, and CS input buffer LOW voltage -0.3 0.3*VCC V 4 FN6333.3 July 17, 2009 ISL22449 Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL VIH Hysteresis VOL Rpu (Note 12) Cpin (Note 13) fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tCS tWRT NOTES: 3. Typical values are for TA = +25°C and 3.3V supply voltage. 4. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 5. ZS error = V(RW)0/LSB. 6. FS error = [V(RW)127 – VCC]/LSB. 7. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 8. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 127 9. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 10. TC = --------------------------------------------------------------------------------------------- × ---------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 12. Rpu is specified for the highest data rate transfer for the device. Higher value pullup can be used at lower data rates. 13. This parameter is not 100% tested. PARAMETER SHDN, SCK, SDI, and CS input buffer HIGH voltage SHDN, SCK, SDI, and CS input buffer hysteresis SDO output buffer LOW voltage SDO pull-up resistor off-chip IOL = 4mA Maximum is determined by tRO and tFO with maximum bus load Cbus = 30pF, fSCK = 5MHz TEST CONDITIONS MIN 0.7*VCC 0.05* VCC 0 0.4 2 TYP (Note 3) MAX VCC+0.3 UNIT V V V kΩ SHDN, SCK, SDI, SDO and CS pin capacitance SPI frequency SPI clock cycle time SPI clock high time SPI clock low time Lead time Lag time SDI, SCK and CS input setup time SDI, SCK and CS input hold time SDI, SCK and CS input rise time SDI, SCK and CS input fall time SDO output Disable time SDO output valid time SDO output hold time SDO output rise time SDO output fall time CS deselect time Wiper Response Time after SPI write to WR register Rpu = 2k, Cbus = 30pF Rpu = 2k, Cbus = 30pF 2 0 200 100 100 250 250 50 50 10 10 0 10 5 pF MHz ns ns ns ns ns ns ns ns 20 100 350 ns ns ns ns 60 60 ns ns µs 1.5 µs 5 FN6333.3 July 17, 2009 ISL22449 Timing Diagrams Input Timing tCS CS tLEAD SCK tSU SDI MSB tH tWL tCYC tLAG ... tWH tFI LSB tRI ... SDO HIGH IMPEDANCE Output Timing CS SCK tV SDO MSB tHO ... tDIS ... LSB SDI ADDR XDCP Timing (for All Load Instructions) CS SCK ... tWRT MSB SDI ... LSB VW SDO HIGH IMPEDANCE 6 FN6333.3 July 17, 2009 ISL22449 Typical Performance Curves 100 90 WIPER RESISITANCE (Ω) 80 70 ISB (µA) 60 50 40 30 20 10 0 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) VCC = 3.3V, T = +20°C VCC = 3.3V, T = -40°C 1.0 0.8 0.6 0.4 0.2 0 2.7 T = +25°C T = +125°C VCC = 3.3V, T = +125°C 1.4 1.2 3.2 3.7 4.2 VCC (V) 4.7 5.2 FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC/RTOTAL] FOR 10kΩ (W) FIGURE 2. STANDBY ICC vs VCC 0.2 T = +25°C VCC = 2.7V 0.1 DNL (LSB) INL (LSB) 0.2 T = +25°C 0.1 VCC = 2.7V 0 0 -0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) -0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 1.3 10k 1.1 0.9 ZSERROR (LSB) 0.7 0.5 0.3 0.1 -0.1 -0.3 -40 -20 0 20 50k VCC = 2.7V VCC = 5.5V ZSERROR (LSB) 0.0 -0.3 VCC = 2.7V 50k VCC = 5.5V -0.6 -0.9 10k -1.2 40 60 80 100 120 -1.5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (ºC) FIGURE 5. ZSERROR vs TEMPERATURE FIGURE 6. FSERROR vs TEMPERATURE 7 FN6333.3 July 17, 2009 ISL22449 Typical Performance Curves 1.0 END TO END RTOTAL CHANGE (%) (Continued) 105 90 0.5 VCC = 2.7V 0.0 VCC = 5.5V 10k -0.5 50k TCv (ppm/°C) 75 60 45 30 15 50k 10k -1.0 -40 0 -20 0 20 40 60 80 100 120 16 36 56 76 96 TEMPERATURE (ºC) TAP POSITION (DECIMAL) FIGURE 7. END TO END RTOTAL % CHANGE vs TEMPERATURE FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) FIGURE 9. MIDSCALE GLITCH, CODE 80h TO 7Fh FIGURE 10. LARGE SIGNAL SETTLING TIME Pin Description Potentiometers Pins RWI (I = 0, 1, 2, 3) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SHDN The SHDN pin forces the resistors to end-to-end open circuit condition and shorts all RWs to GND. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically ANDed with the SHDN bit in the ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE RW Bus Interface Pins SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. SERIAL DATA OUTPUT (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low. SDO requires an external pull-up resistor for proper operation. 8 FN6333.3 July 17, 2009 ISL22449 SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. CHIP SELECT (CS) CS LOW enables the ISL22449, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22449 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. DCP1, DCP2 or DCP3 respectively. The WRi and IVRi can be read or written to directly using the SPI serial interface as described in the following sections. Memory Description The ISL22449 contains seven non-volatile and five volatile 8bit registers. The memory map of ISL22449 is on Table 1. The four non-volatile registers (IVRi) at address 0, 1, 2 and 3, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, three non-volatile General Purpose registers from address 4 to address 6 are available. TABLE 1. MEMORY MAP ADDRESS 8 7 6 5 4 3 2 1 0 General Purpose General Purpose General Purpose IVR3 IVR2 IVR1 IVR0 NON-VOLATILE — Reserved Not Available Not Available Not Available WR3 WR2 WR1 WR0 VOLATILE ACR Principles of Operation The ISL22449 is an integrated circuit incorporating four DCPs with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometers and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi is recalled and loaded into the corresponding WRi to set the wiper to the initial value. The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit (ACR[7]) determines whether the access is to wiper registers WR or initial value registers IVR. TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # Bit Name DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer and internally connected to Vcc and GND. The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest to GND. When the WR register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper terminal (RW) is closest to VCC. As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to GND to the closest to VCC. While the ISL22449 is being powered up, all four WRs are reset to 40h (64 decimal), which locates RW roughly at the center between GND and VCC. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). The SPI interface register address bits have to be set to 0000b, 0001b, 0010b or 0011b to access the WR of DCP0, 7 VOL 6 SHDN 5 WIP 4 0 3 0 2 0 1 0 0 0 If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WRi is accessible. Note, value is written to IVRi register also is written to the WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically AND with SHDN pin. When this bit is 0, DCPs are in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write to the IVRi, WRi or ACR while WIP bit is 1. Shutdown Mode The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3. 9 FN6333.3 July 17, 2009 ISL22449 TABLE 3. SHDN pin High Low High Low SHDN bit 1 1 0 0 Mode Normal operation Shutdown Shutdown Shutdown Write Operation A Write operation to the ISL22449 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte following by Data Byte is sent to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. For a write to addresses 0000b to 0011b, the MSB at address 8 (ACR[7]) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to “Memory Description” on page 9 and Figure 12. Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 0110b, the internal pointer “rolls over” to address 0000b. The internal non-volatile write cycle starts after rising edge of CS and takes up to 20ms. Thus, non-volatile registers must be written individually. SPI Serial Interface The ISL22449 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22449. SCK and CS lines are controlled by the host or master. The ISL22449 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. Read Operation A read operation to the ISL22449 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte following by “dummy” Data Byte is sent to SDI pin. The SPI host reads the data from SDO pin on falling edge of SCK. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 13). The ISL22449 will provide the Data Bytes to the SDO pin as long as SCK is provided by the host from the registers indicated by an internal pointer. This pointer initial value is determined by the register address in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 0110b, the pointer “rolls over” to 0000b, and the device continues to output the data for each received SCK clock. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. Protocol Conventions The first byte sent to the ISL22449 from the SPI host is the Identification Byte. A valid Identification Byte contains 0101 as the four MSBs, with the following four bits set to 0. TABLE 4. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 0 0 0 0 (LSB) The next byte sent to the ISL22449 contains the instruction and register pointer information. The four MSBs are the instruction and four LSBs are register address (see Table 5). TABLE 5. IDENTIFICATION BYTE FORMAT 7 I3 6 I2 5 I1 4 I0 3 R3 2 R2 1 R1 0 R0 There are only two valid instruction sets: 1011(binary) - is a Read operation 1100(binary) - is a Write operation 10 FN6333.3 July 17, 2009 ISL22449 CS SCK SDI 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0 0 D6 D5 D4 D3 D2 D1 D0 FIGURE 12. THREE BYTE WRITE SEQUENCE CS SCK SDI 0 SDO 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0 DON’T CARE D6 D5 D4 D3 D2 D1 D0 FIGURE 13. THREE BYTE READ SEQUENCE Applications Information Communicating with ISL22449 Communication with ISL22449 proceeds using SPI interface through the ACR (address 1000b), IVRi (addresses 0000b, 0001b, 0010b and 0011b) and WRi (addresses 0000b, 0001b, 0010b and 0011b) registers. The wiper of the potentiometer is controlled by the WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 1000b to 1. The non-volatile IVRi stores the power up value of the wiper. IVRs are accessible when MSB bit at address 1000b is set to 0. Writing a new value to the IVRi register will set a new power up position for the wiper. Also, writing to this register will load the same value into the corresponding WRi as the IVRi. Reading from the IVRi will not change the WRi, if its contents are different. 11 FN6333.3 July 17, 2009 ISL22449 Examples: A. Writing to the IVR: This sequence will write a new value (77h) to the IVR2(non-volatile): Set the ACR (Addr 1000b) for NV write (40h) Send the ID byte, Instruction Byte, then the Data byte 010100001100100 Set the IVR (Addr 0010b) to 77h Send the ID byte, Instruction Byte, then the Data byte 010100001100001 0 0100 (Sent to SDI) 0 0 0 0 0 0111 (Sent to SDI) 0 1 1 1 B. Reading from the WR: This sequence will read the value from the WR3 (volatile): W rite to ACR first to access the volatile WRs Send the ID byte, Instruction Byte, then the Data byte 010100001100100 0 1100 (Sent to SDI) 0 0 0 0 Read the data from WR3 (Addr 0011b) Send the ID byte, Instruction Byte, then Read the Data byte 0101000010110011xxxxx (Out on SDO) x x x 12 FN6333.3 July 17, 2009 ISL22449 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c D E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6333.3 July 17, 2009