ISL23428

Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) ISL23428 The ISL23428 is a volatile, low voltage, low noise, low power, 128-tap, dual digitally controlled potentiometer (DCP) with an SPI Bus™ interface. It integrates two DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (64 tap position). The low voltage, low power consumption, and small package of the ISL23428 make it an ideal choice for use in battery operated equipment. In addition, the ISL23428 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23428 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Two potentiometers per package • 128 resistor taps • 10k 50kor 100k total resistance • SPI serial interface - No additional level translator for low bus supply - Daisy Chaining of multiple DCPs • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V SPI bus/logic power supply • Maximum supply current without serial bus activity (standby) - 4µA @ VCC and VLOGIC = 5V - 1.7µA @ VCC and VLOGIC = 1.7V • Shutdown Mode - Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally - Reduces power consumption by disconnecting the DCP resistor from the circuit • Wiper resistance: 70 typical @ VCC = 3.3V • Power-on preset to mid-scale (64 tap position) • Extended industrial temperature range: -40°C to +125°C • 14 Ld TSSOP or 16 Ld UTQFN packages • Pb-free (RoHS compliant) Applications • Power supply margining • Trimming sensor circuits • Gain adjustment in battery powered instruments • RF power amplifier bias compensation 10000 VREF 8000 RESISTANCE (Ω) 6000 RH ISL23428 RW + ISL28114 RL VREF_M 4000 2000 0 0 32 64 TAP POSITION (DECIMAL) 96 128 FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP FIGURE 2. VREF ADJUSTMENT August 25, 2011 FN7904.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners ISL23428 Block Diagram VLOGIC VCC RH0 RH1 SCK SDI SDO CS SPI INTERFACE POWER UP INTERFACE, CONTROL AND STATUS LOGIC WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY WR1 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY GND RW0 RL0 RW1 RL1 Pin Configurations ISL23428 (14 LD TSSOP) TOP VIEW GND VLOGIC SDO SCK SDI CS GND 1 2 3 4 5 6 7 14 VCC 13 RL0 12 RW0 11 RH0 10 RH1 9 8 RW1 RL1 Pin Descriptions TSSOP 1, 7 2 3 4 5 6 8 9 10 UTQFN 5, 6, 15 16 1 2 3 4 8 9 10 11 12 13 14 7 SYMBOL GND VLOGIC SDO SCK SDI CS RL1 RW1 RH1 RH0 RW0 RL0 VCC NC Ground pin SPI bus/logic supply Range 1.2V to 5.5V Logic Pin - Serial bus data output (configurable) Logic Pin - Serial bus clock input Logic Pin - Serial bus data input Logic Pin - Active low chip select DCP1 “low” terminal DCP1 wiper terminal DCP1 “high” terminal DCP0 “high” terminal DCP0 wiper terminal DCP0 “low” terminal Analog power supply. Range 1.7V to 5.5V Not Connected DESCRIPTION ISL23428 (16 LD UTQFN) TOP VIEW VLOGIC GND VCC RL0 11 12 13 14 RW0 RH0 RH1 RW1 16 15 14 7 NC SDO SCK SDI CS 1 2 3 4 5 6 13 12 11 10 9 8 RL1 GND GND 2 FN7904.0 August 25, 2011 ISL23428 Ordering Information PART NUMBER (Note 4) ISL23428TFVZ (Note 2) ISL23428TFVZ-T7A (Notes 1, 2) ISL23428TFVZ-TK (Notes 1, 2) ISL23428UFVZ (Note 2) ISL23428UFVZ-T7A (Notes 1, 2) ISL23428UFVZ-TK (Notes 1, 2) 23425WFVZ (Note 2) 23425WFVZ-T7A (Notes 1, 2) 23425WFVZ-TK (Notes 1, 2) ISL23428TFRUZ-T7A (Notes 1, 3) ISL23428TFRUZ-TK (Notes 1, 3) ISL23428UFRUZ-T7A (Notes 1, 3) ISL23428UFRUZ-TK (Notes 1, 3) ISL23428WFRUZ-T7A (Notes 1, 3) ISL23428WFRUZ-TK (Notes 1, 3) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL23428. For more information on MSL please see techbrief TB363. PART MARKING 23428 TFVZ 23428 TFVZ 23428 TFVZ 23428 UFVZ 23428 UFVZ 23428 UFVZ 23428 WFVZ 23428 WFVZ 23428 WFVZ GBR GBR GBP GBP GBN GBN RESISTANCE OPTION (kΩ) 100 100 100 50 50 50 10 10 10 100 100 50 50 10 10 TEMP RANGE (°C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 16 Ld 2.6x1.8 UTQFN 16 Ld 2.6x1.8 UTQFN 16 Ld 2.6x1.8 UTQFN 16 Ld 2.6x1.8 UTQFN 16 Ld 2.6x1.8 UTQFN 16 Ld 2.6x1.8 UTQFN PKG. DWG. # M14.173 M14.173 M14.173 M14.173 M14.173 M14.173 M14.173 M14.173 M14.173 L16.2.6x1.8A L16.2.6x1.8A L16.2.6x1.8A L16.2.6x1.8A L16.2.6x1.8A L16.2.6x1.8A 3 FN7904.0 August 25, 2011 ISL23428 Absolute Maximum Ratings Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .4.5kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Thermal Information Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 14 Ld TSSOP Package (Notes 5, 6) . . . . . . 112 40 16 Ld UTQFN Package (Notes 5, 6) . . . . . . 110 64 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the “case temp” location is the center top of the package. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL RTOTAL PARAMETER RH to RL Resistance W option U option T option RH to RL Resistance Tolerance End-to-End Temperature Coefficient W option U option T option VRH, VRL RW DCP Terminal Voltage Wiper Resistance VRH or VRL to GND RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V VCC = 1.7V CH/CL/CW Terminal Capacitance ILkgDCP Noise Leakage on DCP Pins Resistor Noise Density See “DCP Macro Model” on page 9 Voltage at pin from GND to VCC Wiper at middle point, W option Wiper at middle point, U option Wiper at middle point, T option Feed Thru Digital Feed-through from Bus to Wiper PSRR Power Supply Reject Ratio Wiper at middle point Wiper output change if VCC change ±10%; wiper at middle point -0.4 0 70 -20 TEST CONDITIONS MIN (Note 19) TYP (Note 7) 10 50 100 ±2 125 65 45 VCC 200 +20 MAX (Note 19) UNITS kΩ kΩ kΩ % ppm/°C ppm/°C ppm/°C V Ω 580 32/32/32 2V IOL = 1.5mA, VLOGIC < 2V Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 10 VLOGIC = 1.7V to 5.5V VLOGIC = 1.2V to 1.6V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V VLOGIC ≥ 1.7V 200 100 100 250 250 50 50 10 10 0 50 150 0 20 100 5 1 0.05 x VLOGIC 0.1 x VLOGIC 0 0.4 0.2 x VLOGIC 1.5 TYP (Note 7) MAX (Note 19) 0.3 x VLOGIC VLOGIC+ 0.3 UNITS V V V V V V kΩ Cpin fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tSO tV tHO SCK, SDO, SDI, CS Pin Capacitance SCK Frequency SPI Clock Cycle Time SPI Clock High Time SPI Clock Low Time Lead Time Lag Time SDI, SCK and CS Input Setup Time SDI, SCK and CS Input Hold Time SDI, SCK and CS Input Rise Time SDI, SCK and CS Input Fall Time SDO Output Disable Time SDO Output Setup Time SDO Output Valid Time SDO Output Hold Time pF MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 7 FN7904.0 August 25, 2011 ISL23428 Serial Interface Specification SYMBOL tRO tFO tCS NOTES: For SCK, SDI, SDO, CS Unless Otherwise Noted. (Continued) TEST CONDITIONS Rpu = 1.5k, Cbus = 30pF Rpu = 1.5k, Cbus = 30pF 2 MIN (Note 19) TYP (Note 7) MAX (Note 19) 60 60 UNITS ns ns µs PARAMETER SDO Output Rise Time SDO Output Fall Time CS Deselect Time 7. Typical values are for TA = +25°C and 3.3V supply voltages. 8. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 9. ZS error = V(RW)0/LSB. 10. FS error = [V(RW)127 – VCC]/LSB. 11. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 12. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 Max  V  RW  i  – Min  V  RW  i  10 6 13. TC = -----------------------------------------------------------------------------  --------------------- for i = 8 to 127decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage V V  RW i  +25°C   +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 14. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 15. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 16. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 17. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 18.  Max  Ri  – Min  Ri   10 TC R = ------------------------------------------------------  --------------------Ri  +25°C  +165°C 6 for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the minimum value of the resistance over the temperature range. 19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 20. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible it is recommended to ramp-up the VLOGIC first followed by the VCC. 21. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 22. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 8 FN7904.0 August 25, 2011 ISL23428 DCP Macro Model RTOTAL RH CH CW CL 32pF RL 32pF RW 32pF Timing Diagrams Input Timing tCS CS tLEAD SCK tSU SDI MSB tH tWL tCYC ... tWH ... tLAG tFI LSB tRI SDO Output Timing CS SCK tSO SDO MSB tV SDI ADDR tHO ... tDIS ... LSB XDCP™ Timing (for All Load Instructions) CS tDCP SCK ... ... SDI MSB LSB VW SDO *When CS is HIGH SDO at Z or Hi-Z state 9 FN7904.0 August 25, 2011 ISL23428 Typical Performance Curves 0.20 0.04 0.10 DNL (LSB) DNL (LSB) 0.02 0.00 0.00 -0.10 -0.02 -0.20 0 32 64 TAP POSITION (DECIMAL) 96 128 -0.04 0 32 64 TAP POSITION (DECIMAL) 96 128 FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C 0.30 0.12 0.15 INL (LSB) INL (LSB) 0.09 0.00 0.06 -0.15 0.03 -0.30 0 32 64 TAP POSITION (DECIMAL) 96 128 0.00 0 32 64 TAP POSITION (DECIMAL) 96 128 FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C 0.20 0.04 0.10 RDNL (MI) RDNL (MI) 0.02 0.00 0.00 -0.10 -0.02 -0.20 0 32 64 TAP POSITION (DECIMAL) 96 128 -0.04 0 32 64 TAP POSITION (DECIMAL) 96 128 FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C 10 FN7904.0 August 25, 2011 ISL23428 Typical Performance Curves 0.30 (Continued) 0.08 0.15 RINL (MI) 0.04 RINL (MI) 0.00 0.00 -0.15 -0.04 -0.30 0 32 64 TAP POSITION (DECIMAL) 96 128 -0.08 0 32 64 TAP POSITION (DECIMAL) 96 128 FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C 100 +25°C +125°C WIPER RESISTANCE () 120 100 80 60 40 20 0 -40°C +125°C WIPER RESISTANCE () 80 +25°C 60 40 -40°C 20 0 0 32 64 96 TAP POSITION (DECIMAL) 128 0 32 64 TAP POSITION (DECIMAL) 96 128 FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 200 40 150 TCv (ppm/°C) TCv (ppm/°C) 30 100 20 50 10 0 15 43 71 99 TAP POSITION (DECIMAL) 127 0 15 43 71 TAP POSITION (DECIMAL) 99 127 FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V 11 FN7904.0 August 25, 2011 ISL23428 Typical Performance Curves 500 400 (Continued) 120 90 TCr (ppm/°C) TCr (ppm/°C) 300 60 200 100 30 0 15 43 71 TAP POSITION (DECIMAL) 99 127 0 15 43 71 99 TAP POSITION (DECIMAL) 127 FIGURE 15. 10kΩ TCr vs TAP POSITION FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V 20 120 15 TCv (ppm/°C) TCr (ppm/°C) 90 10 60 5 30 0 15 43 71 99 TAP POSITION (DECIMAL) 127 0 15 43 71 99 TAP POSITION (DECIMAL) 127 FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V SCK CLOCK WIPER CS RISING RW PIN CH1: 1V/DIV, 1µs/DIV CH2: 10mV/DIV, 1µs/DIV CH1: 20mV/DIV, 2µs/DIV CH2: 2V/DIV, 2µs/DIV   FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH 12 FN7904.0 August 25, 2011 ISL23428 Typical Performance Curves 1V/DIV 0.2µs/DIV CS RISING (Continued) 0.5V/DIV 20µs/DIV VCC WIPER WIPER   FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE CH1: RH TERMINAL CH2: RW TERMINAL STANDBY CURRENT ICC (µA) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 VCC = 1.7V, VLOGIC = 1.2V VCC = 5.5V, VLOGIC = 5.5V 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP 0 -40 -15 10 35 60 85 110 TEMPERATURE (°C) FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions Potentiometers Pins RHI AND RLI The high (RHi, i = 0, 1) and low (RLi, i = 0, 1) terminals of the ISL23428 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. Power Pins VCC Power terminal for the potentiometer section analog power source. Can be any value needed to support voltage range of DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. Bus Interface Pins SERIAL CLOCK (SCK) This input is the serial clock of the SPI serial interface. RWI RWi (i = 0, 1) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SERIAL DATA INPUT (SDI) The SDI is a serial data input pin for SPI interface. It receives operation code, wiper address and data from the SPI remote host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. 13 FN7904.0 August 25, 2011 ISL23428 SERIAL DATA OUTPUT (SDO) The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. The output type is configured through ACR[1] bit for Push-Pull or Open Drain operation. Default setting for this pin is Push-Pull. An external pull-up resistor is required for Open Drain output operation. When CS is HIGH, the SDO pin is in tri-state (Z) or high-tri-state (Hi-Z) depends on the selected configuration. the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL23428 is being powered up, both WRi are reset to 40h (64 decimal), which positions RWi at the center between RLi and RHi. The WRi can be read or written to directly using the SPI serial interface, as described in the following sections. CHIP SELECT (CS) CS LOW enables the ISL23428, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power-up. When CS is HIGH, the ISL23428 is deselected and the SDO pin is at high impedance, and the device will be in the standby state. Memory Description The ISL23428 contains three volatile 8-bit registers: Wiper Register WR0, Wiper Register WR1, and Access Control Register (ACR). Memory map of ISL23428 is shown in Table 1. The Wiper Register WR0 at address 0 contains current wiper position of DCP0; the Wiper Register WR1 at address 1 contains current wiper position of DCP1. The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. TABLE 1. MEMORY MAP ADDRESS (hex) 10 1 0 VOLATILE REGISTER NAME ACR WR1 WR0 TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # NAME/ VALUE 7 0 6 SHDN 5 0 4 0 3 0 2 0 1 SDO 0 0 DEFAULT SETTING (hex) 40 40 40 VLOGIC Digital power source for the logic control section. It supplies an internal level translator for 1.2V to 5.5V serial bus operation. Use the same supply as the I2C logic source. Principles of Operation The ISL23428 is an integrated circuit incorporating two DCPs with its associated registers and an SPI serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the SPI logic source which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has lower levels than DCP analog supply. The SDO bit (ACR[1]) configures type of SDO output pin. The default value of SDO bit is 0 for Push-Pull output. The SDO pin can be configured as Open Drain output for some applications. In this case, an external pull-up resistor is required; reference the “Serial Interface Specification” on page 7. Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e., each DCP is forced to end-to-end open circuit and each RW shorted to RL through a 2kΩ serial resistor, as shown in Figure 25. Default value of the SHDN bit is 1. RH DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WR of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RWi) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = 7Fh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE 14 FN7904.0 August 25, 2011 ISL23428 When the device enters shutdown, all current DCP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). SPI Serial Interface The ISL23428 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL23428. The SCK and CS lines are controlled by the host or master. The ISL23428 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. WIPER VOLTAGE, VRW (V) POWER-UP MID SCALE = 40H AFTER SHDN USER PROGRAMMED Protocol Conventions The SPI protocol contains Instruction Byte followed by one or more Data Bytes. A valid Instruction Byte contains instruction as the three MSBs, with the following five register address bits (see Table 3). The next byte sent to the ISL23428 is the Data Byte. TABLE 3. INSTRUCTION BYTE FORMAT BIT # 7 I2 6 I1 5 I0 4 R4 3 R3 2 R2 1 R1 0 R0 SHDN ACTIVATED SHDN RELEASED WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE Table 4 contains a valid instruction set for ISL23428. If the [R4:R0] bits are zero or one, then the read or write is to the WRi register. If the [R4:R0] are 10000, then the operation is to the ACR. TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 0 0 0 1 1 I1 0 0 1 0 1 I0 0 1 1 0 0 R4 X X X R4 R4 R3 X X X R3 R3 R2 X X X R2 R2 R1 X X X R1 R1 R0 X X X R0 R0 NOP ACR READ ACR WRTE WRi or ACR READ WRi or ACR WRTE OPERATION Where X means “do not care”. 15 FN7904.0 August 25, 2011 ISL23428 CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI WR INSTRUCTION ADDR DATA BYTE SDO FIGURE 27. TWO BYTE WRITE SEQUENCE CS 1 8 16 24 32 SCK SDI RD ADDR NOP SDO RD ADDR READ DATA FIGURE 28. FOUR BYTE READ SEQUENCE Write Operation A write operation to the ISL23428 is a two or more bytes operation. First, It requires the CS transition from HIGH-to-LOW. Then the host sends a valid Instruction Byte, followed by one or more Data Bytes to the SDI pin. The host terminates the write operation by pulling the CS pin from LOW-to-HIGH. Instruction is executed on the rising edge of CS (see Figure 27). Read Operation A Read operation to the ISL23428 is a four byte operation. First, It requires the CS transition from HIGH-to-LOW. Then the host sends a valid Instruction Byte, followed by a “dummy” Data Byte, NOP Instruction Byte and another “dummy” Data Byte to SDI pin. The SPI host receives the Instruction Byte (instruction code + register address) and requested Data Byte from SDO pin on the rising edge of SCK during third and fourth bytes, respectively. The host terminates the read by pulling the CS pin from LOW-to-HIGH (see Figure 28). 16 FN7904.0 August 25, 2011 ISL23428 Applications Information Communicating with ISL23428 Communication with ISL23428 proceeds using SPI interface through the ACR (address 10000b), WR0 (addresses 00000b) and WR1 (addresses 00001b) registers. The wiper of the potentiometer is controlled by the WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position. The first part starts by HIGH-to-LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW-to-HIGH transition on CS line. The read instructions are executed during the second part of read sequence. It also starts by HIGH-to-LOW transition on CS line, followed by N number of two bytes NOP instructions on SDI line and LOW-to-HIGH transition of CS. The data is read on every even byte during the second part of the read sequence while every odd byte contains code 111b followed by address from which the data is being read. Daisy Chain Configuration When an application needs more than one ISL23428, it can communicate with all of them without additional CS lines by daisy chaining the DCPs as shown in Figure 29. In Daisy Chain configuration, the SDO pin of the previous chip is connected to the SDI pin of the following chip, and each CS and SCK pins are connected to the corresponding microcontroller pins in parallel, like regular SPI interface implementation. The Daisy Chain configuration can also be used for simultaneous setting of multiple DCPs. Note, the number of daisy chained DCPs is limited only by the driving capabilities of the SCK and CS pins of the microcontroller; for larger number of SPI devices, buffering of SCK and CS lines is required. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time ( DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously. VLOGIC Requirements It is recommended to keep VLOGIC powered all the time during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23428. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VLOGIC pin. Daisy Chain Read Operation The read operation consists of two parts: first, send the read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation) as shown in Figures 31 and 32. VCC Requirements and Placement It is recommended to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VCC pin. N DCP IN A CHAIN CS SCK MOSI MISO µC CS SCK SDI SDO DCP0 CS SCK SDI SDO DCP1 CS SCK SDI SDO DCP2 DCP(N-1) CS SCK SDI SDO FIGURE 29. DAISY CHAIN CONFIGURATION 17 FN7904.0 August 25, 2011 ISL23428 CS SCK 16 CLKLS SDI SDO 0 SDO 1 WR D C P2 16 CLKS WR WR D C P1 D C P2 WR WR WR 16 CLKS D C P0 D C P1 D C P2 SDO 2 FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR DATA IN SDO DATA OUT FIGURE 31. TWO BYTE READ INSTRUCTION CS SCK 16 CLKS SDI RD DCP2 16 CLKS RD DCP1 16 CLKS RD DCP0 16 CLKS NOP 16 CLKS NOP 16 CLKS NOP SDO DCP2 OUT DCP1 OUT DCP0 OUT FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP 18 FN7904.0 August 25, 2011 ISL23428 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 8/25/11 REVISION FN7904.0 Initial Release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL23428 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN7904.0 August 25, 2011 ISL23428 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 5.00 ±0.10 14 8 SEE DETAIL "X" 3 6.40 4.40 ±0.10 2 3 PIN #1 I.D. MARK 0.20 C B A 1 0.65 TOP VIEW 7 B 0.09-0.20 END VIEW 1.00 REF H C SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 SIDE VIEW CBA 1.20 MAX 0.05 0.90 +0.15/-0.10 GAUGE PLANE 0.05 MIN 0.15 MAX DETAIL "X" 0°-8° 0.60 ±0.15 0.25 5 (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. TYPICAL RECOMMENDED LAND PATTERN 20 FN7904.0 August 25, 2011 ISL23428 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D A B L16.2.6x1.8A 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 6 INDEX AREA 2X 2X 0.10 C N E SYMBOL A MIN 0.45 - NOMINAL 0.50 0.127 REF MAX 0.55 0.05 NOTES - 12 0.10 C TOP VIEW A1 A3 b D 0.15 2.55 1.75 0.20 2.60 1.80 0.40 BSC 0.25 2.65 1.85 5 - 0.10 C 0.05 C SEATING PLANE A A1 SIDE VIEW C E e K L L1 0.15 0.35 0.45 0.40 0.50 16 4 4 0.45 0.55 2 3 3 e PIN #1 ID 12 L1 K NX L NX b 5 16X 0.10 M C A B 0.05 M C BOTTOM VIEW N Nd Ne  NOTES: 0 - 12 4 Rev. 5 2/09 (DATUM B) (DATUM A) 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 3.00 1.80 1.40 1.40 2.20 0.90 0.40 0.20 0.50 0.40 10 LAND PATTERN 0.20 21 FN7904.0 August 25, 2011