ISL28238FUZ

® ISL28138, ISL28238 Data Sheet February 19, 2008 FN6336.2 4.5MHz, Single and Dual Precision Rail-to-Rail Input-Output (RRIO) Op Amps with Very Low Input Bias Current The ISL28138 and ISL28238 are 4.5MHz low-power single and dual operational amplifiers. The parts are optimized for single supply operation from 2.4V to 5.5V, allowing operation from one lithium cell or two Ni-Cd batteries. The parts feature an Input Range Enhancement Circuit (IREC) which enables them to maintain CMRR performance for input voltages greater than the positive supply. The input signal is capable of swinging 0.25V above the positive supply and to 100mV below the negative supply with only a slight degradation of the CMRR performance. The output operation is rail-to-rail. The parts draw minimal supply current (900µA per amplifier) while meeting excellent DC accuracy, AC performance, noise and output drive specifications. The ISL28138 features an enable pin that can be used to turn the device off and reduce the supply current to less than 20µA. Operation is guaranteed over -40°C to +125°C temperature range. Features • 4.5MHz gain bandwidth product • 900µA supply current (per amplifier) • 300µV maximum offset voltage • 1pA typical input bias current • Down to 2.4V single supply voltage range • Rail-to-rail input and output • Output sources and sinks 60mA load current • Enable pin (ISL28138) • -40°C to +125°C operation • Pb-free (RoHS compliant) Applications • Low-end audio • 4mA to 20mA current loops • Medical devices • Sensor amplifiers • ADC buffers Ordering Information PART NUMBER (Note) ISL28138FHZ-T7* PART MARKING GABR PACKAGE (Pb-free) 6 Ld SOT-23 6 Ld SOT-23 PKG. DWG. # MDP0038 MDP0038 MDP0027 MDP0027 MDP0027 MDP0027 MDP0043 MDP0043 • DAC output amplifiers ISL28138FHZ-T7A* GABR ISL28138FBZ ISL28138FBZ-T7* Coming Soon ISL28238FBZ Coming Soon ISL28238FBZ-T7* Coming Soon ISL28238FUZ Coming Soon ISL28238FUZ-T7* Pinouts ISL28138 (6 LD SOT-23) TOP VIEW OUT 1 V- 2 IN+ 3 6 V+ 5 EN 4 INNC 1 IN- 2 IN+ 3 V- 4 + 28138 FBZ 8 Ld SOIC 28138 FBZ 8 Ld SOIC 28238 FBZ 8 Ld SOIC 28238 FBZ 8 Ld SOIC 8238Z 8238Z 8 Ld MSOP 8 Ld MSOP ISL28138 (8 LD SO) TOP VIEW 8 EN 7 V+ 6 OUT 5 NC +- *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ISL28238 (8 LD SO) TOP VIEW OUT_A 1 IN-_A 2 IN+_A 3 V- 4 -+ +8 V+ 7 OUT_B 6 IN-_B 5 IN+_B OUT_A 1 IN-_A 2 IN+_A 3 V- 4 ISL28238 (8 LD MSOP) TOP VIEW 8 V+ -+ +7 OUT_B 6 IN-_B 5 IN+_B 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL28138, ISL28238 Absolute Maximum Ratings (TA = +25°C) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Information Thermal Resistance θJA (°C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 110 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 115 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. CONDITIONS 8 Ld SOIC 6 Ld SOT-23 MIN (Note 1) -300 -650 -550 -750 TYP ±6 PARAMETER VOS DESCRIPTION Input Offset Voltage MAX (Note 1) 300 650 550 750 UNIT µV µV µV/°C ±6 Δ V OS --------------ΔT IOS IB CMIR CMRR PSRR AVOL Input Offset Voltage vs Temperature 8 Ld SOIC 0.6 Input Offset Current TA = -40°C to +85°C Input Bias Current TA = -40°C to +85°C Common-Mode Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Guaranteed by CMRR VCM = 0V to 5V V+ = 2.4V to 5.5V VO = 0.5V to 4.5V, RL = 100kΩ to VCM VO = 0.5V to 4.5V, RL = 1kΩ to VCM -35 -80 -30 -80 0 75 70 80 75 200 150 ±5 35 80 30 80 5 pA pA V dB dB V/mV V/mV ±1 98 98 580 50 3 50 6 8 70 110 VOUT Maximum Output Voltage Swing Output low, RL = 100kΩ to VCM Output low, RL = 1kΩ to VCM Output high, RL = 100kΩ to VCM Output high, RL = 1kΩ to VCM 4.994 4.99 4.93 4.89 0.7 0.4 mV mV V V 4.998 4.95 0.9 10 1.1 1.4 14 16 IS,ON IS,OFF Supply Current, Enabled Supply Current, Disabled (ISL28138) mA µA 2 FN6336.2 February 19, 2008 ISL28138, ISL28238 Electrical Specifications V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) CONDITIONS R L = 1 0Ω R L = 1 0Ω V+ to V-, Guararteed by PSRR MIN (Note 1) 48 45 50 45 2.4 2 0.8 VEN = V+ VEN = V1 12 1.5 1.6 25 30 TYP 75 68 5.5 MAX (Note 1) UNIT mA mA V V V µA nA PARAMETER IO+ IOVSUPPLY VENH VENL IENH IENL DESCRIPTION Short-Circuit Output Source Current Short-Circuit Output Sink Current Supply Operating Range EN Pin High Level (ISL28138) EN Pin Low Level(ISL28138) EN Pin Input High Curren (ISL28138) EN Pin Input Low Current (ISL28138) AC SPECIFICATONS GBW Unity Gain Bandwidth eN Gain Bandwidth Product -3dB Bandwidth Input Noise Voltage Peak-to-Peak Input Noise Voltage Density iN Input Noise Current Density AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM AV =1, RF = 0Ω, VOUT = 10mVP-P, RL = 10kΩ to VCM f = 0.1Hz to 10Hz fO = 1kHz fO = 1kHz VCM = 1VP-P, RL = 10kΩ to VCM V+, V- = ±1.2V and ±2.5V, VSOURCE = 1VP-P, RL = 10kΩ to VCM V+, V- = ±1.2V and ±2.5V VSOURCE = 1VP-P, RL = 10kΩ to VCM 4.5 13 2 26 0.12 85 -82 -100 MHz MHz µVP-P nV/√Hz pA/√Hz dB dB dB CMRR @ 60Hz Input Common Mode Rejection Ratio PSRR- @ 120Hz PSRR+ @ 120Hz Power Supply Rejection Ratio (V-) Power Supply Rejection Ratio (V+) TRANSIENT RESPONSE SR tr, tf, Large Signal Slew Rate Rise Time, 10% to 90%, VOUT Fall Time, 90% to 10%, VOUT tr, tf, Small Signal Rise Time, 10% to 90%, VOUT Fall Time, 90% to 10%, VOUT tEN Enable to Output Turn-on Delay Time, 10% EN to 10% VOUT, (ISL28138) Enable to Output Turn-off Delay Time, 10% EN to 10% VOUT, (ISL28138) NOTE: 1. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. ±4.8 V/µs ns ns ns ns µs µs AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ RL = 10kΩ to VCM AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ RL = 10kΩ to VCM AV = +2, VOUT = 10mVP-P, RG = RF = RL = 10kΩ to VCM AV = +2, VOUT = 10mVP-P, RG = RF = RL = 10kΩ to VCM VEN = 5V to 0V, AV = +2, RG = RF = RL = 1k to VCM VEN = 0V to 5V, AV = +2, RG = RF = RL = 1k to VCM 530 530 50 50 5 0.2 3 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 15 NORMALIZED GAIN (dB) 10 Rf = Rg = 100k 5 0 V+ = 5V -5 RL = 1k CL = 16.3pF -10 AV = +2 VOUT = 10mVP-P -15 100 1k 10k Rf = Rg = 10k 1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 V = 5V + -7 RL = 1k CL = 16.3pF -8 AV = +1 -9 1k 10k VOUT = 100mV VOUT = 50mV VOUT = 10mV VOUT = 1V Rf = R g = 1 k 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg FIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k 1 0 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 1k V+ = 5V RL = 10k CL = 16.3pF AV = +1 10k 100k 1M 10M 100M VOUT = 100mV VOUT = 50mV VOUT = 10mV VOUT = 1V 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 FREQUENCY (Hz) V+ = 5V RL = 100k CL = 16.3pF AV = +1 1k 10k 100k 1M 10M 100M VOUT = 100mV VOUT = 50mV VOUT = 10mV VOUT = 1V FREQUENCY (Hz) FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k 1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 V + = 5V VOUT = 10mVP-P CL = 16.3pF AV = +1 1k 10k 100k RL = 1 k RL = 10k GAIN (dB) RL = 100k 70 60 50 AV = 101 40 30 AV = 10 20 10 0 AV = 1 V+ = 5V CL = 16.3pF RL = 10k VOUT = 10mVP-P AV = 1001 AV = 1, Rg = INF, Rf = 0 AV = 10, Rg = 1k, Rf = 9.09k AV = 101, Rg = 1k, Rf = 100k AV = 1001, Rg = 1k, Rf = 1M 1M 10M 100M -10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. GAIN vs FREQUENCY vs RL FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 4 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 RL = 10k CL = 16.3pF AV = +1 VOUT = 10mVP-P 100k 1M FREQUENCY (Hz) 10M 100M V+ = 2.4V NORMALIZED GAIN (dB) V + = 5V 8 7 6 5 4 3 2 1 0 -1 -2 -3 V+ = 5V -4 RL = 1k -5 A = +1 V -6 VOUT = 10mVP-P -7 -8 10k 100k (Continued) CL = 51.7pF CL = 43.7pF CL = 37.7pF CL = 26.7pF CL = 16.7pF CL = 4.7pF -9 10k 1M FREQUENCY (Hz) 10M 100M FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 8. GAIN vs FREQUENCY vs CL 10 0 -10 -20 CMRR (dB) -30 -40 -50 -60 -70 -80 -90 100 1k 10k 100k FREQUENCY (Hz) V+ = 2.4V, 5V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M PSRR (dB) 20 0 -20 -40 -60 -80 -100 -120 100 PSRR+ PSRR- V+, V- = ±1.2V RL = 1 k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M 1k 10k 100k FREQUENCY (Hz) FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V 20 INPUT VOLTAGE NOISE (nV/√Hz) 0 -20 PSRR (dB) -40 -60 -80 -100 -120 100 PSRR+ PSRR- 1k V+ = 5V RL = 1 k CL = 16.3pF AV = +1 100 V+, V- = ±2.5V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M 10 1 10 100 1k FREQUENCY (Hz) 10k 100k 1k 10k 100k FREQUENCY (Hz) FIGURE 11. PSRR vs FREQUENCYV, V+, V- = ±2.5V FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY 5 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 10 INPUT CURRENT NOISE (pA/√Hz) V+ = 5V RL = 1 k CL = 16.3pF AV = +1 1 0 -0.5 INPUT NOISE (µV) -1.0 -1.5 -2.0 -2.5 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k -3.0 0 RL = 10k V + = 5V CL = 16.3pF AV = 10k Rf = 100k Rg = 1 0 1 2 3 4 5 6 TIME (s) 7 8 9 10 (Continued) FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz to 10Hz 2.0 1.5 LARGE SIGNAL (V) SMALL SIGNAL (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 1 2 3 V+, V- = ±2.5V RL = 1k CL = 16.3pF Rg = Rf =10k AV = 2 VOUT = 3VP-P 4 5 6 TIME (µs) 7 8 9 10 0.025 0.020 0.015 V+, V- = ±2.5V RL = 1k CL = 16.3pF Rg= Rf = 10k AV = 2 VOUT = 10mVP-P 0 1 2 3 4 5 TIME (µs) 6 7 8 9 10 0.010 FIGURE 15. LARGE SIGNAL STEP RESPONSE FIGURE 16. SMALL SIGNAL STEP RESPONSE 3.5 3.0 2.5 VENABLE (V) 2.0 1.5 1.0 0.5 0 -0.5 0 10 20 30 40 50 60 TIME (µs) 70 80 90 V+ = 5V Rg = Rf = 10k CL = 16.3pF AV = +2 VOUT = 1VP-P RL = 10k VEN VOUT 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 100 OUTPUT (V) FIGURE 17. ISL28138 ENABLE TO OUTPUT RESPONSE 6 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 800 600 400 VOS (µV) 200 0 -200 -400 -600 -800 -1 0 1 2 3 VCM (V) 4 5 6 V + = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1k IBIAS (pA) 100 80 60 40 20 0 -20 -40 -60 -80 -100 -1 0 1 2 3 VCM (V) 4 5 6 V + = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1k (Continued) FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON MODE INPUT VOLTAGE FIGURE 19. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE 1.2 1.1 CURRENT (µA) 1.0 MEDIAN 0.9 0.8 0.7 0.6 -40 10.5 9.5 MAX CURRENT (µA) 8.5 7.5 6.5 5.5 4.5 3.5 -40 MIN MEDIAN MAX MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE V+, V- = ±2.5V FIGURE 21. SUPPLY CURRENT DISABLED vs TEMPERATURE V+, V- = ±2.5V 600 400 200 VOS (µV) 0 -200 -400 -600 -800 -40 MAX MEDIAN VOS (µV) 800 600 400 200 0 -200 -400 MIN -600 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -800 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 MEDIAN MAX MIN FIGURE 22. VOS (SOIC PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V FIGURE 23. VOS (SOT PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V 7 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 600 400 200 VOS (µV) 0 -200 -400 -600 -800 -40 MIN VOS (µV) MEDIAN MAX 400 200 MEDIAN 0 -200 -400 -600 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -800 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 MIN 800 600 MAX (Continued) FIGURE 24. VOS (SOIC PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V FIGURE 25. VOS (SOT PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V 800 600 400 VOS (µV) 200 0 -200 MIN -400 -600 -800 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 MAX 1000 800 600 VOS (µV) 400 200 0 -200 -400 -600 -40 -20 0 MIN 20 40 60 80 TEMPERATURE (°C) 100 120 MEDIAN MAX MEDIAN FIGURE 26. VOS (SOIC PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V FIGURE 27. VOS (SOT PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V 300 250 200 IBIAS- (pA) 150 100 50 0 -50 -40 MIN MAX IBIAS- (pA) MEDIAN 250 200 150 100 50 0 -50 -40 MAX MEDIAN MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 28. IBIAS- vs TEMPERATURE V+, V- = ±2.5V FIGURE 29. IBIAS- vs TEMPERATURE V+, V- = ±1.2V 8 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 10 0 -10 MAX 20 10 0 (Continued) IOS (pA) IOS (pA) -20 -30 -40 -50 -60 -70 -40 -20 0 MEDIAN MIN -10 -20 -30 -40 -50 MAX MEDIAN MIN 20 40 60 80 TEMPERATURE (°C) 100 120 -60 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 30. IOS vs TEMPERATURE V+, V- = ±2.5V FIGURE 31. IOS vs TEMPERATURE V+, V- = ±1.2V 80 1750 70 1550 AVOL (V/mV) AVOL (V/mV) 1350 1150 950 750 550 350 150 -40 MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 20 -40 -20 0 MAX MEDIAN 60 50 40 30 MAX MEDIAN MIN 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 32. AVOL vs TEMPERATURE, RL = 100k, V+, V- = ±2.5V, VO = -2V TO +2V FIGURE 33. AVOL vs TEMPERATURE, RL = 1k V+, V- = ±2.5V, VO = -2V TO +2V 140 130 120 CMRR (dB) PSRR (dB) 110 100 90 80 70 -40 MEDIAN MAX 140 130 120 110 100 MEDIAN 90 80 70 -40 MIN MAX MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 34. CMRR vs TEMPERATURE, VCM = +2.5V TO -2.5V, V+, V- = ±2.5V FIGURE 35. PSRR vs TEMPERATURE, V+, V- = ±1.2V TO ±2.75V 9 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 4.970 4.965 MAX 4.960 VOUT (V) VOUT (V) 4.955 MEDIAN 4.950 4.945 4.940 -40 MIN 4.9990 4.9988 4.9986 4.9984 4.9982 -40 MEDIAN MIN 4.9994 4.9992 MAX (Continued) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 36. VOUT HIGH vs TEMPERATURE RL = 1k, V+, V- = ±2.5V FIGURE 37. VOUT HIGH vs TEMPERATURE RL = 100k, V+, V- = ±2.5V 75 70 65 VOUT (mV) 60 MEDIAN 55 50 45 40 -40 MIN MAX VOUT (mV) 3.3 3.1 2.9 2.7 2.5 2.3 MEDIAN 2.1 1.9 1.7 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 1.5 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 MIN MAX FIGURE 38. VOUT LOW vs TEMPERATURE RL = 1k, V+, V- = ±2.5V FIGURE 39. VOUT LOW vs TEMPERATURE RL=100k, V+, V- = ±2.5V + OUTPUT SHORT CIRCUIT CURRENT (mA) - OUTPUT SHORT CIRCUIT CURRENT (mA) 95 90 MAX 85 80 MEDIAN 75 70 MIN 65 60 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -50 -55 MAX -60 -65 -70 MIN -75 -80 -85 -40 MEDIAN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 40. + OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V FIGURE 41. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V 10 FN6336.2 February 19, 2008 ISL28138, ISL28238 Pin Descriptions ISL28138 (6 Ld SOT-23) ISL28138 (8 Ld SOIC) 1, 5 4 2 2 (A) 6 (B) ISL28238 (8 Ld SOIC) (8 Ld MSOP) PIN NAME NC ININ-_A IN-_B FUNCTION Not connected inverting input V+ IN- EQUIVALENT CIRCUIT IN+ VCircuit 1 3 3 3 (A) 5 (B) IN+ IN+_A IN+_B V- Non-inverting input (See circuit 1) 2 4 4 Negative supply V+ CAPACITIVELY COUPLED ESD CLAMP VCircuit 2 1 6 1 (A) 7 (B) OUT OUT_A OUT_B Output V+ OUT VCircuit 3 6 5 7 8 8 V+ EN Positive supply Chip enable (See circuit 2) V+ EN VCircuit 4 Applications Information Introduction The ISL28138 and ISL28238 are single and dual channel CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifiers. The parts are designed to operate from single supply (2.4V to 5.5V) or dual supply (±1.2V to ±2.75V). The parts have an input common mode range that extends 0.25V above the positive rail and 100mV below the the negative supply rail. The output operation can swing within about 3mV of the supply rails with a 100kΩ load. input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28138 and ISL28238 achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range gives us an undistorted behavior from typically 100mV below the negative rail and 0.25V higher than the V+ rail. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the 11 FN6336.2 February 19, 2008 ISL28138, ISL28238 Rail-to-Rail Output A pair of complementary MOS devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The ISL28138 and ISL28238 with a 100kΩ load will swing to within 3mV of the positive supply rail and within 3mV of the negative supply rail. will be enabled by default. When not used, the EN pin should either be left floating or connected directly to the V- pin. Limitations of the Differential Input Protection If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For non-inverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several sources: 1) During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don’t track, so differentials arise. 2) When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3) When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the VOUT can’t keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 4.8V/µs, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled ICC. Results of Over-Driving the Output Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in two ways. 1) The input voltage times the gain of the amplifier exceeds the supply voltage by a large value or, 2) the output current required is higher than the output stage can deliver. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1µV/hr. of exposure under these conditions. IN+ and IN- Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (see “Pin Descriptions” on page 11 - Circuit 1). For applications where the input differential voltage is expected to exceed 0.5V, an external series resistor must be used to ensure the input currents never exceed 5mA (Figure 42). VIN RIN + RL VOUT Using Only One Channel FIGURE 42. INPUT CURRENT LIMITING Enable/Disable Feature The ISL28138 offers an EN pin that disables the device when pulled up to at least 2.0V. In the disabled state (output in a high impedance state), the part consumes typically 10µA at room temperature. By disabling the part, multiple ISL28138 parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN pin. The loading effects of the feedback resistors of the disabled amplifier must be considered when multiple amplifier outputs are connected together. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while disabled channel VIN = GND), so the mux implementation is best suited for small signal applications. If large signals are required, use series IN+ resistors, or large value RF, to keep the feed through current low enough to minimize the impact on the active channel. See “Limitations of the Differential Input Protection” on page 12 for more details.The EN pin also has an internal pull-down. If left open, the EN pin will pull to the negative rail and the device If the application only requires one channel of the ISL28238, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 43). + FIGURE 43. PREVENTING OSCILLATIONS IN UNUSED CHANNELS 12 FN6336.2 February 19, 2008 ISL28138, ISL28238 Proper Layout Maximizes Performance To achieve the maximum performance of the high input impedance and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 44 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. HIGH IMPEDANCE INPUT IN V+ Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1: T JMAX = T MAX + ( θ JA xPD MAXTOTAL ) (EQ. 1) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated as shown in Equation 2: V OUTMAX PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × --------------------------RL (EQ. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier FIGURE 44. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER • VS = Supply voltage (Magnitude of V+ and V-) • IMAX = Maximum supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance Current Limiting The ISL28138 and ISL28238 have no internal current limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. 13 FN6336.2 February 19, 2008 ISL28138, ISL28238 SOT-23 Package Family e1 A N 6 4 MDP0038 D SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX ±0.05 ±0.15 ±0.05 ±0.06 Basic Basic Basic Basic Basic ±0.10 Reference Reference Rev. F 2/07 NOTES: E1 2 3 E A2 b c 0.20 C 0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D D E E1 e e1 L L1 N 0.15 C A-B 2X C D 1 3 A2 SEATING PLANE 0.10 C NX A1 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) H 6. SOT23-5 version has no center lead (shown as a dashed line). A GAUGE PLANE c L 0° +3° -0° 0.25 14 FN6336.2 February 19, 2008 ISL28138, ISL28238 Small Outline Package Family (SO) A D N (N/2)+1 h X 45° A E E1 PIN #1 I.D. MARK c SEE DETAIL “X” 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4° ±4° 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150”) 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300”) (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07 15 FN6336.2 February 19, 2008 ISL28138, ISL28238 Mini SO Package Family (MSOP) 0.25 M C A B D N A (N/2)+1 MDP0043 MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. ±0.05 ±0.09 +0.07/-0.08 ±0.05 ±0.10 ±0.15 ±0.10 Basic ±0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. E E1 PIN #1 I.D. A2 b c B 1 (N/2) D E E1 e C SEATING PLANE 0.10 C N LEADS b H e L L1 N 0.08 M C A B L1 A c SEE DETAIL "X" 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. A2 GAUGE PLANE L DETAIL X 0.25 A1 3° ±3° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6336.2 February 19, 2008