IS61LF6432A

IS61LF6436A IS61LF6432A 64K x 32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin TQFP package • Power Supply: +3.3V VDD +3.3V or 2.5V VDDQ • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode • Industrial Temperature Available: (-40oC to +85oC) • Lead-free available ISSI OCTOBER 2005 ® DESCRIPTION The ISSI IS61LF6432A and IS61LF6436A are high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, memory. IS61LF6432A is organized as 65,536 words by 32 bits. IS61LF6436A is organized as 65,536 words by 36 bits. They are fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BWa controls DQa, BWb controls DQb, BWc controls DQc, BWd controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61LF6432A/36A and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 8.5 8.5 11 90 Unit ns ns MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 1 IS61LF6436A IS61LF6432A BLOCK DIAGRAM MODE Q0 A0' ISSI CLK ® CLK BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' 64Kx32; 64Kx36 MEMORY ARRAY A0, A1 14 16 17/18 A D Q ADDRESS REGISTER CE CLK 32, 36 32, 36 GW BWE BW(a-d) x32/x36: a-d DQ(a-d) BYTE WRITE REGISTERS CLK D Q CE CE2 CE2 D Q 4 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OE 32, 36 DQa - DQd OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 IS61LF6436A IS61LF6432A PIN CONFIGURATION 100-Pin TQFP A A CE CE2 BWd BWc BWb BWa CE2 VDD Vss CLK GW BWE OE ADSC ADSP ADV A A ISSI ® NC DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa NC 64K x 32 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VDD Vss VDDQ ZZ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable A CLK ADSP ADSC ADV BWa-BWd BWE Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 MODE A A A A A1 A0 NC NC Vss VDD NC NC A A A A A A NC 3 IS61LF6436A IS61LF6432A PIN CONFIGURATION 100-Pin TQFP A A CE CE2 BWd BWc BWb BWa CE2 VDD Vss CLK GW BWE OE ADSC ADSP ADV A A ISSI ® DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC Vss VDD NC NC A A A A A A NC DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa 64K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VDD Vss VDDQ ZZ DQPa-DQPd Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O A CLK ADSP ADSC ADV BWa-BWd BWE 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 IS61LF6436A IS61LF6432A TRUTH TABLE Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used CE None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L X X L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L H H L H H H H X X H X H H X X H X L X X L L X L L H H H H H H H H H H H H ADV X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X Read Write Read Read Read Read Write Write Read Read Read Read Write Write ISSI OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D ® PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 5 IS61LF6436A IS61LF6432A INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 ISSI ® 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN VDD Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Voltage on VDD Supply Relative to Vss Value –55 to +150 1.6 100 –0.5 to VDDQ + 0.3 –0.5 to VDD + 0.5 –0.5 to 4.6 Unit °C W mA V V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 IS61LF6436A IS61LF6432A ISSI VDD 3.3V, +10%, –5% 3.3V (I/O) VDDQ 3.3V, +10%, –5% 2.5V (I/O) VDDQ 2.5V + 5% ® OPERATING RANGE Range Industrial Ambient Temperature –40°C to +85°C DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter OutputHIGHVoltage OutputLOWVoltage Input HIGH Voltage Input LOW Voltage InputLeakageCurrent OutputLeakageCurrent Test Conditions IOH = –4.0 mA (3.3V) IOH = 1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) 2.5V (I/O) Min. Max. 2.0 — — 1.7 –0.3 –5 –5 0.4 VDD + 0.3 0.7 5 5 3.3V (I/O) Min. Max. 2.4 — — 2.0 –0.3 –5 –5 0.4 VDD + 0.3 0.8 5 5 Unit V V V V µA µA Vss ≤ VIN ≤ VDD Vss ≤ VOUT ≤ VDDQ, OE = VI POWER SUPPLY CHARACTERISTICS (Over Operating Range) 8.5 Max. 150 Symbol ICC Parameter AC Operating Supply Current ISB1 Standby Current CMOS Input IZZ Sleep Mode Test Conditions Device Selected, OE = VIH, ZZ ≤ VIL, All Inputs ≤ 0.2V or ≥ VDD – 0.2V, Cycle Time ≥ tKC min. Device Deselected, VDD = Max., VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f=0 ZZ>VIH IND. Unit mA IND. 75 mA IND. 35 mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to Vss, or tied to VDD. 2. The MODE pin should be tied to VDD or Vss. It exhibits ±10 µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ VDD – 0.2V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 7 IS61LF6436A IS61LF6432A CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF ISSI ® Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V ZO = 50Ω Output 50Ω OUTPUT 351 Ω 5 pF Including jig and scope 1.5V Figure 1 Figure 2 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 IS61LF6436A IS61LF6432A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1ns 1.25V See Figures 3 and 4 ISSI ® 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω Output 50Ω OUTPUT 1538 Ω 5 pF Including jig and scope 1.25V Figure 3 Figure 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 9 IS61LF6436A IS61LF6432A READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) 8.5 Symbol fMAX tKC tKH tKL (3) (3) (1) (3) (3) ISSI Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Min. — 11 4.5 4.5 — 2 0 2 — 2 0 — 2 2 2 2 2 1 0.5 0.5 0.5 0.5 Max. 90 — — — 8.5 — — 3.5 4.0 — — 5.0 — — — — — — — — — — Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® tKQ tKQX tKQLZ(1,2) tKQHZ tOEQ tOEQX (1,2) (3) (1) tOELZ(1,2) tOEHZ(1,2) tAS tSS (3) (3) tWS(3) tCES tAVS tAH (3) (3) (3) tSH(3) tWH (3) (3) tCEH tAVH (3) Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 IS61LF6436A IS61LF6432A READ/WRITE CYCLE TIMING tKC ISSI tSH tKH tKL ® CLK tSS ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS tAH Address RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BWd-BWa tCES tCEH WR1 CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC CE2 tCES tCEH Unselected with CE2 CE2 tOEHZ OE tOEQX tKQ tKQ tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b tKQX 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Flow-through Single Write Burst Read Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 11 IS61LF6436A IS61LF6432A WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) 8.5 Symbol tKC(1) tKH(1) tKL (1) (1) ISSI Min. 11 4.5 4.5 2 2 2 3 2 2 1 0.5 1 0.5 0.5 0.5 Max. — — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time tAS tSS(1) tWS tDS (1) (1) (1) tCES tAH tSH tAVS(1) (1) (1) (1) tDH tWH(1) tCEH(1) tAVH (1) Notes: 1. Tested with load in Figure 1. 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 IS61LF6436A IS61LF6432A WRITE CYCLE TIMING tKC ISSI tSH tKH tKL ® CLK tSS ADSP is blocked by CE inactive ADSC initiate Write ADSP ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BWd-BWa tCES tCEH WR1 WR2 CE Masks ADSP WR3 CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 OE High-Z tDS tDH DATAOUT DATAIN High-Z 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a Single Write Burst Write Write Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 13 IS61LF6436A IS61LF6432A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current Conditions ZZ ≥ Vih Min. — — 2 — 0 Max. 35 2 — 2 — ISSI Unit mA cycle cycle cycle ns ® SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 IS61LF6436A IS61LF6432A ORDERING INFORMATION 3.3V I/O OR 2.5V I/O Industrial Range: -40°C TO +85°C Speed (ns) 8.5 8.5 Order Part No. IS61LF6432A-8.5TQI IS61LF6432A-8.5TQLI IS61LF6436A-8.5TQI IS61LF6436A-8.5TQLI Package TQFP TQFP, Lead-free TQFP TQFP, Lead-free ISSI ® Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 08/25/05 15 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ ISSI D D1 ® E E1 N 1 C e SEATING PLANE L1 L A2 A1 b A Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03