HF88M02

King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 - Table of Contents 1 2 3 4 5 6 Function Description______________________________________________________________2 Features ________________________________________________________________________2 Functional block diagram __________________________________________________________3 Pin Description __________________________________________________________________4 Pad Location ____________________________________________________________________5 Device Operation _________________________________________________________________6 6.1 6.2 6.3 6.4 6.5 6.6 Retrieve data in Data File ____________________________________________________________8 Loading the Address Counter _________________________________________________________8 Sequential Read Mode and Auto Increment of Address Counter ____________________________9 Output data to External I/O __________________________________________________________9 Reading Input pin status _____________________________________________________________9 Retrieving the Contents of Expansion I/O registers ______________________________________10 7 Timing Diagrams ________________________________________________________________10 7.1 7.2 7.3 7.4 7.5 7.6 Data File Read Cycle _______________________________________________________________11 Interrupted by I/O when Loading Address Counter______________________________________12 Setting and Reading the I/O Mode for P0 and P1 ________________________________________13 Reading P0 and P1 in Mixed-I/O Mode ________________________________________________14 Reading the input pins ______________________________________________________________15 Output to P0 and P1 Ports___________________________________________________________16 8 9 10 11 12 Absolute Maximum Rating ________________________________________________________16 AC Electrical Characteristics ______________________________________________________16 DC Electrical Characteristics ____________________________________________________17 Application Circuit Diagram _______________________________________________________17 Updated History _______________________________________________________________19 January 16, 2004 Page 1 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 1 Function Description The HF88M02 is a command interfaced 256K x 8 bit Mask ROM. It features command mode interface with external CPU or MCU. In other words, it uses only 8-bit data bus and a few additional control pins to load addresses and provide the ROM access as well as expansion I/O ports capability. This design not only reduces pin count required to access data in ROM dramatically but also allows for systems expansion to higher capacity memories while using the existing board design. The application areas include voice, graphic, data storage in consumer product. 2 Features Data File Mode with only 11 pin interface Sixteen-bit Expansion I/O pins with three-state mode Voltage range 2.4V ~ 5.5V Organization - Memory Cell Array: 256K x 8 Sequential Read Operation in Data File Operation Mode - Sequential Access : 120ns (min.) at VDD = 5.0V Command/Address/Data Multiplexed I/O port Low Operation Current (Typical) 10µA Standby mode Current 10mA Active Read Current Package bare chip, PLCC32 January 16, 2004 Page 2 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 3 Functional block diagram X BUFFER & DECODER Y BUFFER & DECODER CEn OEn WEn MEMORY CELL ARRAY SENSE AMP. CONTROL LOGIC AC0 AC1 AC2 [AC18..A0] RS2..RS0 [P00..P07] [P10..P17] P0 P1 DIR0 DIR1 [D7.. D0] January 16, 2004 Page 3 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 4 Pin Description P14 P17 RS0 WE VDD RS2 RS1 5 6 7 8 9 2 11 12 13 4 3 2 1 32 31 30 P07 P06 P05 P04 P03 P02 P01 P00 D0 D1 D2 VSS D3 D4 D5 D6 P16 P15 P10 P11 P13 OE P12 CE D7 29 28 27 26 25 24 23 22 21 Symbol VDD VSS CEn Pin No. I/O Description 32 P Positive power supply input pin. 16 P Gound pin. 22 I The CEn (Chip Enable) input is the device selection and power control for internal Mask ROM array. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode and the contents of the ROM and registers can be accessed. Please note that only accesses to the internal registers are inhibited, but the status of I/O registers are not affected by the CEn pin and will remain unchanged. CEn is also useful to uniquely select a certain device for applications where multiple-chip array is required. WEn 1 I WEn controls writing to internal registers such as the Output Port Registers, Direction Registers, Address Counter and Data on D7 ~ D0 are latched on the rising edge of the WE pulse. The WEn (Write Enable) input is internally pulled-up to VDD to prevent pin floating. So this pin should stay at ‘1’ state when inactive to prevent unintended current consumption. OEn 24 I OEn (Output Enable) is the output control which gates ROM array data, expansion I/O ports, Direction Registers to the data I/O pins D7 ~ D0. The internal Address Counter will automatically increment by one with each rising edge of OEn pin in Sequentially Read mode. RS2~RS0 I Register Select pins RS2 ~ RS0 for accessing ROM data, Address Counter, as well as expansion I/O ports. The RS2 (Register Select) input is internally pulled-down to Ground. So this pin should stay at ‘0’ state when inactive to prevent unintended current drain. P17 ~ P10 I/O Bi-directional I/O port P1. P07 ~ P00 I/O Bi-directional I/O port P0. January 16, 2004 14 15 16 17 18 19 20 H F88M02-PLCC32 Page 4 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 Symbol D7 ~ D0 億 電 子 股 份 有 限 公 司 HF88M02 Pin No. I/O Description 21 ~ 17, IO The Bi-directional Data I/O pins are used to input Starting Address, setting 15 ~13 the Expansion I/O direction and Output Registers, and to output ROM array data during read operations, contents of I/O Registers and status of input pins. The D7 ~ D7 float to high-impedance when the chip is deselected (CEn high) or when the outputs are disabled. 5 Pad Location P14 P17 RS0 WEN VDD VDD VDD RS2 RS1 P16 P07 P15 P06 P10 P11 P05 P13 P04 NC P03 NC P02 NC NC P01 P00 OEN NC P12 CEN D0 D1 D2 VSS VSS VSS D3 D4 D5 D6 D7 Die Size: X= 3110 µm, Y=2170 µm, and substrate is connected to GND. Pad No. Pin Name X Coord.e Y Coord. Pad No. Pin Name X Coord. Y Coord. 1 P07 108.33 1931.75 22 P12 2975.87 382.79 2 P06 108.33 1744.31 23 OEN 2975.87 522.79 3 P05 108.33 1557.03 24 NC 2978.86 875.14 4 P04 108.33 1369.59 25 NC 2978.86 1035.14 January 16, 2004 Page 5 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 Pad No. 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 億 電 子 股 份 有 Pad No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 限 公 司 HF88M02 Pin Name X Coord.e Y Coord. P03 108.33 1182.31 P02 108.33 994.87 P01 108.33 807.59 P00 108.33 620.15 NC 108.33 432.98 D0 108.33 171.72 D1 525.97 101.14 D2 713.13 101.14 GND 1077.39 125.28 GND 1267.83 125.48 GND 1651.38 105.09 D3 1814.02 106.14 D4 2001.18 106.14 D5 2188.62 106.14 D6 2375.78 106.14 D7 2975.87 103.39 CEN 2975.87 242.79 Pin Name X Coord. Y Coord. NC 2978.86 1195.14 NC 2978.86 1355.14 P13 2978.87 1495.14 P11 2978.87 1635.14 P10 2978.87 1775.14 P15 2978.87 1915.14 P16 2978.87 2055.13 RS1 2237.66 2066.92 RS2 2050.22 2066.92 VDD 1708.76 2013.72 VDD 1534.34 2013.72 VDD 1359.92 2013.72 WEN 1159.22 2052.30 RS0 971.19 2052.30 P17 625.57 2052.30 P14 438.13 2052.30 6 Device Operation The device provides the capability of accessing the contents of ROM array by external MCU not through standard address and data bus configuration but through minimal number of 8-bit data bus and control pins. Only 11 pins D7 ~ D0, CEn, OEn, WEn are required to use the device as a Data File device. By fixing the RS2 to ‘0’, only CEn, WEn, OEn and D0 ~ D7 are required to access the ROM array data. The CEn pin is device selection pin to uniquely select one device when more than one device are used in parallel and control the access to Mask ROM contents and internal registers. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode. Therefore, when accessing contents of ROM is not intended, CEn should stay at ‘1’ to conserve the power. In addition to Data File mode, the device also provide the expansion I/O capability. Two ports of I/O pins (8 bit each) are provided. The I/O ports can be configured to function as output pin or high-impedance input pins. Only 14 pins, CEn, WEn, OEn, RS2, RS1 and D0 ~ D7 are required to provide the Data File function and full access to two I/O ports. January 16, 2004 Page 6 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 D0 公 司 HF88M02 DIR00 D IR00 DIR10 D Q Q D RS = 100 & OEn = '0' P00 D P10 D RS = 110 & OEn = '0' P00 Q Q P10 1 0 1 0 RS = 101 & OEn = '0' RS = 111 & OEn = '0' There are seven internal registers used to provide the functionality of Data file as well as Expansion I/O capability. These registers are selected by RS2 ~ RS0. All registers are 8-bit wide except AC2. AC2 ~ AC0 are write-only and constitute the complete 19-bit Address Counter used as pointer to the data. While the P0, P1, DIR0 and DIR1 can be read as well as written. Their initial values are as indicated in the following table. When RS2 = ‘0’, the RS1 ~ RS0 are ignored, the Address Counter can be loaded or contents of Data File can be read. This is to reduce the required pin needed for external MCU to interface with the Device and also simplify the procedure for loading the address counter. The P0, P1, DIR0, and DIR1 are used for expansion I/O registers. The P0 and P1 are output registers of Expansion I/O and DIR0 and DIR1 are the Direction Registers that determine the I/O mode of P0 and P1. Each pin can be configured as output or input mode individually by setting or resetting the corresponding pin of the DIR registers. Initially, both P0 and P1 are default to input mode at ‘Hi’ state. The accesses to the internal registers will be inhibited when CEn is ‘1’. However, the status of internal registers, such as expansion I/O ports, will not be affected. For example, if a certain pin is in output mode and driving ‘Hi’, it will not change when CEn pin goes to ‘1’ state. Therefore, the users are advised to take care of the power down condition of I/O ports when entering sleep mode to prevent unnecessary power drain. RS2RS1RS0 Symbol 0xx AC2 January 16, 2004 Type R W Description Read data by Indirect access Address latch 2 for A17 ~ A16 Page 7 of 19 Initial Value “--------“ V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 AC1 AC0 P0 DIR0 P1 DIR1 W W R/W R/W R/W R/W Address latch 1 for A15 ~ A8 Address latch 0 for A7 ~ A0 Port 0 Output Register Direction Register 0 Port 1 Output Register Direction Register 0 HF88M02 “--------“ “--------“ “11111111“ “00000000“ “11111111“ “00000000“ 100 101 110 111 6.1 Retrieve data in Data File Accesses to the ROM contents, expansion I/O, Address Counter and Direction registers are made through 8 Data I/O pins – D7 ~ D0. With Register Selection RS = “0xx”, the starting addresses can be written through Data I/Os by bringing WEn to low and back to high. WEn. Addresses are latched on the rising edge of Once the starting address of data block is latched into the Address Counter, data may be read out by sequentially pulsing OEn with CEn staying low. When at ‘0’, the OEn gate the data of the selected address unto Data I/O pin D7 ~ D0. With the rising edge of OEn, the internal Address Counter is incremented by one automatically. 6.2 Loading the Address Counter Before the data can be retrieved, the Address Counter must be initialized with the starting address, then the contents of ROM pointed to by Address Counter (AC) can be accessed through D7 through D0. In order to simplify the procedure of loading 19-bit Address Counter (AC), a internal pointer is implemented and used to point to next register to write in the up to three-cycle address loading sequence. Initially, with RS = “0xx” CEn goes from ‘1’ to ‘0’ and the AC pointer is initialized. The pointer is then incremented to point to next register with falling edge of each WEn pulse. So when randomly accessing data within a 256-byte page, or within a 64K-byte block mode, then only one or two-cycle address reload process is needed to access different locations within a page or block. The Address Counter pointer will be held in reset state in the following conditions: 1. When CEn is '1' (the device is deselected). 2. By the Read pulse (OEn is '0') and RS2 = '0' (ROM is being accesses). The inclusion of the 3rd condition is to force the address loading to start from LSB of Address Counter once the read cycle is initiated. However, the AC Pointer will not be reset when reading or writing from/to expansion I/O registers (P0, P1, DIR0, DIR1). This design is useful in certain application scenarios where in the midst of the multi-byte address loading process, an interrupt to the MCU main loop occurs. And in the interrupt service routine, manipulation of expansion I/O registers is performed, January 16, 2004 Page 8 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 i.e., key board is scanned using P0 and P1. When the execution of program returns to main loop after interrupt service routine completed, the loading of address can still resume from where it was interrupted. 6.3 Sequential Read Mode and Auto Increment of Address Counter With each read access to the ROM data (RS = “0xx”), the Address Counter is incremented automatically by one with rising edge of OEn to facility sequential access to a block of ROM data and avoid repeated loading of addresses. 6.4 Output data to External I/O The device’s 16-bit Expansion I/O capability provides additional I/O ports for applications where the I/O pin are heavily used. To use as a certain pin as output pin, the corresponding bit in Direction Register must be set to ‘1’. Please refer to the following example where output 0x00 to P0 to ‘0’ is intended. 1. 2. 3. 4. 5. 6. Set RS to “101” (DIR0). Keep D7 ~ D0 at 0xff (all bits in output mode). Pulse the WEn to low then high to write to write contents of D-bus to DIR0. Set RS to “100” (P0 Output Register). Set D7 ~ D0 to 0x00. Pulse the WEn to low then high to write contents of D-bus to P0 and drive all bits in P0 to low. 6.5 Reading Input pin status To use expansion I/O ports as input pins and read the status from them, the corresponding bit in direction register must be set to ‘0’. Please see the following example where reading inputs from of P1 is intended. 1. 2. 3. 4. 5. 6. Set RS to “111” (DIR1). Set D7 ~ D0 to 0x00. Pulse the WEn to low then high to set DIR1 to all High-Impedance input mode. Set RS to “110” (P1 Output Register). Pulse the OEn to low. Read P1 then set the OEn back to high. There is one thing should be noted. For any unused (open) expansion I/O pin, it is advisable to set the port to output mode either at ‘0’ or ‘1’ state to prevent it from floating or fix it at VDD or VSS if it is set to input mode. Otherwise, the noise might cause the unnecessary power consumption. January 16, 2004 Page 9 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 6.6 Retrieving the Contents of Expansion I/O registers The contents of all four registers can be read through data bus. The ability to access the contents of registers avoids the necessity of using the RAM as mirror to keep the current status of latches in applications. However, extra care should be taken when reading P0 and P1. To read the contents of P0 and P1, the DIR0 and DIR1 should be set to output mode. Otherwise, the pin status instead of P0 and P1 will be read. The same precaution should be applied in Read-Modify-Write sequence that read back the contents of the output registers of output mode pins and input status of input mode pins. 7 Timing Diagrams Symbol TCE TWEL TWEH TDHeld TOLZ TACE TOEL TOEH TCEHeld TACER TORL TORH TRCEL TRCEH Parameter Chip selected to active width WEn active low width WEn inactive low width Written data hold time Read-Write mode transient time ROM data file available time Output enable low duty for access ROM Output enable low duty for access ROM Chip selection signal holding time Register data available time Output enable low duty for access register Output enable low duty for access register RS signal setup time RS signal hold time Min. 0 100 100 50 200 50 250 150 50 30 100 100 50 50 Typ. 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns January 16, 2004 Page 10 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 7.1 Data File Read Cycle HF88M02 tCEHeld tCE CEn tWEL tWEH tOLZ tOEL tOEH WEn OEn tDHeld AC0 D[7:0] Internal Memory Address Internal Memory Data RS[2:0] tRCEL RS2=0, RS1 and RS0 can be any value. 34 AC1 56 AC2 07 ZZ 1E ZZ 3C ZZ 78 ZZ tACE xxxx34 xx5634 075634 ZZ 075635 ZZ 075636 075637 ZZ tRCEH 1E 3C 78 Data File Read Cycle January 16, 2004 Page 11 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 7.2 Interrupted by I/O when Loading Address Counter CEn HF88M02 WEn tORL tACER AC0 tORH OEn AC1 00h 00h ZZ 55h ZZ BBh 78h AC2 00h D[7:0] Internal Memory Address RS[2:0] 000b 3Dh xxxx3Dh xx783Dh 00783Dh 101b 111b 100b 110b 000b P0_Data FFh P0_DIR FFh 00h P1_Data FFh P1_DIR FFh 00h Interrupted by I/O when Loading Address Counter January 16, 2004 Page 12 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 7.3 Setting and Reading the I/O Mode for P0 and P1 CEn HF88M02 W En tO R L tA C E R tO R H OEn D [ 7 :0 ] F0h 0Fh F0h ZZ 0Fh ZZ R S [ 2 :0 ] 000b 101b 111b 101b 111b P 0 _ D a ta FFh P 1 _ D a ta FFh P 0 _ D IR 00h F0h P 1 _ D IR 00h 0Fh S e t t in g a n d R e a d in g t h e I /O M o d e f o r P 0 a n d P 1 January 16, 2004 Page 13 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 7.4 Reading P0 and P1 in Mixed-I/O Mode CEn HF88M02 W En tO R L tA C E R tO R H OEn D [7 :0 ] F0h 0Fh F5h ZZ AFh ZZ R S [2 :0 ] 000b 101b 111b 100b 110b P 0 _ D a ta FFh P 1 _ D a ta FFh P 0 _ D IR 00h F0h P 1 _ D IR 00h 0Fh R e a d in g P 0 a n d P 1 in M ix e d -I /O M o d e January 16, 2004 Page 14 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 7.5 Reading the input pins CEn HF88M02 W En OEn D [7 :0 ] 00h 00h 55h ZZ AAh ZZ R S [2 :0 ] 000b 101b 111b 100b 110b P 0 _ D a ta FFh P 1 _ D a ta FFh P 0 _ D IR F0h 00h P 1 _ D IR 0Fh 00h R e a d in g th e In p u t P in s January 16, 2004 Page 15 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 7.6 Output to P0 and P1 Ports CEn HF88M02 W En OEn D [7 :0 ] FFh FFh 55h ZZ AAh ZZ R S [ 2 :0 ] 000b 101b 111b 100b 110b P 0 _ D a ta FFh 55h P 1 _ D a ta FFh AAh P 0 _ D IR 00h FFh P 1 _ D IR 00h FFh O u tp u t to P 0 a n d P 1 P o r ts 8 Absolute Maximum Rating Items Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VDD VIN TOPR TSTR Rating -0.3 to 6 V -0.3 to Vdd+0.3 V -0 to 70 °C -55 to 125 °C 9 AC Electrical Characteristics READ CYCLE There are two ways of accessing the ROM data. The first one is to assert the valid address on the Address Bus, then assert CEn “low” to enable the ROM array. The access time in this mode is specified as tACE. The advantage of this access mode is that power consumption can be lowered. The second access mode keeps the CEn “low” while changes the addresses to access the contents of ROM data. The January 16, 2004 Page 16 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 access time in this way is specified as tAA. In this device, the Address Access Time decrease monotonically with increasing voltage, and it is shorter than Chip Enable Access Time when the Operation Voltage is higher then 4.5 V. Therefore in Vop higher than 4.5 Volts, it is more advisable to use the Address Access Mode to achieve faster access to ROM data when the power consumption is not a concern. Item Symbol 5.5V 5V 4.5V 3.6V Read Cycle Time tRC 290 220 170 180 Chip Enable Access Time tACE 290 220 170 150 Address Access Time tAA 120 130 150 180 3.3V 190 170 190 3.0V 220 220 210 2.4V 290 290 280 Unit ns ns ns Remark Min Min Min 10 DC Electrical Characteristics (VSS = 0V, VDD = 5.0 V, TOPR = 25°C unless otherwise noted) Parameter Supply Voltage Operating Current Standby Current Input voltage Input current leakage P0, P1 Output High Voltage P0, P1 Output Low Voltage D Output High Voltage D Output Low Voltage Symbol VDD IDD IDD VIH VIL IIL VOH VOL VOH VOL Min. 2.4 2/3 0 2.4 2.4 - Typical 10 10 - Max. 5.5 1 1/3 +/- 10 0.4 0.4 Unit V mA µA VDD µA V V V V Condition No load No load VDD = 4V ~ 6V IOH = 0.4 mA IOL = 2.1 mA IOH = 14 mA IOL = 3 mA 11 Application Circuit Diagram This application circuit illustrates that how KB83760 MCU uses two external HF88M02s for ROM expansion as well as keyboard scan functions. January 16, 2004 Page 17 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 D7 1 C2 En D 7 On E 1N4148 U3 HF88M02-PLCC32 P6 1 P5 1 P0 1 P1 1 P3 1 O E P2 1 CE D 7 1N4148 D6 D5 D4 D3 VSS D2 D1 P7 0 P6 0 P5 0 P4 0 P3 0 P2 0 P1 0 P0 0 D 0 20 19 18 17 16 15 14 D6 D5 D4 D3 D2 D1 D5 1 1N4148 D4 1 1N4148 D3 1 D0 1N4148 D2 1 R 1 R 2 R 4 On E R 3 C1 En D 7 1N4148 U2 HF88M02-PLCC32 P6 1 P5 1 P0 1 P1 1 P3 1 O E P2 1 CE D 7 1 1N4148 D6 D5 D4 D3 D2 D1 R5 C7 C6 C5 C4 C3 C2 C1 D1 2 K1 1 D6 D5 D4 D3 VSS D2 D1 P7 0 P6 0 P5 0 P4 0 P3 0 P2 0 P1 0 P0 0 D0 20 19 18 17 16 15 14 K8 4 K15 7 K22 * 2 2 K3 3 K10 6 K17 9 2 Pause Flash Auto Redial 2 Erase UP DOWN Name D6 1 2 M1 M2 M3 M4 2 份 有 限 公 司 HF88M02 M10 R5 K35 M6 M7 M8 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 RS1 RS2 VDD WEn RS0 30 31 32 1 2 3 4 RS1 RS2 VDD WE RS0 P17 P14 5 6 7 8 9 2 1 1 1 2 1 3 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 K29 PGM RS1 RS2 VDD WEn RS0 R5 30 31 32 1 2 3 4 RS1 RS2 VDD WE RS0 P17 P14 R4 330K R3 330K 5 6 7 8 9 2 1 1 1 2 1 3 R2 330K C7 C6 C5 C4 C3 C2 C1 D0 R1 330K VDD R1 R2 R3 330K R4 Mute K2 2 K9 5 K16 8 K23 0 # K30 HF K24 K31 HOLD K4 K11 K18 K25 K32 Dial K5 K12 K19 K26 K33 M5 K6 K13 K20 K27 M9 K7 K14 K21 K28 K34 C6 1uF VDD C5 D0 D1 D2 D3 D4 D5 D6 D7 K NE TO S DO DTM FO M UTE P1 RT1 0 P1 RT1 1 P1 RT1 2 P1 RT1 3 P1 RT1 4 P1 RT1 5 P1 RT1 6 P1 RT1 7 P0 RT1 0 P0 RT1 1 P0 RT1 2 P0 RT1 3 P0 RT1 4 P0 RT1 5 P0 RT1 6 P0 RT1 7 RS 0 RS 1 RS 2 On E Wn E CE n 1 CE n 2 1uF SI X SO X TS TP FX I FX O RS TP OO P O IP P O IN P DA O C4 U1 KB83760 1uF P T1 0 R1 P T1 1 R1 P T1 2 R1 P T1 3 R1 P T1 4 R1 P T1 5 R1 P T1 6 R1 P T1 7 R1 P T1 0 R0 P T1 1 R0 P T1 2 R0 P T1 3 R0 P T1 4 R0 P T1 5 R0 P T1 6 R0 P T1 7 R0 P TC R0 P TC R1 P TC R2 P TC R3 P TC R4 P TC R5 P TC R6 P TC R7 P TD R0 P TD R1 P TD R2 P TD R3 P TD R4 P TD R5 P TD R6 P TD R7 KY N E TO E S DO DTM FO M TE U V DD SI X SO X TS TP FX I FX O RS TP OO P O IP P O IN P DA O 10 9 19 8 18 8 17 8 16 8 15 8 14 8 13 8 12 8 11 8 10 8 19 7 18 7 17 7 16 7 15 7 14 7 13 7 12 7 11 7 10 7 19 6 18 6 17 6 16 6 15 6 14 6 13 6 12 6 11 6 10 6 19 5 18 5 17 5 16 5 15 5 14 5 13 5 12 5 11 5 10 5 19 4 18 4 17 4 16 4 15 4 14 4 C3 1uF VO GND LVG LR0 LR1 LR2 LR3 LR4 LV3 LV2 LV1 LC2 LC1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 V O PWMP PWMN COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PWMP PWMN COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 C2 1uF C1 1uF C10 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 1uF VDD C7 C8 C9 1uF 1uF 1uF January 16, 2004 S G5 E6 S G4 E6 S G3 E6 S G2 E6 S G1 E6 S G0 E6 S G9 E5 S G8 E5 S G7 E5 S G6 E5 S G5 E5 S G4 E5 S G3 E5 S G2 E5 S G1 E5 S G0 E5 S G9 E4 S G8 E4 S G7 E4 S G6 E4 S G5 E4 S G4 E4 S G3 E4 S G2 E4 S G1 E4 S G0 E4 S G9 E3 S G8 E3 S G7 E3 S G6 E3 S G5 E3 S G4 E3 S G3 E3 S G2 E3 S G1 E3 S G0 E3 S G9 E2 S G8 E2 S G7 E2 S G6 E2 S G5 E2 S G4 E2 S G3 E2 S G2 E2 S G1 E2 S G0 E2 S G9 E1 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 S G5 E6 S G4 E6 S G3 E6 S G2 E6 S G1 E6 S G0 E6 S G9 E5 S G8 E5 S G7 E5 S G6 E5 S G5 E5 S G4 E5 S G3 E5 S G2 E5 S G1 E5 S G0 E5 S T4 E9 S G8 E4 S G7 E4 S G6 E4 S G5 E4 S G4 E4 S G3 E4 S G2 E4 S G1 E4 S G0 E4 S G9 E3 S G8 E3 S G7 E3 S G6 E3 S G5 E3 S G4 E3 S G3 E3 S G2 E3 S G1 E3 S G0 E3 S G9 E2 S G8 E2 S G7 E2 S G6 E2 S G5 E2 S G4 E2 S G3 E2 S G2 E2 S G1 E2 S G0 E2 S G9 E1 Page 18 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M02 12 Updated History Version 1.10 1.11 Date 2003/8/27 2004/1/16 Update Description Timing diagrams modified. Add the die size January 16, 2004 Page 19 of 19 V1.11 This specification is subject to change without notice. Please contact sales person for the latest version before use.