LT3095
Dual-Channel Low Noise
Bias Generators
FEATURES
DESCRIPTION
Generates Two Independent Low Noise Bias Supplies
nn Boost Regulator:
nn Wide Input Voltage Range: 3V to 20V
nn Adjustable Switching Frequency: 450kHz to 2MHz
nn Synchronizable to External Clock
nn 950mA Power Switches
nn Integrated Schottky Diodes
nn Internal Frequency Compensation
nn Linear Regulator:
nn Wide Output Voltage Range: 1V to 20V
nn SET Pin Reference Current: 50µA
nn Low Noise: 4µV
RMS (10Hz to 100kHz)
nn High Frequency PSRR: 72dB at 1MHz
nn Independent Precision-Threshold Enable Pins
nn Symmetric Pinout Simplifies PCB Layout
nn Thermally Enhanced 3mm × 5mm 24-Lead
QFN Package
The LT®3095 generates two low noise bias supplies from
a common input voltage ranging from 3V to 20V. Each
channel includes a fixed frequency, peak current-mode
step-up switching regulator and a low noise, singleresistor-programmable 50mA linear regulator. The linear
regulator’s high power supply ripple rejection (PSRR)
combined with its low noise performance results in less
than 100µVP-P output ripple and noise.
nn
Each boost regulator adjusts its output voltage to 2V above
the corresponding linear regulator’s output voltage, optimizing power dissipation, PSRR and transient response.
This tracking scheme, along with internal boost regulator
frequency compensation and integrated Schottky diodes,
minimizes external component count and simplifies system
design. Each linear regulator includes internal current limit
and thermal limit protection circuitry.
The LT3095 switching frequency is externally programmable with a single resistor from 450kHz to 2MHz. A
SYNC pin allows synchronization to an external clock. The
LT3095 is available in a thermally enhanced, low profile
(0.75mm) 24-lead 3mm × 5mm QFN package.
APPLICATIONS
Noise-Sensitive USB Powered Applications
Data Conversion, Industrial Supplies, RF
nn Instrumentation Amplifiers
nn
nn
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
VIN
3V to 7V
Output Ripple
2.2µF
6.8µH
EN1
SW2
GND
GND
LT3095
BSTOUT1
LDOIN1
2.2µF
1µF
VOUT
50µV/DIV
VOUT2
15V, 50mA
LDOIN2
SET1
SET2
2.2µF
RT
SYNC
GND
VBSTOUT
20mV/DIV
BSTOUT2
OUT2
0.1µF
10µH
10µF
OUT1
INTVCC
100k
EN2
SW1
10µF
VOUT1
5V, 50mA
IN
300k
VIN = 5V
VOUT = 15V
ILOAD = 50mA
fOSC = 1MHz
20MHz BW
1µF
100k
GND
1µs/DIV
3095 G03
3095 TA01a
3095fa
For more information www.linear.com/LT3095
1
LT3095
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
SW2
IN
SW1
IN
TOP VIEW
IN, SET1, SET2 .........................................................24V
SW1, SW2,.................................................................24V
OUT1, OUT2....................................................24V, –0.3V
EN1, EN2 ........................................................24V, –0.3V
LDOIN1, LDOIN2, BSTOUT1, BSTOUT2.....................24V
RT, SYNC.....................................................................6V
Operating Junction Temperature (Note 2)
E-Grade, I-Grade................................. –40°C to 125°C
MP-Grade........................................... –55°C to 125°C
Storage Temperature Range................... –65°C to 150°C
24 23 22 21
GND 1
20 GND
BSTOUT1 2
19 BSTOUT2
NC 3
18 SYNC
INTVCC 4
17 RT
25
GND
GND 5
16 GND
LDOIN1 6
15 LDOIN2
GND 7
14 GND
OUT1 8
13 OUT2
SET2
EN2
EN1
SET1
9 10 11 12
UDD PACKAGE
24-LEAD (3mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 38°C/W, θJC = 5.0°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
(http://www.linear.com/product/LT3095#orderinfo)
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3095EUDD#PBF
LT3095EUDD#TRPBF
LGRQ
24-Lead (3mm x 5mm) Plastic QFN
–40°C to 125°C
LT3095IUDD#PBF
LT3095IUDD#TRPBF
LGRQ
24-Lead (3mm x 5mm) Plastic QFN
–40°C to 125°C
LT3095MPUDD#PBF
LT3095MPUDD#TRPBF
LGRQ
24-Lead (3mm x 5mm) Plastic QFN
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 5V, SYNC = 0V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VIN
Input Voltage Supply Range
IIN
VIN Pin Supply Current
VEN1 = VEN2 = 5.0V, VIN = 5V (Not Switching)
VEN1,2
VTRIP (off to on)
VEN1,2 Rising
MIN
l
3.25
VEN1 = VEN2 = 0.3V, VIN = 20V (Shutdown)
Enable Threshold Hysteresis
Enable Pin Current
2
VEN = 5V
TYP
3
l
MAX
UNITS
20
V
5
mA
1.6
5
μA
1.12
1.23
1.35
V
110
125
135
mV
1
5
μA
3095fa
For more information www.linear.com/LT3095
LT3095
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 5V, SYNC = 0V unless otherwise noted.
SYMBOL PARAMETER
INTVCC
CONDITIONS
MIN
INTVCC Voltage
VEN1 = VEN2 = 5V
INTVCC Under Voltage Lockout
VEN1 = VEN2 = 5V, INTVCC Rising
INTVCC Under Voltage Lockout
Hysteresis
VEN1 = VEN2 = 5V
TYP
MAX
UNITS
2.7
l
2.25
2.4
V
2.55
300
V
mV
Boost Regulator
BOOST
OSC
(VLDOIN – VOUT) Differential Regulation
Voltage
VEN1 = VEN2 = 5V, VOUT = 10V, ILOAD = 0mA
l
1.85
Boost Maximum Duty Cycle
fOSC = 1MHz
l
90
Switch Pin Leakage Current
Switch OFF, VSW = 12V
Boost Switch Peak Current Limit
(Note 3)
Switch VCESAT
ISW = 400mA
Oscillator Frequency
RT = 210k, VIN = 5V
RT = 100k, VIN = 5V
RT = 44.5k, VIN = 5V
SYNC Duty Cycle Range
VSYNC = 0V to 1.5V pulse
SYNC Pin Input Current
VSYNC = 5V
SYNC Threshold
fOSC = 1MHz, 50% duty cycle
l
0.8
2
2.15
V
0.01
1
µA
0.95
1.1
%
250
l
l
l
0.47
0.95
1.85
0.5
1
2
0.53
1.05
2.15
80
%
15
20
µA
0.8
1.1
1.3
V
49.5
50
50.5
µA
49
50
51
µA
–1
0.15
1
mV
20
l
A
mV
MHz
MHz
MHz
LDO Linear Regulator
LDO
SET Pin Current
VOUT = 10V, ILOAD = 0mA
Offset Voltage (VOUT – VSET)
VOUT = 10V, ILOAD = 0mA
LDO Voltage Regulation: ΔISET
LDO Voltage Regulation: ΔVOS (Note 5)
VOUT = 3V to 20V, ILOAD = 0mA
VOUT = 1V to 20V, ILOAD = 0mA
–60
–50
–100
nA
µV
LDO Load Regulation: ΔISET
LDO Load Regulation: ΔVOS (Note 4)
VOUT = 10V, ILOAD = 0mA to 50mA
VOUT = 10V, ILOAD = 0mA to 50mA
100
–6
150
nA
mV
LDOIN Supply Current
ILOAD = 0mA
450
µA
Ripple Rejection
3V < VOUT < 20V, ILOAD = 50mA
fRIPPLE = 450kHz, CSET = 0.1µF, COUT = 2.2µF, ILOAD = 50mA
fRIPPLE = 1MHz, CSET = 0.1µF, COUT = 2.2µF, ILOAD = 50mA
fRIPPLE = 2MHz, CSET = 0.1µF, COUT = 2.2µF, ILOAD = 50mA
73
72
71
dB
LDO Output Noise Voltage
VOUT = 5V, ILOAD = 50mA, CSET = 0.47µF, COUT = 2.2µF,
BW = 10Hz to 100KHz.
4
µVRMS
LDO Output Current Limit
VOUT = 1V to 20V
70
mA
VOUT = 1V to 20V, ILOAD = 0mA to 50mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Absolute Maximum Ratings are those values
beyond which the life of a device may be impaired.
Note 2: The LT3095E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. The
LT3095I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3095MP is 100% tested over the –55°C to
125°C operating junction temperature range.
l
l
55
Note 3: The boost peak current limit is measured in a low frequency test
mode. In operation at high frequencies, the inductor current may exceed
this value due to delays in the control circuitry.
Note 4: Linear Technology® is unable to guarantee maximum load
regulation due to production test limitations with Kelvin-sensing the
package pins. Please consult the Typical Performance Characteristics for
curves of output regulation as a function of load current.
Note 5: For VOUT 1.25V.
3095fa
For more information www.linear.com/LT3095
3
LT3095
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency
TA = 25°C, unless otherwise noted.
Transient Output Ripple
Transient Output Ripple
80
70
EFFICIENCY (%)
60
VBSTOUT
20mV/DIV
VBSTOUT
20mV/DIV
VOUT
5mV/DIV
VOUT
50µV/DIV
50
40
fSW = 1MHz
VOUT1 = 5V
VOUT2 = 15V
ILOAD1 = ILOAD2
30
20
10
0
VIN = 5V
VIN = 3.3V
0
10
20
30
40
LOAD CURRENT (mA)
VIN = 5V
VOUT = 15V
ILOAD = 50mA
fOSC = 1MHz
350MHz BW
50
3095 G01
Linear Regulator Transient
Response
1µs/DIV
3095 G03
SET Pin Current Distribution
N = 10298
SET PIN CURRENT (µA)
50.6
VOUT1
10mV/DIV
VOUT2
10mV/DIV
5µs/DIV
VIN = 5V
VOUT1 = 5V
VOUT2 = 15V
COUT = 2.2µF
CH1 LOAD STEP = 1mA to 50mA
50.4
50.2
50.0
49.8
49.6
49.4
3095 G04
49.2
49.0
–75 –50 –25
SET Pin Current
51.0
VIN = 5V
50.8
49
0 25 50 75 100 125 150
TEMPERATURE (°C)
300
50.8
250
50.4
50.2
50.0
49.8
49.6
50.4
50.2
50.0
49.8
49.6
49.4
49.4
49.2
49.2
2
4
6 8 10 12 14 16 18 20
SET PIN VOLTAGE (V)
3095 G07
OFFSET VOLTAGE (µV)
50.6
SET PIN CURRENT (µA)
50.6
0
49.5
50
50.5
ISET DISTRIBUTION (µA)
3095 G05
SET Pin Current
51.0
SET PIN CURRENT (µA)
VIN = 5V
VOUT = 15V
ILOAD = 50mA
fOSC = 1MHz
20MHz BW
VOUT = 10V
50.8
IOUT
50mA/DIV
4
3095 G02
SET Pin Current
51.0
49.0
1µs/DIV
49.0
51
3095 G06
Offset Voltage (VOUT – VSET)
VOUT = 10V
ILOAD = 0mA
200
150
100
50
0
10
20
30
40
OUTPUT CURRENT (mA)
50
3095 G08
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3095 G09
3095fa
For more information www.linear.com/LT3095
LT3095
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Voltage (VOUT – VSET)
100
TA = 25°C, unless otherwise noted.
Offset Voltage Distribution
Offset Voltage (VOUT – VSET)
1
N = 10298
ILOAD = 1mA
0
–1
OFFSET VOLTAGE (mV)
OFFSET VOLTAGE (µV)
80
60
40
20
–2
–3
–4
–5
–6
–40°C
25°C
125°C
–7
0
0
2
4
–1
6 8 10 12 14 16 18 20
OUTPUT VOLTAGE (V)
–0.5
0
0.5
VOS DISTRIBUTION (mV)
3095 G10
LDO Current Limit
70
65
60
0 25 50 75 100 125 150
TEMPERATURE (°C)
VOUT = VSET – 200mV
70.0
65.0
0
2
4
6 8 10 12 14 16 18 20
OUTPUT VOLTAGE (V)
3095 G13
1.22
1.21
1.20
–75 –50 –25 0
25 50 75
TEMPERATURE (°C)
1.2
120
110
EN Pin Current
5
VEN = VIN = 5V
1.0
0.8
3095 G16
0.4
–75 –50 –25
VIN = 5V
4
0.6
100 125
100 125
3095 G15
EN PIN CURRENT (µA)
140
100
–75 –50 –25 0
25 50 75
TEMPERATURE (°C)
1.23
EN Pin Current
1.4
EN PIN CURRENT (µA)
EN PIN HYSTERESIS (mV)
EN Pin Hysteresis
50
VIN = 5V
3095 G14
150
130
20
30
40
OUTPUT CURRENT (mA)
EN Turn-On Threshold
1.24
75.0
60.0
10
3095 G12
TURN–ON THRESHOLD (V)
75
LDO CURRENT LIMIT (mA)
LDO CURRENT LIMIT (mA)
80.0
0
3095 G11
LDO Current Limit
80
55
–75 –50 –25
–8
1
3
2
1
0 25 50 75 100 125 150
TEMPERATURE (°C)
3095 G17
0
0
2
4
6 8 10 12 14 16 18 20
EN PIN VOLTAGE (V)
3095 G18
3095fa
For more information www.linear.com/LT3095
5
LT3095
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V
VOUT = 12V
VLDOIN – VOUT (V)
2.05
2.00
1.95
1.90
0 25 50 75 100 125 150
TEMPERATURE (°C)
18
2.05
15
2.00
12
1.95
9
1.90
6
1.80
0
2
4
6
1000
950
900
850
40
60
DUTY CYCLE (%)
80
1000
950
900
100
850
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
1800
1030
0.7
1600
1020
FREQUENCY (kHz)
0.8
FREQUENCY (kHz)
1040
1400
1200
1000
800
1000
990
980
600
970
0.1
400
960
3095 G25
0
50
100
150
RT (kΩ)
200
250
3095 G26
RT = 100kΩ
1010
0.2
200
1000
Switching Frequency
2000
1.2
250
500
750
SWITCH CURRENT (mA)
3095 G24
0.9
0.6
0.8
1.0
FORWARD VOLTAGE (V)
0
3095 G23
1050
0
0.4
VIN = 5V
200
Switching Frequency
0.3
50
300
2200
0.4
20
30
40
OUTPUT CURRENT (mA)
400
1.0
0.5
10
Switch Drop
VIN = 5V
800
–75 –50 –25
100
0.6
0
3095 G21
1050
Power Schottky I-V
Characteristic
SCHOTTKY CURRENT (A)
1.85
0
500
3095 G22
6
1.95
1.90
SWITCH DROP (mV)
SWITCH CURRENT LIMIT (mA)
SWITCH CURRENT LIMIT (mA)
1050
20
2.00
Boost Switch Peak Current Limit
1100
VIN = 5V
0
2.05
3095 G20
Boost Switch Peak Current Limit
800
8 10 12 14 16 18 20
VOUT (V)
LDO Differential (VLDOIN – VOUT)
2.10
3
VLDOIN – VOUT
VLDOIN = VBSTOUT
LT3095 G19
1100
21
2.10
1.85
ILOAD = 0mA
ILOAD = 50mA
1.85
–75 –50 –25
VIN = 3V
ILOAD = 1mA
2.15
2.15
24
BOOST OUTPUT VOLTAGE (V)
2.10
VLDOIN - VOUT (V)
Boost Tracking
2.20
LDO DIFFERENTIAL (V)
2.15
Differential Voltage
(VLDOIN – VOUT)
TA = 25°C, unless otherwise noted.
950
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3095 G27
3095fa
For more information www.linear.com/LT3095
LT3095
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency
530
Switching Frequency
2.15
RT = 210kΩ
Maximum Duty Cycle
100
RT = 44.5kΩ
510
500
490
480
MAXIMUM DUTY CYCLE (%)
2.10
FREQUENCY (MHz)
FREQUENCY (kHz)
520
2.05
2.00
1.95
1.90
470
–75 –50 –25
1.85
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
16.0
1.05
1.00
0.95
0.90
0.85
200
VSYNC = VIN = 5V
175
15.0
14.5
14.0
13.5
0 25 50 75 100 125 150
TEMPERATURE (°C)
13.0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3095 G31
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (µA)
VIN = 5V
4.5 V
EN1 = VEN2 = 5V
3.0
2.0
1.0
2
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
3095 G34
125
100
75
50
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3095 G33
Boost Transient Response
VIN Pin
VLDOIN Pin
4.0
3.5
ILOAD
50mA/DIV
3.0
VBST
100mV/DIV
2.5
2.0
VIN = 5V
VOUT = 12V
1.5
1.0
100µs/DIV
0.5
0
150
Quiescent Current
5.0
VEN1 = VEN2 = 0V
2.0
VEN1 = VEN2 = 0V
VIN = 5V
VIN = 20V
3095 G32
Quiescent Current in Shutdown
(Both Channels, Boost + LDO)
4.0
0.6 0.8 1 1.2 1.4 1.6 1.8
OSCILLATOR FREQUENCY (MHz)
25
0.80
0
92
Quiescent Current in Shutdown
(Both Channels, Boost + LDO)
QUIESCENT CURRENT (µA)
SYNC PIN CURRENT (µA)
1.10
5.0
94
3095 G30
15.5
1.15
0.75
–75 –50 –25
96
SYNC Pin Current
VIN = 5V
1.20
98
3095 G29
SYNC Threshold
1.25
VOUT = 20V
ILOAD = 20mA
90
0.4
0 25 50 75 100 125 150
TEMPERATURE (°C)
3095 G28
SYNC THRESHOLD (V)
TA = 25°C, unless otherwise noted.
0
–75 –50 –25
3095 G36
0 25 50 75 100 125 150
TEMPERATURE (°C)
3095 G35
3095fa
For more information www.linear.com/LT3095
7
LT3095
TYPICAL PERFORMANCE CHARACTERISTICS
Start Up Response
TA = 25°C, unless otherwise noted.
Integrated RMS Thermal Noise
(10Hz – 100kHz)
SYNC Acquisition
45
RT = 100kΩ
fSYNC = 1.5MHz
VSYNC
2V/DIV
VINTVCC
5V/DIV
VBSTOUT1
10V/DIV
VOUT1
10V/DIV
VSW1
10V/DIV
IL
500mA/DIV
VSW2
20V/DIV
3095 G37
1ms/DIV
3095 G38
1µs/DIV
COUT = 2.2µF
IOUT = 50mA
40
RMS OUTPUT NOISE (µVRMS)
RSET1 = 240kΩ
CSET1 = 10nF
VEN1
5V/DIV
35
30
25
20
15
10
5
0
0.01
RSET = 100k
RSET = 240k
0.1
SET PIN CAPACITANCE (µF)
1
3095 G39
Noise Spectral Density
CSET = 0.01µF
CSET = 0.1µF
CSET = 1µF
10
VLDOIN = 7V
VOUT = 5V
COUT = 2.2µF
IOUT = 50mA
0.1
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10
0.1
10M
VLDOIN = 7V
VOUT = 5V
CSET = 0.1µF
IOUT = 50mA
10
100
IOUT = 50mA
IOUT = 20mA
IOUT = 10mA
IOUT = 1mA
1k
100
1
Noise Spectral Density
10k
COUT = 2.2µF
COUT = 4.7µF
COUT = 10µF
1k
100
1
Noise Spectral Density
OUTPUT NOISE (nV/√Hz)
1k
OUTPUT NOISE (nV/√Hz)
10k
OUTPUT NOISE (nV/√Hz)
10k
100
10
VLDOIN = 7V
VOUT = 5V
COUT = 2.2µF
CSET = 0.1µF
1
1k
10k 100k
FREQUENCY (Hz)
1M
3095 G40
0.1
10M
10
Linear Regulator Power Supply
Rejection Ratio
110
110
100
100
100
90
90
90
80
80
80
40
CSET = 10nF
CSET = 100nF
CSET = 1µF
30
20
10
100
1M
60
40
COUT = 2.2µF
COUT = 4.7µF
COUT = 10µF
30
10M
3095 G43
8
70
50
VLDOIN = 7V
VOUT = 5V
COUT = 2.2µF
ILOAD = 50mA
1k
10k 100k
FREQUENCY (Hz)
PSRR (dB)
110
PSRR (dB)
120
PSRR (dB)
120
50
1M
20
10
100
1M
70
60
50
VLDOIN = 7V
VOUT = 5V
CSET = 0.1µF
ILOAD = 50mA
1k
10k 100k
FREQUENCY (Hz)
10M
Linear Regulator Power Supply
Rejection Ratio
120
60
1k
10k 100k
FREQUENCY (Hz)
3095 G42
Linear Regulator Power Supply
Rejection Ratio
70
100
3095 G41
ILOAD = 50mA
ILOAD = 20mA
ILOAD = 10mA
ILOAD = 1mA
40
30
10M
3095 G44
20
10
100
VLDOIN = 7V
VOUT = 5V
COUT = 2.2µF
CSET = 0.1µF
1k
10k 100k
FREQUENCY (Hz)
1M
10M
3095 G45
3095fa
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LT3095
PIN FUNCTIONS
GND (Pins 1, 5, 7, 14, 16, 20, Exposed Pad Pin 25):
Ground. Tie the exposed pad Pin 25 directly to all other
GND pins for optimum performance. The exposed pad
provides enhanced thermal performance with its connection to the PCB ground.
BSTOUT1 (Pin 2): Channel 1 Step-Up Regulator Output.
This pin is Channel 1’s boost converter output. Connect
BSTOUT1 directly to LDOIN1. Connect the boost output
capacitor directly from BSTOUT1 to Pin 1’s GND. An internal
feedback loop regulates BSTOUT1’s voltage typically to
(OUT1 + 2V). This optimizes transient response and PSRR
performance of the Linear Regulator.
NC (Pin 3): No Connect. Pin 3 has no internal electrical
connection and may be floated or tied to GND.
INTVCC (Pin 4): Internal Regulator Output. INTVCC powers
most of the internal circuitry for both channels. It nominally regulates to 2.7V. INTVCC is not designed to power
any external load and should not be driven. Connect a
minimum value 0.1µF or higher ceramic capacitor directly
from INTVCC to Pin 5’s GND.
LDOIN1 (Pin 6): Channel 1 Linear Regulator Input. This pin
is Channel 1’s linear regulator input supply pin. Connect
Pin 6 directly to BSTOUT1 at Pin 2.
OUT1 (Pin 8): Channel 1 Linear Regulator Output. This
pin supplies power to Channel 1’s load. Use a minimum
value 2.2µF ceramic capacitor with an ESR less than 0.1Ω
to prevent oscillations. Large load transient applications
require larger value output capacitors to limit peak voltage transients. See the applications information section
for more information on output capacitance. Connect the
output capacitor and the load directly to Pin 7’s GND.
SET1 (Pin 9): Output Voltage Set. This pin is the noninverting input to Channel 1’s LDO error amplifier and the
regulation setpoint. A precision, trimmed 50µA flows out of
SET1. Connecting a resistor from SET1 to GND programs
Channel 1’s output voltage (VOUT = 50µA • RSET1, Ohm’s
Law). Output voltage ranges from 1V to 20V. Connecting
a capacitor from SET1 to Pin 7’s GND improves transient
response, PSRR, noise performance and soft starts the
output. SET1 requires a minimum capacitor of 10nF. Larger
value capacitors reduce output noise while correspondingly increasing startup time. For precision applications,
an external reference or power supply may drive SET1 (see
Applications Information section). This power supply must
be current-limited to < 1mA or diode-clamped to exceed
VLDOIN1 by no more than 1V.
EN1 (Pin 10): Channel 1’s Enable. Pulling EN1 low disables
Channel 1’s boost converter and linear regulator, thus
turning the output off. Its typical rising threshold is 1.23V
with 125mV of hysteresis. Pulling both EN1 and EN2 low
activates the micropower shutdown state in which internal
circuit blocks shared by both channels are also disabled.
EN1 can be used as a digital shutdown pin or, with the
use of an external resistor divider, an external VIN UVLO
threshold can be programmed. If EN1 is unused, tie EN1
to VIN. Do not float EN1.
EN2 (Pin 11): Channel 2’s Enable. Pulling EN2 low turns
off Channel 2’s boost converter and linear regulator, thus
turning the output off. Its typical rising threshold is 1.23V
with 125mV of hysteresis. Pulling both EN1 and EN2 low
activates the micropower shutdown state in which internal
circuit blocks shared by both channels are also disabled.
EN2 can be used as a shutdown pin or, with the use of an
external resistor divider, an external VIN UVLO threshold
can be programmed. If EN2 is unused, tie EN2 to VIN. Do
not float EN2.
SET2 (Pin 12): Output Voltage Set. This pin is the noninverting input to Channel 2’s LDO error amplifier and the
regulation setpoint. A precision, trimmed 50µA flows out of
SET2. Connecting a resistor from SET2 to GND programs
Channel 2’s output voltage (VOUT2 = 50µA • RSET2, Ohm’s
Law). Output voltage ranges from 1V to 20V. Connecting a
capacitor from SET2 to Pin 14’s GND improves transient
response, PSRR, noise performance and soft starts the
output. SET2 requires a minimum capacitor of 10nF. Larger
value capacitors reduce output noise while correspondingly increasing startup time. For precision applications,
an external reference or power supply may drive SET2 (see
Applications Information section). This power supply must
be current-limited to < 1mA or diode-clamped to exceed
VLDOIN2 by no more than 1V.
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LT3095
PIN FUNCTIONS
OUT2 (Pin 13): Channel 2 Linear Regulator Output. This
pin supplies power to Channel 2’s load. Use a minimum
value 2.2µF ceramic capacitor with an ESR less than 0.1Ω
to prevent oscillations. Large load transient applications
require larger value output capacitors to limit peak voltage transients. See the applications information section
for more information on output capacitance. Return the
output capacitor and the load directly to Pin 14’s GND.
LDOIN2 (Pin 15): Channel 2 Linear Regulator Input. This
pin is Channel 2’s linear regulator input supply pin. Connect Pin 15 directly to BSTOUT2 at Pin 19.
RT (Pin 17): Oscillator Frequency Target. A single resistor
from RT to ground programs the internal oscillator from
450kHz to 2MHz. If synchronizing to an external clock,
connect a resistor to program the oscillator to a frequency
close to the SYNC clock frequency. Do not load the RT
pin with a capacitor.
SYNC (Pin 18): External Clock Synchronization Input.
Ground this pin to use the internal oscillator. Tie to a
logic-level clock source for external synchronization. Do
not leave floating.
10
BSTOUT2 (Pin 19): Channel 2 Step-Up Regulator Output.
This pin is Channel 2’s boost converter output. Connect
BSTOUT2 directly to LDOIN2. Connect the boost output
capacitor directly from BSTOUT2 to Pin 20’s GND. An
internal feedback loop regulates BSTOUT2’s voltage typically to (OUT2 + 2V). This optimizes transient response
and PSRR performance of the Linear Regulator.
SW2 (21): Channel 2 Step-Up Regulator Switch Node.
The SW pin is connected internally to the collector of the
power switch and Schottky anode of the corresponding
boost regulator. This is the path for boost input power of
Channel 2.
IN (Pins 23, 22): Input Bias Supply. The IN pins supply
current to the INTVCC regulator and switch drivers. These
pins must be locally bypassed with a minimum of 2.2µF
of low-ESR capacitance. Place the positive terminal of the
capacitor as close as possible to IN pins and return near
to Pin 1 & PIN 20’s GND. Note that Pins 22 and 23 are
internally connected.
SW1 (24): Channel 1 Step-Up Regulator Switch Node.
The SW pin is connected internally to the collector of the
power switch and Schottky anode of the corresponding
boost regulator. This is the path for boost input power of
Channel 1.
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BLOCK DIAGRAM
IN
23
IN
22
IN
SW1
SW2
INTVCC
INTVCC
BOOST CURRENT
CONTROL
BOOST CURRENT
CONTROL
24
21
INTVCC
2
+
–
1X
LDOIN1
2V
20
EN2
CLK2
UVLOB
CLK1
BSTOUT1
UVLOB
GND
EN1
GND
1
BSTOUT2
INTVCC
+
–
19
+
–
+
–
2V
+
–
+
1X
–
LDOIN2
6
15
50µA
+
50µA
EN1
EN2
UVLOB
–
UVLOB
+
–
OUT1
OUT2
8
13
SET1
SET2
9
12
GND
GND
7
14
EN1
10
+
–
+
–
EN1
EN2
INTVCC
1.23V
EN2
+
–
11
1.23V
+
–
BANDGAP
UVLOB
+
–
2.4V
CLK1
OSCILLATOR
–
+
CLK2
+
–
INTVCC
4
RT
17
SYNC
18
GND
5
GND
16
3095 BD
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LT3095
APPLICATIONS INFORMATION
The LT3095 is an easy-to-use step-up bias generator with
two independent channels supporting loads up to 50mA.
Since the boost converters are monolithic and feature internal compensation, the LT3095 is easy to configure with
a few external components. The output of each switcher is
post-regulated by a linear regulator to filter output ripple
and provide a precision DC voltage with very low noise for
biasing sensitive circuits and sensors. The output of each
channel is programmed with a single resistor and internal
feedback automatically regulates the output of each boost
converter to 2V above the corresponding linear regulator’s
output. The filtered outputs are protected by independent
current limit and thermal shutdown.
L
VIN
10µF
VIN
–
+1×
–
+
+
–
SW1
BSTOUT1
LDOIN1
program the output, simply choose the appropriate SET
pin resistor according to Ohm’s law:
RSET =
VOUT
50µA
The SET pin voltage is buffered to the output, so the linear
regulator always operates in unity gain configuration. This
allows optimal loop gain and bandwidth regardless of
output voltage. With this architecture, it is also possible
to drive the set pin externally for a dynamic supply (see
the Typical Applications section below).
The LT3095 step-up regulator tracks the output of the linear
regulator and maintains 2V typically between LDOIN and
OUT of each channel. This input-to-output voltage control
obviates the need to externally program the boost output
voltage and insures controlled power dissipation in the
linear regulator pass device, even if the target output voltage
is adjusted or programmed dynamically during operation.
Boost Output Capacitor/Linear Regulator Input Capacitor
CTRL
50µA
2V
+
–
GND
SET1
OUT1
2.2µF
RSET1
The LT3095 step-up converters are internally compensated
and require an output capacitor, which also serves as the
input capacitor for the linear regulator. A value of 10µF is
recommended. Consider capacitance degradation under
bias and temperature conditions, as outlined below. The
connection of the boost output capacitor on the PCB is
crucial for ripple performance, as discussed in the Pin
Functions section.
3095 F01
Figure 1. LT3095 Architecture (Single Channel)
Programming the Output Voltage
Figure 1 illustrates the architecture of the LT3095. The
boost converter simply regulates the difference between
LDOIN and OUT – no external feedback configuration is
necessary. The linear regulators have a single-resistorprogrammable reference architecture. An accurate,
temperature-compensated 50µA current flows out of the
SET pin and into an external resistor, RSET, to establish
the reference for the linear regulator output voltage. To
12
Linear Regulator Stability & Output Capacitor
The LT3095 linear regulators are stable with a minimum
output capacitance of 2.2µF (ESR < 0.1Ω). Use low-ESR
multilayer ceramic capacitors and give consideration to
the actual capacitance under bias and temperature conditions. See the Effective Operating Capacitance section for
more information.
The linear regulator feedback loop has very high bandwidth,
allowing it to respond quickly to load steps and actively
correct input ripple feed-through up to frequencies near
the self-resonance of a typical multilayer ceramic capaci-
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APPLICATIONS INFORMATION
If capacitor types with higher ESR (>100 mΩ) or lower
self-resonant frequencies (< 500 kHz) must be used, it may
be necessary to parallel several output capacitors. This
lowers the effective ESR and ESL and can have beneficial
effects on ripple rejection.
Using an output capacitor with a value greater than the
minimum 2.2µF can improve ripple rejection under certain
conditions, as shown in the Typical Performance plots.
However, due to limitations in parasitic electromagnetic
coupling, the advantages may not be dramatic in practice.
A value of 2.2µF is recommended for most applications.
SET Pin (Reference Bypass) Capacitance
Within the bandwidth of the linear regulator, wideband
thermal noise and injected ripple at the output of the
LT3095’s built-in reference (that is, the SET pin) are
replicated at the output. Minimize this source of noise
by using an external capacitor to bypass the SET pin.
Table 1 shows the total RMS output noise in a 10Hz to
100kHz bandwidth and a 1kHz to 20MHz bandwidth for
several different values of CSET in a typical application.
The lower-bandwidth measurement reflects thermal and
shot noise only, while the higher-bandwidth measurement
includes residual ripple components from the switching converter. Both are influenced by the value of CSET.
A minimum of 10nF is required, but noise is reduced
substantially with CSET ≥ 100nF.
Table 1. Output Noise for Different Values of CSET
CSET
VOUT-AC
(µVRMS 10Hz to 100kHz)
VOUT-AC
(µVRMS 1kHz to 20MHz)
10nF
35
40
47nF
15
25
100nF
12
25
470nF
7
25
1µF
4
25
Single channel operation, VIN = 5V, VOUT = 18V, ILOAD = 50mA,
COUT = 2.2µF, CBSTOUT = 10µF
A system level consideration that may limit the value
of CSET is start-up time: when the part is enabled from
shutdown, the SET pin voltage rises with a time constant
of RSET • CSET. Since OUT tracks SET, this causes the
linear regulator output to soft-start. If very fast startup is
required and noise performance cannot be compromised,
use an auxiliary circuit to speed up the start time or drive
the SET pin externally (see Typical Applications).
Effective Operating Capacitance
The effective capacitance of a multilayer ceramic capacitor
varies over temperature and DC bias conditions, and may
be considerably lower than the manufacturer’s nominal
value. To ensure stable operation of the LT3095, make
sure that the boost and linear regulator output capacitors
meet the minimum requirement in their actual operating
conditions, after accounting for temperature and DC bias.
12
EFFECTIVE CAPACITANCE (µF)
tor. As an example, the loop bandwidth driving a 50mA
load with COUT = 2.2µF is about 1MHz. With such a high
bandwidth, the parasitic series resistance and inductance
of the output capacitor can have a noticeable impact on the
loop dynamics near the unity gain frequency. If the phase
response of the loop is degraded, transient output ringing
can result and supply ripple rejection may suffer. Avoid
these problems by using ceramic capacitors with ESR less
than 100mΩ; place the capacitor as close as possible to
the OUT pin and return directly to the adjacent GND pin.
See the discussion of board layout below for an example
PCB design that meets these requirements.
0805
1206
1210
10
8
6
4
2
0
ALL CAPACITORS X5R, 25V RATING
0
5
10
15
DC BIAS VOLTAGE (V)
20
3095 F02
Figure 2. Capacitance Degradation with DC Bias Voltage
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LT3095
APPLICATIONS INFORMATION
Capacitance degradation under DC bias can be dramatic.
In some cases, the effective value of a capacitor may be
less than 20% of the nominal value, even at voltages well
below the nominal voltage rating of the component. Different dielectric materials have different sensitivities to
DC bias, with X5R and X7R offering good performance.
Package size also has a large influence on the effective
capacitance achieved at higher voltages. In general, capacitors in physically larger packages suffer less degradation
under DC bias than capacitors of the same voltage rating
in a smaller size. Figure 2 shows typical bias curves for
three X5R capacitors with nominal values of 10µF, all rated
for 25V, but in different package sizes.
The effective values of some ceramic capacitors can
also degrade significantly with temperature, as Figure 3
demonstrates. Of the common dielectric types, X5R and
X7R offer relatively stable capacitance over a wide temperature range. Both are widely available in a variety of
sizes and values.
40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
CHANGE IN VALUE (%)
20
X5R
0
–20
–40
Y5V
–60
–80
–100
–50
–25
0
25
75
50
TEMPERATURE (°C)
100
125
3095 F03
Figure 3. Capacitance De-Rating with Temperature
In the case of the linear regulator output capacitor, the
regulator can show ringing or degraded ripple rejection
if the effective capacitance is more than 20% below the
recommended minimum of 2.2µF. The recommended
minimum value for CBSTOUT — the output capacitor for
the boost converter — is 10µF; however, lower effective
values may be tolerable in certain applications. At high
duty cycles, for example, the linearized transconductance
of the current control loop is reduced, and less output
capacitance is required to achieve the same unity gain
14
frequency. When using a boost output capacitor with effective capacitance below 8µF, verify the loop dynamics
experimentally or with an AC model to ensure adequate
loop stability in realistic operating conditions.
Programming the Switching Frequency
The LT3095’s two switching regulator channels run out of
phase to reduce input current ripple amplitude. An internal
oscillator generates a precise clock that can be programmed
from 450kHz to 2MHz by connecting an external resistor
from the RT pin to ground. Table 2 lists the closest 1%
resistor values for a few common frequencies. Refer to the
Typical Performance section for a plot of clock frequency
as a function of RT.
Table 2. SW Frequency vs RT Value
fOSC (MHz)
RT (kΩ)
0.45
232
0.50
210
0.75
137
1.00
100
1.50
63.4
2.00
44.2
Alternatively, an external frequency source can be used to
synchronize the switching edges to a system clock using
the SYNC pin. The voltage and duty-cycle requirements
for the logic level SYNC signal are listed in the Electrical
Characteristics table. When using the SYNC pin to set the
frequency, connect a resistor to the RT pin as if programming the oscillator to the SYNC frequency. Use a resistor
with 1% tolerance to insure appropriate scaling of internal
control signals. The LT3095 will sense a pulsed signal on
the SYNC pin and override the oscillator to align the switch
edges with the external clock.
When using the internal oscillator, each channel will run
at the programmed switching frequency, fOSC, and the
power switches will turn on 180º out-of-phase. If SYNC
functionality is used, each channel will run at the SYNC
pulse frequency: one power switch will turn on at the rising edge of the SYNC input, and the other power switch
at the falling edge.
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APPLICATIONS INFORMATION
Inductor Selection & Boost Loop Stability
The choice of inductor for the boost converter affects the
system efficiency, loop stability, and solution size. As a
starting point, choose a value which results in ≤30% current
ripple when the switcher is operating at its peak current of
about 1A. The minimum inductor value that satisfies this
requirement can be calculated from the input and output
voltages and the switching frequency:
( VIN – 0.5) ( VOUT + 3 – VIN)
0.3 ( VOUT + 3) fSW
Finally, with a low inductance, the converter may operate
at or near discontinuous conduction mode, even at large
loads. While stability is guaranteed in discontinuous
conduction mode, switch node ringing may introduce
new frequency components into the system. In extreme
cases (e.g. high boost ratio and heavy load), the step-up
converter may not be able to deliver 50mA average output
current, even when the inductor is energized to the switch
peak current limit each clock cycle.
In some cases, it may be appealing to use a smaller inductor
value because of solution size or other constrains. Before
reducing the inductance, there are some considerations
that must be taken into account. A smaller inductor will
result in increased output ripple and additional conduction losses in the inductor and power switch. Higher peak
currents will translate to increased EMI radiation during
switching, which can easily couple frequency content onto
the output of the linear regulators.
Use an inductor with a sufficient current rating to prevent
core saturation, which can cause the effective inductance
to drop dramatically and the current to jump very quickly.
In case of runaway, an internal protection circuit senses
very high currents in the internal catch diode and prevents
the power switch from turning on until the inductor current
falls. This safety mechanism protects the power switch,
but damage to the power Schottky diode or overvoltage
of the boost converter’s output are still possible. For these
reasons, avoid inductor core saturation during normal
operation: choose an inductor rated for the peak current
in your application, with appropriate margin for tolerances
and transient overshoot. If in doubt, a rating of 1.5A will
provide insurance against saturation in all normal operating conditions.
Furthermore, a small inductor may make the current-control
loop unstable in continuous conduction mode, causing
subharmonic oscillations in the inductor current. This can
introduce unpredictable spectral content into the system.
Subharmonic oscillation is only a concern for duty cycles
greater than 50%, and can be avoided by making sure the
inductor meets the following requirement:
Regarding switching supply loop stability, it is well known
that the control loop of a boost converter has an inherent
right half-plane zero. Fundamentally, this is due to the fact
that current is not delivered to the load while the inductor
is being energized. Thus, when the loop commands more
current, the output voltage temporarily drops. A linearized
approximation of the zero frequency is:
LMIN =
…where VOUT is the programmed voltage at the output of
the linear regulator, and VIN is the supply of the inductor
current.
L>
VOUT – VIN + 3
• 1µH for D < 0.75
1.25V
L>
VOUT – VIN + 3
• 1µH for D > 0.75
2.50V
where
D = 1–
VIN – 0.5
VOUT + 3
2
V (1– D)
fzero,RHP = BST
2πLILOAD
…where VBST is the output of the boost converter (approximately VOUT + 3V), D is the switch duty cycle, and
L is the inductor value. When this zero falls near the loop
unity gain frequency (typically around 50kHz), phase
margin is degraded. For this reason, avoid inductor values
much larger than suggested by the 30% ripple calculation
given above.
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LT3095
APPLICATIONS INFORMATION
High Frequency Edges & Passive Filtering Techniques
Figure 4 shows the output of the LT3095 boost converter
in a typical application with a 50mA load, before and after
filtering by the linear regulator. The most noticeable residual
switching feature is the short spike when the boost power
switch turns off. This edge is generated by high dI/dt circulating through the boost output capacitor parasitic and
the corresponding magnetic circuit on the PCB.
These edges can couple onto the output of the linear
regulator indirectly through parasitic capacitance in the
linear regulator or electromagnetically from one PCB trace
to another. The spikes contain high frequency (>1MHz)
content that the linear regulator control loop cannot actively filter out. Minimize the residual spike amplitude by
following the PCB layout guidelines provided in the next
section. In many applications, the energy associated with
the residual spikes is at a sufficiently high frequency that
it does not interfere with the load.
option is a small resistor — typically an Ohm or less to
avoid introducing a large load regulation term to the voltage
seen at the load. Another option is a low-ESR chip ferritebead or inductor. This solution offers the best rejection at
very high frequencies (>10 MHz); however, a resonance
is formed at a frequency of 1/ 2π LFILTERCLOAD that
can amplify noise and introduce a new ripple component
at the load. The peaking, or Q, associated with the filter
can be reduced by introducing a series damping resistor
or reducing the ratio LFILTER /CLOAD.
(
)
0.1Ω
OUT1
COUT
2.2µF
LT3095
CLOAD
1µF
LOAD
GND
3095 F05
Figure 5. Pi Network Filter
Figure 6 shows the residual noise at the output of the
LDO after it has been filtered with a 0.1Ω resistor and an
additional 1µF capacitor at the load. The high frequency
switch edges have been substantially reduced.
VBSTOUT
20mV/DIV
VOUT
50µV/DIV
VIN = 5Vdata0
Figure 4.
Output
VOUT = 15V
data1
ILOAD = 50mA
fOSC = 1MHz
20MHz BW
1µs/DIV
3095 F04
Transient Showing Spikes
In cases where extreme ripple rejection up to very high
frequencies is required, a passive filter at the output of
the LDO can be used. Form a pi-network by placing the
output capacitor very close to the LT3095 and another
capacitor directly at the load, as shown Figure 5. Make
sure the additional capacitor is large enough to present
low impedance to the load across the full frequency range.
PCB trace inductance between the LT3095 and load will
provide some high-frequency filtering, but passives with
additional impedance can offer further improvement. One
16
VBSTOUT
20mV/DIV
VIN = 5Vdata0
VOUT = 15V
data0
ILOAD = 50mA
fOSC = 1MHz
20MHz BW
VOUT
50µV/DIV
1µs/DIV
3095 F06
Figure 6. Residual Ripple with Passive Pi Filter
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APPLICATIONS INFORMATION
CBST0UT2
COUT2
L2
L1
COUT1
CBST0UT1
3095 F07
Figure 7. Example PCB Layout, Top Layer (Demo Board DC2270A)
Board Layout
Figure 7 shows a compact two-layer PCB layout designed
to minimize the residual switching content at the output.
Perhaps the most important component placement is the
boost output capacitor, CBSTOUT. A high frequency “hot”
loop is formed by the internal power switch, the Schottky
diode, and CBSTOUT. The inductance of this loop generates
spikes in the boost output and radiates high frequency
electromagnetic energy that can feed through the parasitic
capacitance of the linear regulator or couple directly to
the post-regulator output. Minimize the size of the loop
by placing the output capacitor as close as possible to
the BSTOUT and adjacent GND pins. Do not force current
to flow through vias while circulating around this loop.
Furthermore, minimize the SW node trace area to prevent
electrostatic coupling of the high dV/dt signal.
While the boost converter hot loop generates electromagnetic energy, the LDO output and reference traces act as
antennas that can pick up and deliver it to the load. Reduce
coupling onto the output by minimizing the unshielded
output PCB trace area and returning COUT and CSET as
close as possible to the adjacent GND pin. Also take care
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LT3095
APPLICATIONS INFORMATION
to eliminate any ground loops between this return point
and the reference ground of the regulator’s load. In a
multilayer board, shielding the output trace with ground
conductors can also help prevent coupling.
The presence of a solid ground plane underneath the
routing traces can significantly reduce electromagnetic
radiation and coupling. The dielectric thickness separating the signal traces and ground plane determine how
effective it is. For more information on this topic, and an
extended discussion of PCB layout for high-frequency
switching converters, read Application Note 139 – Power
Supply Layout and EMI. The same principles that apply
to EMI generation by stand-alone switching converters
apply to LT3095 applications where residual ripple is of
critical concern. In the end, electromagnetic coupling is
likely to be responsible for most of the frequency content
observed at the LT3095 output.
Thermal Considerations
The LT3095 has an internal thermal limiting circuit
that will protect the device under overload conditions.
For continuous normal load conditions, do not exceed
the 125°C maximum junction temperature. Carefully consider all sources of thermal resistance from
junction-to-ambient. This includes (but is not limited to)
junction-to-case, case-to-heat sink interface, heat sink
resistance or circuit board-to-ambient, as the application
18
dictates. Consider all additional, adjacent heat generating
sources in proximity on the PCB.
Surface mount packages provide the necessary heat
sinking by using the heat spreading capabilities of the
PC board, copper traces and planes. Surface mount heat
sinks, plated through-holes and solder-filled vias can also
spread the heat generated by power devices.
Junction-to-case thermal resistance is specified from the
IC junction to the bottom of the case directly, or the bottom of the pin most directly in the heat path. This is the
lowest thermal resistance path for heat flow. Only proper
device mounting ensures the best possible thermal flow
from this area of the packages to the heat sinking material.
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
In typical applications, where VIN is below the desired
output voltage, the boost converter will maintain 2V across
the linear regulator pass device. In this case, the power
dissipation in the linear regulators will be limited to a
few hundred milliwatts, even at full load. In applications
where the input voltage may exceed one or both of the
outputs, the linear regulator will dissipate approximately
(VIN – VOUT) • ILOAD. In this case, power dissipation may
be substantial and extra care should be taken to ensure
the maximum junction temperature is not exceeded.
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LT3095
TYPICAL APPLICATIONS
5V VIN with 5V and 15V Outputs and VIN UVLO = 4V
VIN
5V ±10%
2.2µF
L1
6.8µH
EN1
IN
SW2
GND
GND
BSTOUT1
VOUT1
5V, 50mA
2.2µF
10µF
BSTOUT2
LDOIN1
100k
1%
50k
1%
LT3095
10µF
0.1µF
EN2
SW1
113k
1%
L2
10µH
LDOIN2
OUT1
OUT2
SET1
SET2
INTVCC
VOUT2
15V, 50mA
2.2µF
RT
0.1µF
100k
SYNC
GND
300k
1%
0.1µF
GND
3095 TA03
L1: COILCRAFT LPS4012-682MRB
L2: COILCRAFT LPS4012-103MRB
5V to 20V VIN with 5V and 12V Outputs and SEPIC on Channel 2 for Continuous Output Current
VIN
5V to 20V
2.2µF
L1
2.2µH
EN1
VIN
SW1
15µH
EN2
SW2
GND
LT3095
10µF
L2
15µH
1µF
GND
D1
VOUT1
5V, 50mA
LDOIN = VIN – Vf
WHEN VIN > VOUT – 3V,
LDO REGULATES OUT
2.2µF
0.1µF
100k
1%
BSTOUT1
LDOIN1
BSTOUT2
OUT2
SET1
SET2
0.1µF
FLOAT
LDOIN2
OUT1
INTVCC
VOUT2
12V, 50mA
RT
SYNC
GND
10µF
100k
243k
1%
2.2µF
0.1µF
GND
3095 TA03
L1 = COILCRAFT LPS4012-222MR
L2 = WÜRTH 74489430150T
D1 = ON SEMI MBR130
Vf = INTERNAL BOOST REGULATOR SCHOTTKY FORWARD VOLTAGE
3095fa
For more information www.linear.com/LT3095
19
LT3095
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3095#packaging for the most recent package drawings.
UDD Package
24-Lead Plastic QFN (3mm × 5mm)
(Reference LTC DWG # 05-08-1833 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
3.65 ±0.05
1.50 REF
1.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
0.75 ±0.05
1.50 REF
23
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
24
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
5.00 ±0.10
1
2
3.65 ±0.10
3.50 REF
1.65 ±0.10
(UDD24) QFN 0808 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
20
3095fa
For more information www.linear.com/LT3095
LT3095
REVISION HISTORY
REV
DATE
DESCRIPTION
A
03/16
Changed Title of Graph
PAGE NUMBER
1
Changed Bandwidth in SET Pin section
13
Modified High Frequency Edges section
16
3095fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT3095
21
LT3095
TYPICAL APPLICATION
Programmable Outputs with Tracking
VIN
5V
L1
10µH
2.2µF
IN
EN1
EN2
SW1
SW2
GND
GND
LT3095
10µF
BSTOUT1
10µF
BSTOUT2
LDOIN1
VOUT1 = VDAC,
50mA
2.2µF
L2
15µH
LDOIN2
OUT1
OUT2
SET1
SET2
INTVCC
0.1µF
2.2µF
40k
RT
SYNC
GND
VOUT2 = VDAC + 2V,
50mA
100k
GND
3095 TA04
VDAC
DAC
0.1µF
L1: VISHAY IHLP-2525CZER100M51
L2: VISHAY IHLP-2525CZER150M51
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT3048
Low Noise Bias Generator in 2mm × 2mm DFN VIN: 2.7V to 4.8V, 40mA LDO, 300mA Boost Switch, Noise:
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