LT1205CS

LT1203/LT1205 150MHz Video Multiplexers FEATURES s s s s s s s s s s s s s DESCRIPTIO – 3dB Bandwidth: 150MHz 0.1dB Gain Flatness: 30MHz Channel-to-Channel Switching Time: 25ns Turn-On/Turn-Off Time: 25ns High Slew Rate: 300V/µs Disabled Output Impedance: 10MΩ 50mV Switching Transient Channel Separation at 10MHz: > 90dB Differential Gain: 0.02% Differential Phase: 0.02° Wide Supply Range: ± 5V to ± 15V Output Short-Circuit Protected Push-Pull Output The LT1203 is a wideband 2-input video multiplexer designed for pixel switching and broadcast quality routing. The LT1205 is a dual version that is configured as a 4-input, 2-output multiplexer. These multiplexers act as SPDT video switches with 10ns transition times at toggle rates up to 30MHz. The – 3dB bandwidth is 150MHz and 0.1dB gain flatness is 30MHz. Many parts can be tied together at their outputs by using the enable feature which reduces the power dissipation and raises the output impedance to 10MΩ. Output capacitance when disabled is only 3pF and the LT1203 peaks less than 3dB into a 50pF load. Channel crosstalk and disable isolation are greater than 90dB up to 10MHz. An on-chip buffer interfaces to fast TTL or CMOS logic. Switching transients are only 50mV with a 25ns duration. The LT1203 and LT1205 outputs are protected against shorts to ground. The LT1203/LT1205 are manufactured using Linear Technology’s proprietary complementary bipolar process. The LT1203 is available in both the 8-lead PDIP and SO package while the LT1205 is available in the 16-lead narrow body SO package. APPLICATI s s s s s s s S Broadcast Quality Video Multiplexing Picture-in-Picture Switching HDTV Computer Graphics Title Generation Video Crosspoint Matrices Video Routers TYPICAL APPLICATI High Speed RGB MUX CHANNEL SELECT RED 1 RED 2 V– GREEN 1 GREEN 2 V– +1 +1 +1 +1 LT1205 V+ EN LOGIC V+ EN LOGIC VOUT GREEN VOUT RED Large-Signal Response BLUE 1 BLUE 2 V– +1 LT1203 +1 V+ EN LOGIC LT1203 • TA01 VOUT BLUE U UO UO 1 LT1203/LT1205 ABSOLUTE AXI U RATI GS Operating Temperature Range ............... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Junction Temperature (Note 5) ............................ 150°C Lead Temperature (Soldering, 10 sec)................. 300°C Supply Voltage ...................................................... ±18V Signal Input Current (Note 1) ............................ ± 20mA Logic Input Current (Note 2).............................. ± 50mA Output Short-Circuit Duration (Note 3) ........ Continuous Specified Temperature Range (Note 4) ....... 0°C to 70°C PACKAGE/ORDER I FOR ATIO TOP VIEW VIN0 1 GND 2 VIN1 3 V – ORDER PART NUMBER 8 7 6 5 V+ VOUT EN LOGIC LT1203CN8* LT1203CS8* S8 PART MARKING 1203 4 N8 PACKAGE S8 PACKAGE 8-LEAD PLASTIC DIP 8-LEAD PLASTIC SOIC TJMAX = 150°C, θJA = 100°C/W (N) TJMAX = 150°C, θJA = 150°C/W (S) *See Note 4 Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS 0°C ≤ TA ≤ 70°C, ± 5V ≤ VS ≤ ± 15V, RL = 1k, pulse tested, EN pin open or high, unless otherwise noted. SYMBOL VOS ∆VOS/∆T IIN RIN CIN COUT VIN PSRR PARAMETER Output Offset Voltage Output Offset Matching Output Offset Drift Input Current Input Resistance Input Capacitance Disabled Output Capacitance Input Voltage (Note 1) Power Supply Rejection Ratio Gain Error VS = ± 5V, VIN = ± 2V VS = ±15V, VIN = ± 2V Input Selected Input Deselected EN Pin Voltage ≤ 0.8V VS = ± 5V VS = ±15V VS = ± 4.5 to ±15V VS = ±15V, VIN = ± 2V, RL = 1k VS = ±15V, VIN = ± 2V, RL = 400Ω VS = ± 5V, VIN = ± 2V, RL = 1k q q q q q q CONDITIONS Any Input Selected Between Outputs q q q q q q 2 U U W WW U W TOP VIEW VINO 1 GND 2 VIN1 3 V– 4 16 V + 15 VOUT1 14 EN1 13 LOGIC 1 12 V + 11 VOUT2 10 EN2 9 LOGIC 2 ORDER PART NUMBER LT1205CS* VIN2 5 GND 6 VIN3 7 V– 8 S PACKAGE 16-LEAD PLASTIC SOIC TJMAX = 150°C, θJA = 100°C/W MIN TYP 10 0.3 40 0.6 MAX 30 5 5 UNITS mV mV µV/°C µA MΩ MΩ pF pF pF V V dB 1 2 5 5 2.6 2.6 2.8 ±2 ±2 60 ± 2.8 ± 3.0 70 2 6 3 4 10 6 % % % LT1203/LT1205 ELECTRICAL CHARACTERISTICS 0°C ≤ TA ≤ 70°C, ± 5V ≤ VS ≤ ± 15V, RL = 1k, pulse tested, EN pin open or high, unless otherwise noted. SYMBOL VOUT PARAMETER Output Voltage Overload Swing (Note 1) IOUT ROUT IS Output Current Enabled Output Resistance Disabled Output Resistance Supply Current (LT1203) Supply Current (LT1205) VIL VIH Logic Low Logic High Enable Low Enable High IIL IIH IEN Digital Input Current Low Digital Input Current High Enable Pin Current CONDITIONS VS = ±15V, VIN = ± 2V, RL = 400Ω VS = ± 5V, VIN = ± 2V, RL = 1k VS = ±15V, VIN = ± 5V VS = ± 5V, VIN = ± 5V VS = ±15V, VIN = ± 2V, RL = 400Ω VS = ± 5V, VIN = ± 2V, RL = 1k EN Pin Voltage = 2V, VOUT = ± 2V, VS = ±15V EN Pin Voltage = 0.5V, VOUT = ± 2V, VS = ±15V EN Pin Voltage = 2V EN Pin Voltage = 0.5V EN Pin Voltage = 2V EN Pin Voltage = 0.5V Logic Pin Logic Pin EN Pin EN Pin LT1203 Pin 5, LT1205 Pins 9, 13 = 0V LT1203 Pin 5, LT1205 Pins 9, 13 = 5V LT1203 Pin 6, LT1205 Pins 10, 14 q q q q q q q q q q q q q q q q q q q MIN ±1.8 ±1.8 TYP ±1.90 ±1.94 ± 0.9 ± 0.9 MAX UNITS V V ±1.5 ±1.5 V V mA mA ± 4.5 ±1.8 1 ± 4.75 ± 2.00 20 10 10.0 5.8 20.0 11.6 42 14 8 28 16 0.8 Ω MΩ mA mA mA mA V V V V µA nA µA 2 0.5 2 1.5 10 20 6.5 200 80 AC CHARACTERISTICS SYMBOL SR FPBW tSEL PARAMETER Slew Rate (Note 6) Full Power Bandwidth (Note 7) TA = 25°C, VS = ±15V, RL = 1k, EN pin open or high, unless otherwise noted. CONDITIONS VOUT = 2VP-P MIN 180 28.6 TYP 300 47.7 25 25 20 2.6 2.9 5 90 110 50 30 0.02 0.02 0.02 35 35 35 MAX UNITS V/µs MHz ns ns ns ns ns % dB dB mVP-P ns % DEG dB Channel-to-Channel Select Time (Note 8) RL = 10k Enable Time (Note 9) RL = 1k Disable Time (Note 9) RL = 1k VOUT = 250mVP-P, 10% to 90% VOUT = 250mVP-P VOUT = 250mVP-P RS = 10Ω RL = 10Ω, EN Pin Voltage ≤ 0.8V All VIN = 0V 1%, VOUT = 1V VS = ±15V, RL = 10k VS = ±15V, RL = 10k RL = 100k, CL = 30pF, VOUT = 500mVP-P, f = 1MHz Small-Signal Rise and Fall Time Propagation Delay Overshoot Crosstalk (Note 10) Chip Disabled Crosstalk (Note 10) Channel Select Output Transient tr, tf tS Settling Time Differential Gain (Note 11) Differential Phase (Note 11) Insertion Loss The q denotes specifications which apply over the specified temperature range. Note 1: The analog inputs (pins 1, 3 for the LT1203, pins 1, 3, 5, 7 for the LT1205) are protected against ESD and overvoltage with internal SCRs. For inputs ≤ ± 2.8V the SCR will not fire. Voltages above 2.8V will fire the SCR and the DC current should be limited to 20mA. To turn off the SCR the pin voltage must be reduced to less than 1V or the current reduced to less than 600µA. 3 LT1203/LT1205 Note 2: The digital inputs (pins 5, 6 for the LT1203, pins 9, 10, 13, 14 for the LT1205) are protected against ESD and overvoltage with internal SCRs. For inputs ≤ ± 6V the SCR will not fire. Voltages above 6V will fire the SCR and the DC current should be limited to 50mA. To turn off the SCR the pin voltage must be reduced to less than 2V or the current reduced to less than 10mA. Note 3: A heat sink may be required depending on the power supply voltage. Note 4: Commercial grade parts are designed to operate over the temperature range of – 40°C to 85°C but are neither tested nor guaranteed beyond 0°C to 70°C. Industrial grade parts specified and tested over – 40°C to 85°C are available on special request, consult factory. Note 5: TJ is calculated from the ambient temperature TA and the power dissipation PD according to the following formulas: LT1203CN8: TJ = TA + (PD × 100°C/W) LT1203CS8: TJ = TA + (PD × 150°C/W) LT1205CS: TJ = TA + (PD × 100°C/W) Note 6: Slew rate is measured at ± 2.0V on a ± 2.5V output signal while operating on ±15V supplies, RL = 1k. Note 7: Full power bandwidth is calculated from the slew rate measurement: FPBW = SR/2πVPEAK Note 8: For the LT1203, apply 1VDC to pin 1 and measure the time for the appearance of 0.5V at pin 7 when pin 5 goes from 5V to 0V. Apply 1VDC to pin 1 and measure the time for disappearance of 0.5V at pin 7 when pin 5 goes from 0V to 5V. Apply 1VDC to pin 3 and measure the time for the appearance of 0.5V at pin 7 when pin 5 goes from 0V to 5V. Apply 1VDC to pin 3 and measure the time for disappearance of 0.5V at pin 7 when pin 5 goes from 5V to 0V. For the LT1205 the same test is performed on both MUXs. Note 9: For the LT1203, apply 1VDC to pin 1 and measure the time for the appearance of 0.5V at pin 7 when pin 6 goes from 0V to 5V. Pin 5 voltage = 0V. Apply 1VDC to pin 1 and measure the time for disappearance of 0.2V at pin 7 when pin 6 goes from 5V to 0V. Pin 5 voltage = 0V. Apply 1VDC to pin 3 and measure the time for the appearance of 0.5V at pin 7 when pin 6 goes from 0V to 5V. Pin 5 voltage = 5V. Apply 1VDC to pin 3 and measure the time for disappearance of 0.2V at pin 7 when pin 5 goes from 5V to 0V. Pin 5 voltage = 5V. For the LT1205 the same test is performed on both MUXs. Note 10: VIN = 0dBm (0.223VRMS) at 10MHz on one input with the other input selected and RS = 10Ω. For disable crosstalk all inputs are driven simultaneously. In disable the output impedance is very high and signal couples across the package; the load impedance determines the crosstalk. Note 11: Differential gain and phase are measured using a Tektronix TSG120 YC/NTSC signal generator and a Tektronix 1780R video measurement set. The resolution of this equipment is 0.1% and 0.1°. Ten identical MUXs were cascaded giving an effective resolution of 0.01% and 0.01°. TRUTH TABLE LOGIC 0 1 0 1 *Must be ≤ 0.5V EN 1 1 0* 0 VOUT VIN0 VIN1 HIGH ZOUT HIGH ZOUT TYPICAL PERFOR A CE CHARACTERISTICS ± 5V Frequency Response 5 4 3 2 VS = ± 5V TA = 25°C RL = ∞ 0 –20 –40 –60 5 4 3 2 VS = ±15V TA = 25°C RL = ∞ GAIN (dB) GAIN (dB) 1 0 –1 –2 –3 –4 –5 1 10 100 FREQUENCY (MHz) 4 UW ± 15V Frequency Response 0 –20 –40 –60 PHASE (DEG) PHASE (DEG) –80 –100 –120 –140 –160 –180 –200 1000 LT1203/05 • TPC01 1 0 –1 –2 –3 –4 –5 1 10 100 FREQUENCY (MHz) –80 –100 –120 –140 –160 –180 –200 1000 LT1203/05 • TPC02 LT1203/LT1205 TYPICAL PERFOR A CE CHARACTERISTICS – 3dB Bandwidth vs Supply Voltage 200 TA = 25°C RL = 10k PEAKING ≤ 0.5dB 180 FREQUENCY (MHz) CL = 50pF CL = 100pF 2 GAIN (dB) CL = 10pF CROSSTALK REJECTION (dB) 160 140 120 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±V) LT1203/05 • TPC03 Crosstalk Rejection vs Frequency –30 – 40 TA = 25°C RS = 0Ω RL = ∞ –30 DISABLE REJECTION (dB) POWER SUPPLY REJECTION RATIO (dB) CROSSTALK REJECTION (dB) –50 – 60 –70 –80 – 90 VS = ± 5V VS = ±15V –100 –110 1 10 FREQUENCY (MHz) 100 LT1203/05 • TPC06 Output Impedance (Enabled) vs Frequency 100 80 VS = ±15V TA = 25°C OUTPUT IMPEDANCE (Ω) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 60 40 30 20 10 10k 100k 1M 10M FREQUENCY (Hz) LT1203/05 • TPC09 UW 100M Frequency Response with Capacitive Loads 5 4 3 VS = ±15V TA = 25°C RL = ∞ CL = 20pF –30 – 40 –50 – 60 –70 –80 –90 Crosstalk Rejection vs Frequency VS = ±15V TA = 25°C RL = ∞ 1 0 –1 –2 –3 –4 –5 1 RS = 75Ω RS = 37.5Ω RS = 0Ω RS = 10Ω –100 –110 1 10 FREQUENCY (MHz) 100 LT1203/05 • TPC05 10 FREQUENCY (MHz) 100 LT1203/05 • TPC04 Disable Rejection vs Frequency –20 VS = ±15V TA = 25°C Power Supply Rejection Ratio vs Frequency 70 60 –PSRR 50 40 +PSRR 30 20 10 0 1 10 FREQUENCY (MHz) 100 LT1203/05 • TPC08 – 40 –50 – 60 –70 –80 –90 RL = ∞ RL = 1k RL = 100Ω RL = 10Ω VS = ±15V TA = 25°C RL = ∞ RS = 0Ω –100 –110 –120 1 10 FREQUENCY (MHz) 100 LT1203/05 • TPC07 Supply Current vs Supply Voltage (Enabled) 9.6 LT1203 RL = ∞ 9.2 –55° 125° 25° 5.0 5.2 Supply Current vs Supply Voltage (Disabled) LT1203 RL = ∞ 25° 125° 4.8 – 55° 8.8 8.4 8.0 4.6 7.6 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) 16 18 4.4 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) 16 18 LT1203/05 • TPC10 LT1203/05 • TPC11 5 LT1203/LT1205 TYPICAL PERFOR A CE CHARACTERISTICS Gain Error vs Temperature 8 7 6 5 4 3 2 1 –50 –25 RL = 1k VS = ±15V VIN = – 2V TO 2V RL = 400Ω INPUT BIAS CURRENT (µA) GAIN ERROR (%) 25°C 0.6 0.4 0.2 0 – 0.2 –55°C OUTPUT VOLTAGE (V) 50 25 75 0 TEMPERATURE (°C) LT1203/05 • TPC12 Settling Time to 1mV and 10mV vs Output Step 2.0 1.5 10mV 1.0 1mV VS = ±15V RL = 1k OUTPUT STEP (V) 0.5 0 –0.5 –1.0 10mV –1.5 –2.0 0 100 300 400 200 SETTLING TIME (ns) 500 1mV VIN1 to VIN0 Select Time LOGIC (PIN 5) LOGIC (PIN 5) VOUT (PIN 7) VOUT (PIN 7) VS = ±15V VINO = 1V RL = 10k VIN1 = 0V 6 UW 100 125 Input Bias Current vs Input Voltage 1.2 1.0 0.8 VS = ±15V RL = ∞ 125°C 4 3 2 1 0 –1 –2 –3 –3 –2 1 2 –1 0 INPUT VOLTAGE (V) 3 4 –4 Output Voltage vs Input Voltage VS = ±15V TA = 25°C RL = 1k – 0.4 –4 –5 – 4 –3 –2 –1 0 1 2 INPUT VOLTAGE (V) 3 4 5 LT1203/05 • TPC13 LT1203/05 • TPC14 Small-Signal Rise Time RL = 1k LT1203/05 • TPC16 LT1203/05 • TPC15 VIN0 to VIN1 Select Time LT1203/05 • TPC17 VS = ±15V VINO = 1V RL = 10k VIN1 = 0V LT1203/05 • TPC18 LT1203/LT1205 TYPICAL PERFOR A CE CHARACTERISTICS Channel 1 Enable Channel 1 Disable EN (PIN 6) VOUT (PIN 7) VS = ±15V RL = 1k VINO = 1V VIN1 = 0V APPLICATI Input Protection S I FOR ATIO The logic inputs have ESD protection (≥ 2kV) and shorting them to 12V or 15V will cause excessive current to flow. Limit the current to less than 50mA when driving the logic above 6V. The analog inputs are protected against ESD and overvoltage with internal SCRs. For inputs ≥ ± 2.8V the SCRs will fire and the DC current should be limited to 20mA. Power Supplies The LT1203/LT1205 will operate from ± 5V (10V total) to ±15V (30V total) and is specified over this range. Characteristics change very little over this voltage range. It is not necessary to use equal value supplies however, the output offset voltage will change. The offset will change about 300µV per volt of supply mismatch. The LT1203/LT1205 have a very wide bandwidth yet are tolerant of power supply bypassing. The power supplies should be bypassed with a 0.1µF or 0.01µF ceramic capacitor within 0.5 inch of the part. Circuit Layout Use a ground plane to ensure a low impedance ground is available throughout the PCB layout. Separate the inputs U W UW EN (PIN 6) VOUT (PIN 7) LT1203/05 • TPC19 VS = ±15V VINO = 1V RL = 1k VIN1 = 0V LT1203/05 • TPC20 U UO with ground plane to ensure high channel separation. For minimum peaking, maximum bandwidth and maximum gain flatness sockets are not recommended because they can add considerable stray inductance and capacitance. If a socket must be used, use a low profile, low capacitance socket such as the SamTec ISO-308. Switching Transients The LT1203/LT1205 use input buffers to ensure switching transients do not couple to other video equipment sharing the input line. Output switching transients are about 50mVP-P with a 20ns duration and input transients are LT1203 Channel-to-Channel Switching Transient OUTPUT 50mV/DIV INPUT 20mV/DIV LOGIC (PIN 5) RS = 50Ω LT1203/05 • AI01 7 LT1203/LT1205 APPLICATI S I FOR ATIO CMOS MUX Channel-to-Channel Switching Transient OUTPUT 1V/DIV INPUT 1V/DIV LOGIC CONTROL RS = 50Ω NOTE: 50 TIMES LARGER THAN LT1203 TRANSIENT LT1203/05 • AI02 LT1203 Switching Inputs LOGIC (PIN 5) OUTPUT (PIN 7) CHANNEL 1 = 0V CHANNEL 2 = 2MHz SINEWAVE LT1203/05 • AI03 C4 4.7µF C3 4.7µF J1 RED 1 R1 75Ω J2 RED 2 R2 75Ω J3 GREEN 1 R3 75Ω J4 GREEN 2 R4 75Ω 1 2 3 4 5 6 7 8 +1 +1 LT1205 +1 +1 16 15 14 13 12 11 10 9 C2 0.1µF R8* 10k R14 1.5k R13 1.5k 5 6 7 8 R15 1.5k R7* 10k R12 1.5k 2 3 J5 BLUE 1 R5 75Ω 1 J6 BLUE 2 R6 75Ω 2 3 4 C1 0.1µF +1 LT1203 +1 8 7 6 5 – LT1260 R9* 10k *OPTIONAL Figure 1. RGB MUX 8 + – 4 + – + + U only 10mVP-P. A photo of the switching transients from a CMOS MUX shows glitches to be 50 times larger than on the LT1203. Also shown is the output of the LT1203 switching on and off a 2MHz sinewave cleanly and without abnormalities. Pixel Switching The multiplexers are fabricated on LTC's Complementary Bipolar Process to attain fast switching speed, high bandwidth, and a wide supply voltage range compatible with traditional video systems. Channel-to-channel switching time and Enable time are both 25ns, therefore delay is the same when switching between channels or between ICs. To demonstrate the switching speed of the LT1203/LT1205 the RGB MUX of Figure 1 is used to switch RGB Workstation inputs with a 22ns pixel width. Figure 2a is a photo showing the Workstation output and RGB MUX output. The slight rise time degradation at the RGB MUX output is due to the bandwidth of the LT1260 current feedback amplifier used to drive the 75Ω cable. In Figure 2b, the LT1203 switches to an input at zero at the end of the first pixel and removes the following pixels. J8 ENABLE J7 LOGIC V+ V– GND R11 1.5k R10 1.5k 16 1 R 15 14 13 G 12 11 R17 75Ω J10 GREEN R16 75Ω J9 RED W U UO + B 10 9 R18 75Ω J11 BLUE LT1203/05 • F01 LT1203/LT1205 APPLICATI WORKSTATION OUTPUT S I FOR ATIO GAIN (dB) RGB MUX OUTPUT LT1203/05 • F02a Figure 2a. Workstation and RGB MUX Output WORKSTATION OUTPUT RGB MUX OUTPUT LT1203/05 • F02b Figure 2b. RGB MUX Output Switched to Ground After One Pixel Demonstration Board A Demonstration Board (#041) of the RGB MUX in Figure 1 has been fabricated and its layout is shown in Figure 3. The small-signal bandwidth of the RGB MUX is set by the bandwidth of the LT1260. The stray capacitance of the surface mount feedback resistors RF and RG restricts the – 3dB bandwidth to about 95MHz. The bandwidth can be improved by about 20% using the through-hole LT1260 and components. A frequency response plot in Figure 4 shows that the R, G, and B amplifiers have slightly different frequency responses. The difference in the G amplifier is due to different output trace routing to feedback resistor R13. VOUT 1V/DIV U 4 3 2 1 R, B 0 –1 –2 –3 –4 1 10 100 FREQUENCY (MHz) 1000 LT1203/05 • F04 W U UO VS = ±15V RL = 150Ω RF = RG = 1.3k G Figure 4. RGB MUX Frequency Response of Demonstration Board #041 Input Expansion The output impedance of the LT1203/LT1205 is typically 20Ω when enabled and 10MΩ when disabled or not selected. This high disabled output impedance allows the output of many LT1205s to be shorted together to form large crosspoint arrays. With their outputs shorted together, shoot-through current is low because the “on” channel is disabled before the “off” channel is activated. Timing and Supply Current Waveforms ENABLE IC #1 ENABLE IC #2 5V/DIV 5V/DIV IS 10mA/DIV LT1203/05 • AI04 Four LT1205s are used in Figure 5 to form a 16-to-1 multiplexer which is very space efficient and uses only six SO packages. In this application 15 switches are turned off and only one is active. An attenuator is formed by the 15 deselected switches and the active device which has an 9 LT1203/LT1205 041A R1 LOGIC ENABLE V– V+ GND R1 R2 R R2 R3 U1 R7 R12 R11 R10 C3 U3 R16 R17 G G1 G2 R4 C1 U2 R13 C2 R8 R14 R9 R15 C4 R18 B B1 R5 B2 R6 (408) 432-1900 LT1203/LT1205 FAST SWITCHING RGB MULTIPLEXER DEMO BOARD COPYWRITE '93 MADE IN USA LT1205/03 • F03 Figure 3. Demo Board #041 Layout 10 LT1203/LT1205 APPLICATI S I FOR ATIO –15V 15V C1 0.1µF CH0 R1 75Ω 1 2 3 4 5 6 7 8 +1 +1 +1 U1 LT1205 +1 16 15 14 13 12 11 10 9 C2 0.1µF 15 14 13 12 11 10 9 7 Y0 Y1 Y2 Y3 Y5 Y6 Y7 1 2 3 4 5 6 7 8 +1 +1 +1 +1 U2 LT1205 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 +1 +1 +1 +1 U3 LT1205 16 15 14 13 12 11 10 9 1 2 3 4 5 6 CH15 R16 75Ω C3 0.1µF 7 8 +1 +1 +1 +1 U4 LT1205 16 15 14 13 12 11 10 9 C4 0.1µF LT1203/05 • F05 Figure 5. 16-to-1 Multiplexer and Truth Table + U GND 5V C7 0.1µF A 16 8 A B C 1 2 3 D 6 5 4 EN B C U5 Y4 74HCT238 G1 G2B G2A OPTIONAL RX 10k W U UO + C5 4.7µF 2 + – 7 6 3 U6 LT1252 4 RF 1.6k RS 75Ω OUTPUT C6 4.7µF RG 1.6k TRUTH TABLE LOGIC SELECT C B A X X X L L L L L H L H L L H H H L L H L H H H L H H H L L L L L H L H L L H H H L L H L H H H L H H H ENABLE EN L H H H H H H H H H H H H H H H H OUTPUT OFF CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 D X L L L L L L L L H H H H H H H H 11 LT1203/LT1205 APPLICATI S I FOR ATIO output impedance of only 25Ω at 10MHz. This attenuator is responsible for the outstanding All Hostile Crosstalk Rejection of 90dB at 10MHz with 15 input signals. Several suggestions to attain this high rejection include: 1. Mount the feedback resistors for the surface mount LT1252 on the back side of the PC board. 2. Keep the feedback trace (pin 3) of the LT1252 as short as possible. 3. Route V + and V – for the LT1205s on the component (top) side and under the devices (between inputs and outputs). 4. Use the backside of the PC board as a solid ground plane. Connect the LT1205 device grounds and bypass capacitors grounds as vias to the backside ground plane. 16-to-1 MUX, Switching LT1205 Enable Lines 5V SELECT LINE C 0V GAIN (dB) 1V 0V VIN4 = 0V VIN0 = 1V RF = RG = 1.6k RL = 100Ω LT1203/05 • AI05 16-to-1 Multiplexer All Hostile Crosstalk Rejection –20 HOSTILE CROSSTALK REJECTION (dB) –40 VS = ±15V RS = 10Ω RL = 100Ω –60 –80 –100 –120 1 10 FREQUENCY (MHz) 100 LT1203/05 • AI06 12 U 16-to-1 MUX Response 2 VS = ±15V RL = 100Ω RF = RG = 1.6k 0 –2 –4 –6 1 10 FREQUENCY (MHz) 100 LT1203/05 • AI07 W U UO Each “off” switch has 2.8pF of output capacitance and 15 “off” switches tied together represent a 48pF load to the one active switch. In this case the active device will peak about 3dB at 50MHz. An attribute of current feedback amplifiers is that the bandwidth can easily be adjusted by changing the feedback resistors, and in this application the LT1252’s bandwidth is reduced to about 60MHz using 1.6k feedback resistors. This has the effect of reducing the peaking in the MUX to 0.25dB and flattening the response to 0.05dB at 30MHz. 4 × 4 Crosspoint The compact high performance 4 × 4 crosspoint shown in Figure 6 uses four LT1205s to route any input to any or all outputs. The complete crosspoint uses only six SO packages and less than six square inches of PC board space. The LT1254 quad current feedback amplifier serves as a cable driver with a gain of 2. A ± 5V supply is used to ensure that the maximum 150°C junction temperature of the LT1254 is not exceeded in the SO package. With this supply voltage the crosspoint can operate at a 70°C ambient temperature and drive 2V (peak or DC) into a double-terminated 75Ω video cable. The feedback resistors of these output amplifiers have been optimized for this supply voltage. The – 3dB bandwidth of the crosspoint is over 100MHz with only 0.8dB of peaking. All Hostile Crosstalk Rejection is 85dB at 10MHz when a shorted input is routed to all outputs. To obtain this level of performance it is necessary to follow techniques similar to LT1203/LT1205 APPLICATI S I FOR ATIO –5V 5V GND 3 C1 0.1µF 1 R1 75Ω 2 3 4 5 6 7 8 +1 +1 +1 U1 LT1205 +1 16 15 14 13 12 11 10 9 6 1 2 3 4 5 CH1 J2 R2 75Ω CH2 J3 1 R3 75Ω 2 3 4 5 6 7 8 +1 +1 +1 U3 LT1205 +1 16 15 14 13 12 11 10 9 13 12 U5 74HC04 R7 10k R14 820Ω 6 7 8 +1 +1 +1 U2 LT1205 16 15 14 13 12 11 10 9 9 10 R12 820Ω C5 4.7µF R6 10k 5 R5 10k R10 820Ω C2 0.1µF CH0 J1 +1 + U6 D LT1254 14 – R15 820Ω 1 2 3 4 5 CH3 J4 R4 75Ω C3 0.1µF 6 7 8 +1 +1 +1 +1 U4 LT1205 16 15 14 13 12 11 10 9 C4 0.1µF A L L H H R8 10k R16 820Ω TRUTH TABLE SELECT LOGIC B L H L H INPUT CHANNEL CH0 CH1 CH2 CH3 LT1203/05 • F06 B A SELECT LOGIC OUTPUT 0 A B SELECT LOGIC OUTPUT 1 A B SELECT LOGIC OUTPUT 2 A B SELECT LOGIC OUTPUT 3 Figure 6. 4 × 4 Crosspoint and Truth Table + U + U6 A LT1254 1 R17 75Ω OUTPUT 0 J5 2 W U UO – R9 820Ω + U6 B LT1254 7 R18 75Ω OUTPUT 1 J6 – R11 820Ω + + – 4 U6 C LT1254 11 R13 820Ω 8 R19 75Ω OUTPUT 2 J7 C6 4.7µF R20 75Ω OUTPUT 3 J8 13 LT1203/LT1205 APPLICATI S I FOR ATIO those used in the 16-to-1 crosspoint with one additional suggestion: Surround the LT1205 output traces by ground plane and route them away from the (–) inputs of the other three LT1254s. Each pair of logic inputs labeled Select Logic Output is used to select a particular output. The truth table is used to select the desired input and is applied to each pair of logic inputs. For example, to route Channel 1 Input to Response of All Four Inputs for the 4 × 4 Crosspoint 2 0 HOSTILE CROSSTALK REJECTION (dB) GAIN (dB) –2 –4 –6 VS = ± 5V RF = RG = 820Ω RL = 100Ω 1 10 FREQUENCY (MHz) 100 200 LT1203/05 • AI08 –8 1 10 FREQUENCY (MHz) 100 LT1203/05 • AI09 4 × 4 Crosspoint, Switching Channel 0 to Channel 2 5V INPUT A OF SELECT LOGIC OUTPUT 0 0V CHANNEL 0 = 1V CHANNEL 2 = 0V 14 U Output 3, the 4th pair of logic inputs labeled Select Logic Output 3 is coded A = Low and B = High. To route Channel 3 Input to all outputs, set all eight logic inputs High. Channel 3 is the default input with all logic inputs open. To shut off all channels a pair of LT1259s can be substituted for the LT1254. The LT1259 is a dual current feedback amplifier with a shutdown pin that reduces the supply current to 0µA. 4 × 4 Crosspoint, All Hostile Rejection –40 VS = ± 5V RL = 100Ω RS = 0Ω –60 –80 –100 –120 LT1203/05 • AI10 W U UO LT1203/LT1205 SI PLIFIED SCHE ATIC V+ ENABLE LOGIC LOGIC GND LT1203/05 • SS PACKAGE DESCRIPTIO 0.300 – 0.320 (7.620 – 8.128) 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 8.255 +0.635 –0.381 ) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U W W 2V V– OFF IN 0 IN 1 V– V+ OUT V+ –2V V– Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP 0.400 (10.160) MAX 8 7 6 5 0.250 ± 0.010 (6.350 ± 0.254) 1 2 3 4 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.020 (0.508) MIN 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 0.018 ± 0.003 (0.457 ± 0.076) N8 0392 15 LT1203/LT1205 PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic SOIC 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157* (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) BSC SO8 0294 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). S Package 16-Lead Plastic SOIC 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157* (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0° – 8° TYP 0.053 – 0.069 (1.346 – 1.752) 2 3 4 5 6 7 8 0.004 – 0.010 (0.101 – 0.254) 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) TYP SO16 0893 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 LT/GP 0494 10K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1994