LTC2473CDDPBF

FEATURES n n n n n n n n n n n n n LTC2471/LTC2473 Selectable 250sps/1ksps, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference DESCRIPTION The LTC®2471/LTC2473 are small, 16-bit analog-to-digital converters with an integrated precision reference and a selectable 250sps or 1ksps output rate. They use a single 2.7V to 5.5V supply and communicate through an I2C Interface. The LTC2471 is single-ended with a 0V to VREF input range and the LTC2473 is differential with a ±VREF input range. Both ADC’s include a 1.25V integrated reference with 2ppm/°C drift performance and 0.1% initial accuracy. The converters are available in a 12-pin DFN 3mm × 3mm package or an MSOP-12 package. They include an integrated oscillator and perform conversions with no latency for multiplexed applications. The LTC2471/LTC2473 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters. Following a single conversion, the LTC2471/LTC2473 automatically power down the converter and can also be configured to power down the reference. When both the ADC and reference are powered down, the supply current is reduced to 200nA. The LTC2471/LTC2473 include a user selectable 250sps or 1ksps output rate and due to a large oversampling ratio (8,192 at 250sps and 2,048 at 1ksps) have relaxed anti-aliasing requirements. 16-Bit Resolution, No Missing Codes Internal, High Accuracy Reference—10ppm/°C (Max) Single-Ended (LTC2471) or Differential (LTC2473) Selectable 250sps/1ksps Output Rate 1mV Offset Error 0.01% Gain Error Single Conversion Settling Time Simplifies Multiplexed Applications Single-Cycle Operation with Auto Shutdown 3.5mA (Typ) Supply Current 2μA (Max) Sleep Current Internal Oscillator—No External Components Required I2C Interface Small 12-Lead, 3mm × 3mm DFN and MSOP Packages APPLICATIONS n n n n n n n System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378. TYPICAL APPLICATION 2.7V TO 5.5V REFERENCE OUTPUT VOLTAGE (V) 1.2520 1.2515 1.2510 1.2505 1.2500 1.2495 1.2490 1.2485 1.2480 –50 0.1μF 0.1μF IN+ LTC2473 IN– 10k 0.1μF R REF– AO GND 24713 TA01a VREF vs Temperature 0.1μF REFOUT COMP VCC SCL SDA 0.1μF 10μF 10k 10k I2C INTERFACE –30 –10 10 30 50 TEMPERATURE (°C) 70 90 24713 TA01b 24713f 1 LTC2471/LTC2473 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (VIN+, VIN –, VIN, VREF –, VCOMP, VREFOUT) ...........................–0.3V to (VCC + 0.3V) Digital Voltage (VSDA, VSCL, VAO)..........................–0.3V to (VCC + 0.3V) Storage Temperature Range .................. –65°C to 150°C Operating Temperature Range LTC2471C/LTC2473C ............................... 0°C to 70°C LTC2471I/LTC2473I..............................–40°C to 85°C PIN CONFIGURATION LTC2473 TOP VIEW REFOUT COMP AO GND SCL SDA 1 2 3 4 5 6 13 GND 12 VCC 11 GND 10 IN– 9 IN+ 8 REF– 7 GND REFOUT COMP AO GND SCL SDA 1 2 3 4 5 6 TOP VIEW 12 11 10 9 8 7 VCC GND IN– IN+ REF– GND LTC2473 DD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION LTC2471 TOP VIEW REFOUT COMP AO GND SCL SDA 1 2 3 4 5 6 13 GND 12 VCC 11 GND 10 GND 9 IN 8 REF– 7 GND LTC2471 MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 130°C/W TOP VIEW REFOUT COMP AO GND SCL SDA 1 2 3 4 5 6 12 11 10 9 8 7 VCC GND GND IN REF– GND DD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 130°C/W ORDER INFORMATION LEAD FREE FINISH LTC2471CDD#PBF LTC2471IDD#PBF LTC2471CMS#PBF LTC2471IMS#PBF LTC2473CDD#PBF LTC2473IDD#PBF LTC2473CMS#PBF LTC2473IMS#PBF TAPE AND REEL LTC2471CDD#TRPBF LTC2471IDD#TRPBF LTC2471CMS#TRPBF LTC2471IMS#TRPBF LTC2473CDD#TRPBF LTC2473IDD#TRPBF LTC2473CMS#TRPBF LTC2473IMS#TRPBF PART MARKING* LFPW LFPW 2471 2471 LFPX LFPX 2473 2473 PACKAGE DESCRIPTION 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic MSOP-12 12-Lead Plastic MSOP-12 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic MSOP-12 12-Lead Plastic MSOP-12 TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 24713f 2 LTC2471/LTC2473 ELECTRICAL CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Transition Noise Power Supply Rejection DC l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) CONDITIONS (Note 3) Output Rate 250sps (Note 4) Output Rate 1000sps (Note 4) l l l l MIN 16 TYP 2 8 ±1 0.05 ±0.01 0.15 3 80 MAX 8.5 12 ±2.5 ±0.25 UNITS Bits LSB LSB mV LSB/°C % of FS LSB/°C μVRMS dB ANALOG INPUTS specifications are at TA = 25°C. PARAMETER SYMBOL VIN+ VIN VIN VOR+, VUR+ VOR–, VUR– CIN IDC_LEAK(IN+, IN–, IN) ICONV VREF – The l denotes the specifications which apply over the full operating temperature range, otherwise CONDITIONS LTC2473 LTC2473 LTC2471 VIN– = 0.625V VIN+ = 0.625V VIN = GND (Note 8) VIN = VCC (Note 8) l l l l l l MIN 0 0 0 TYP MAX VREF VREF VREF UNITS V V V LSB LSB pF Positive Input Voltage Range Negative Input Voltage Range Input Voltage Range Overrange/Underrange Voltage, IN+ Overrange/Underrange Voltage, IN– IN+, IN–, IN Sampling Capacitance IN+, IN– DC Leakage Current (LTC2473) IN DC Leakage Current (LTC2471) Input Sampling Current (Notes 5, 8) Reference Output Voltage Reference Voltage Coefficient 8 8 0.35 –10 –10 1.247 ±1 ±1 50 1.25 ±2 ±5 –90 l l 10 10 1.253 ±10 nA nA nA V ppm/°C ppm/°C dB mA μA mV/mA nV/√Hz (Note 9) C-Grade I-Grade 2.7V ≤ VCC ≤ 5.5V VCC = 5.5, Forcing Output to GND (Note 8) VCC = 5.5, Forcing Output to GND (Note 8) 2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing , , CCOMP= 0.1μF CREFOUT = 0.1μF At f = 1ksps l Reference Line Regulation Reference Short Circuit Current COMP Pin Short Circuit Current Reference Load Regulation Reference Output Noise Density 35 200 3.5 30 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Conversion Nap Sleep LTC2473 (Note 8) LTC2471 (Note 8) (Note 8) (Note 8) CONDITIONS l l l l l POWER REQUIREMENTS MIN 2.7 TYP MAX 5.5 UNITS V mA mA μA μA 3.5 2.5 800 0.2 5 4 1500 2 24713f 3 LTC2471/LTC2473 I2C INPUTS AND OUTPUTS SYMBOL VIH VIL II VHYS VOL IIN CI CB VIH(A0) VIL(A0) PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Hysteresis of Schmidt Trigger Inputs Low Level Output Voltage (SDA) Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line High Level Input Voltage for Address Pin Low Level Input Voltage for Address Pin (Note 8) (Note 3) I = 3mA 0.1VCC ≤ VIN ≤ 0.9VCC The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) CONDITIONS l l l l l l l l l l MIN 0.7VCC TYP MAX 0.3VCC UNITS V V μA V V μA pF pF V V –10 0.05VCC 10 0.4 1 10 400 0.95VCC 0.05VCC I2C TIMING CHARACTERISTICS SYMBOL tCONV1 tCONV2 fSCL tHD(SDA,STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF tOF tSP PARAMETER Conversion Time Conversion Time SCL Clock Frequency Hold Time (Repeated) START Condition LOW Period of the SCL Pin HIGH Period of the SCL Pin Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Rise Time for SDA, SCL Signals Fall Time for SDA, SCL Signals Set-Up Time for STOP Condition Bus Free Time Between a Stop and Start Condition Output Fall Time VIHMIN to VILMAX Input Spike Suppression The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) CONDITIONS SPD = 0 SPD = 1 l l l l l l l l l l l l l MIN 3.2 0.8 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 20 + 0.1CB TYP 4 1 MAX 4.8 1.2 400 UNITS ms ms kHz μs μs μs μs 0.9 300 300 μs ns ns ns μs μs (Note 6) (Note 6) Bus Load CB = 10pF to 400pF (Note 6) l l 250 50 ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = VREF, –VREF ≤ VIN ≤ VREF VIN = VIN+ – VIN –, VINCM = ( VIN+ + VIN –)/2. (LTC2473) Note 3. Guaranteed by design, not subject to test. Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Note 5: Input sampling current is the average input current drawn from the input sampling network while the LTC2471/LTC2473 are converting. Note 6: CB = capacitance of one bus line in pF. Note 7: All values refer to VIH(MIN) and VIL(MAX) levels. Note 8: A positive current is flowing into the DUT pin. Note 9: Voltage temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 24713f 4 LTC2471/LTC2473 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity 3 VCC = 2.7V TA = –45°C, 25°C, 90°C 2 OUTPUT RATE = 250sps 3 2 1 INL (LSB) INL (LSB) 0 –1 –2 VCC = 5.5V TA = –45°C, 25°C, 90°C OUTPUT RATE = 250sps –3 0.25 0.75 –1.25 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) (TA = 25°C, unless otherwise noted) Integral Nonlinearity 6 4 Maximum INL vs Temperature OUTPUT RATE = 250sps VCC = 5.5V 1 INL (LSB) 0 –1 –2 –3 –1.25 2 VCC = 4.1V 0 –2 –4 –6 –50 VCC = 2.7V 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 1.25 1.25 –30 30 50 –10 10 TEMPERATURE (°C) 70 90 24713 G01 24713 G02 24713 G03 Offset Error vs Temperature 35 30 ADC GAIN ERROR (LSB) VCC = 5.5V OFFSET ERROR (LSB) 25 20 15 10 VCC = 2.7V 5 0 –50 VCC = 4.1V 50 40 ADC Gain Error vs Temperature 10 9 TRANSITION NOISE RMS (μV) 8 7 6 5 4 3 2 1 70 90 24713 G05 Transition Noise vs Temperature VCC = 5.5V 30 20 10 0 VCC = 4.1V VCC = 5.5V VCC = 2.7V VCC = 2.7V –10 10 30 50 TEMPERATURE (°C) –30 50 –10 10 30 TEMPERATURE (°C) 70 90 –10 –50 –30 0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 24713 G04 24713 G06 Conversion Mode Power Supply Current vs Temperature 4.0 3.9 CONVERSION CURRENT (mA) 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 50 VCC = 2.7V VCC = 5.5V SLEEP CURRENT (nA) 350 300 250 200 150 100 Sleep Mode Power Supply Current vs Temperature 1.2508 REFERENCE OUTPUT VOLTAGE (V) 1.2507 1.2506 1.2505 1.2504 1.2503 VREF vs Temperature VCC = 5.5V VCC = 4.1V VCC = 4.1V VCC = 2.7V –30 50 –10 10 30 TEMPERATURE (°C) 70 90 0 –50 1.2502 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 24713 G07 24713 G08 24713 G09 24713f 5 LTC2471/LTC2473 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Rejection vs Frequency Applied to VCC 0 –20 CONVERSION TIME (ms) REJECTION (dB) –40 –60 –80 –100 –120 4.4 TA = 25°C 4.3 4.2 4.1 4.0 3.9 3.8 –50 VCC = 5.5V VCC = 4.1V VCC = 2.7V (TA = 25°C, unless otherwise noted) Conversion Time vs Temperature 1.250345 1.250340 1.250335 VREF (V) 1.250330 1.250325 1.250320 1.250315 1.250310 –25 25 50 0 TEMPERATURE (°C) 75 100 24713 G11 VREF vs VCC TA = 25°C 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 10M 1.250305 2.0 2.5 3.0 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0 24713 G010 24713 G12 PIN FUNCTIONS REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V, this voltage sets the full-scale input range of the ADC. For noise and reference stability connect to a 0.1μF capacitor tied to GND. This capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (COMP). REFOUT must not be overdriven by an external reference. COMP (Pin 2): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1μF capacitor to GND. A0 (Pin 3): Chip Address Control Pin. The A0 pin can be tied to GND or VCC. If A0 is tied to GND, the LTC2471/ LTC2473 I2C address is 0010100. If A0 is tied to VCC, the LTC2471/LTC2473 I2C address is 1010100. GND (Pins 4, 7, 11, (Exposed Pad Pin 13 – DFN Package Only)): Ground. Connect exposed pad directly to the ground plane through a low impedance connection. SCL (Pin 5): Serial Clock Input of the I2C Interface. The LTC2471/LTC2473 can only act as an I2C slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of SCL and output through the SDA pin on the falling edges of SCL. SDA (Pin 6): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin. The pin is high impedance unless the LTC2471/LTC2473 is in the data output mode. While the LTC2471/LTC2473 is in the data output mode, SDA is an open drain pull down (which requires an external 1.7k pull-up resistor to VCC). REF– (Pin 8): Negative Reference Input to the ADC. The voltage on this pin sets the zero input to the ADC. This pin should tie directly to ground or the ground sense of the input sensor. IN+ (LTC2473), IN (LTC2471) (Pin 9): Positive input voltage for the LTC2473 differential device. ADC input for the LTC2471 single-ended device. IN– (LTC2473), GND (LTC2471) (Pin 10): Negative input voltage for the LTC2473 differential device. GND for the LTC2471 single-ended device. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to pin 12 as possible. 24713f 6 LTC2471/LTC2473 BLOCK DIAGRAM 1 REFOUT 2 COMP 12 VCC AO SPI INTERFACE SCL SDA 3 5 6 9 IN+ (IN) ΔΣ A/D CONVERTER INTERNAL REFERENCE – 10 IN– (GND) ΔΣ A/D CONVERTER DECIMATING SINC FILTER INTERNAL OSCILLATOR REF– 4, 7, 11, 13 DD PACKAGE 4, 7, 11 MS PACKAGE GND 24713 BD 8 ( ) PARENTHESIS INDICATE LTC2471 Figure 1. Functional Block Diagram APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2471/LTC2473 are low power, delta sigma, analog to digital converters with a simple I2C interface and a user selected 250sps/1ksps output rate (see Figure 1). The LTC2473 has a fully differential input while the LTC2471 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct states: CONVERT, SLEEP/NAP and DATA INPUT/OUTPUT. The operation , begins with the CONVERT state (see Figure 2). Once the conversion is finished, the converter automatically powers down (NAP) or under user control, both the converter and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read or an abort is initiated, the device begins a new conversion. The CONVERT state duration is determined by the LTC2471/LTC2473 conversion time (nominally 4ms or 1ms depending on the selected output rate). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. POWER-ON RESET CONVERT SLEEP/NAP NO READ/WRITE ACKNOWLEDGE YES DATA INPUT/OUTPUT NO STOP OR READ 16 BITS YES 24713 F02 Figure 2. LTC2471/LTC2473 State Transition Diagram 24713f 7 LTC2471/LTC2473 APPLICATIONS INFORMATION After the completion of a conversion, the LTC2471/LTC2473 enters the SLEEP/NAP state and remains there until a valid read/write is acknowledged. Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state. While in the SLEEP/NAP state, the LTC2471/LTC2473’s converters are powered down. This reduces the supply current by approximately 70%. While in the NAP state the reference remains powered up. The user can power down both the reference and the converter by enabling the sleep mode during the DATA INPUT/OUTPUT state. Once the next conversion is complete with the sleep mode enabled, the SLEEP state is entered and power is reduced to 2μA (maximum). The reference is powered up once a valid read/write is acknowledged. The reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1μF). As the reference and compensation capacitors are decreased, the startup time is reduced (see Figure 3), but the transition noise increases (see Figure 4). Power-Up Sequence When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for 25 approximately 0.5ms. For proper operation VDD needs to be restored to normal operating range (2.7V to 5.5V) before the conclusion of the POR cycle. The POR signal clears all internal registers. Following the POR signal, the LTC2471/LTC2473 start a conversion cycle and follow the succession of states shown in Figure 2. The reference startup time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conversion following power-up will be invalid if the reference voltage has not completely settled (see Figure 3). The first conversion following power up can be discarded using the data abort command or simply read and ignored. Depending on the value chosen for CCOMP and CREFOUT, the reference startup can take more than one conversion period, see Figure 3. If the startup time is less than 1ms (1ksps output rate) or 4ms (250sps output rate) then conversions following the first period are accurate to the device specifications. If the startup time exceeds 1ms or 4ms then the user can wait the appropriate time or use the fixed conversion period as a startup timer by ignoring results within the unsettled period. Once the reference has settled, all subsequent conversion results are valid. If the user places the device into the sleep mode (SLP = 1, reference powered down) the reference will require a startup time proportional to the value of CCOMP and CREFOUT (see Figure 3). TRANSITION NOISE (μV RMS) 250 200 VCC = 2.7V 150 TIME (ms) 100 50 0 –50 1 0.1 0.01 CAPACITANCE (μF) 0.001 24713 F03 20 15 10 VCC = 4.1V 5 VCC = 5.5V 0 0.0001 0.001 0.01 0.1 CAPACITANCE (μF) 1 10 24713 F04 Figure 4. Transition Noise RMS vs COMP and Reference Capacitance Figure 3. Reference Start-Up Time vs VREF and Compensation Capacitance 24713f 8 LTC2471/LTC2473 APPLICATIONS INFORMATION Ease of Use The LTC2471/LTC2473 data output has no latency, filter settling delay, or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2471/LTC2473 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional deltasigma architectures. This allows external filter networks to interface directly to the LTC2471/LTC2473. Since the average input sampling current is 50nA, an external RC lowpass filter using 1kΩ and 0.1μF results in