LTC2463CDDPBF

FEATURES n n n n n n n n n n n n LTC2461/LTC2463 Ultra-Tiny, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference DESCRIPTION The LTC®2461/LTC2463 are ultra tiny, 16-Bit analog-todigital converters with an integrated precision reference. They use a single 2.7V to 5.5V supply and communicate through an I2C Interface. The LTC2461 is single-ended with a 0V to 1.25V input range and the LTC2463 is differential with a 1.25V input range. Both ADCs include a 1.25V integrated reference with 2ppm/°C drift performance and 0.1% initial accuracy. The converters are available in a 12-pin 3mm × 3mm DFN package or an MSOP-12 package. They include an integrated oscillator and perform conversions with no latency for multiplexed applications. The LTC2461/LTC2463 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters. Following a single conversion, the LTC2461/LTC2463 automatically power down the converter and can also be configured to power down the reference. When both the ADC and reference are powered down, the supply current is reduced to 200nA. The LTC2461/LTC2463 can sample at 60 conversions per second and, due to the very large oversampling ratio, have extremely relaxed antialiasing requirements. Both include continuous internal offset and fullscale calibration algorithms which are transparent to the user, ensuring accuracy over time and the operating temperature range. 16-Bit Resolution, No Missing Codes Internal Reference, High Accuracy 10ppm/°C (Max) Single-Ended (LTC2461) or Differential (LTC2463) 2LSB Offset Error (Typ) 0.01% Gain Error (Typ) 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications 1.5mA Supply Current 200nA Sleep Current Internal Oscillator—No External Components Required 2-Wire I2C Interface with Two Addresses Plus One Global Address for Synchronization Ultra-Tiny, 12-Lead, 3mm × 3mm DFN and MSOP Packages APPLICATIONS n n n n n n System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Data Acquisition Embedded ADC Upgrades L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378. TYPICAL APPLICATION 2.7V TO 5.5V VREF vs Temperature 1.2520 REFERENCE OUTPUT VOLTAGE (V) 1.2515 1.2510 1.2505 1.2500 1.2495 1.2490 1.2485 1.2480 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 0.1μF 0.1μF IN+ REFOUT 0.1μF COMP VCC SCL LTC2463 IN– SDA REF– A0 GND 0.1μF 10μF 10k 10k I 2C INTERFACE 10k 0.1μF R 24613 TA01a 24613 TA01b 24613f 1 LTC2461/LTC2463 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (VIN+, VIN –, VIN, VREF –, VCOMP, VREFOUT) ...........................–0.3V to (VCC + 0.3V) Digital Voltage (VSDA, VSCL, VA0) ..........................–0.3V to (VCC + 0.3V) Storage Temperature Range .................. –65°C to 150°C Operating Temperature Range LTC2461C/LTC2463C ............................... 0°C to 70°C LTC2461I/LTC2463I .............................–40°C to 85°C PIN CONFIGURATION LTC2463 TOP VIEW REFOUT COMP A0 GND SCL SDA 1 2 3 4 5 6 13 12 VCC 11 GND 10 IN– 9 IN+ 8 REF– 7 GND REFOUT COMP A0 GND SCL SDA 1 2 3 4 5 6 TOP VIEW 12 11 10 9 8 7 VCC GND IN– IN+ REF– GND LTC2463 DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) LTC2461 TOP VIEW REFOUT COMP A0 GND SCL SDA 1 2 3 4 5 6 13 12 VCC 11 GND 10 GND 9 IN 8 REF– 7 GND LTC2461 MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 135°C/W TOP VIEW REFOUT COMP A0 GND SCL SDA 1 2 3 4 5 6 12 11 10 9 8 7 VCC GND GND IN REF– GND DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 135°C/W ORDER INFORMATION LEAD FREE FINISH LTC2461CDD#PBF LTC2461IDD#PBF LTC2461CMS#PBF LTC2461IMS#PBF LTC2463CDD#PBF LTC2463IDD#PBF LTC2463CMS#PBF LTC2463IMS#PBF TAPE AND REEL LTC2461CDD#TRPBF LTC2461IDD#TRPBF LTC2461CMS#TRPBF LTC2461IMS#TRPBF LTC2463CDD#TRPBF LTC2463IDD#TRPBF LTC2463CMS#TRPBF LTC2463IMS#TRPBF PART MARKING* LFGF LFGF 2461 2461 LFGG LFGG 2463 2463 PACKAGE DESCRIPTION 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic MSOP 12-Lead Plastic MSOP 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic MSOP 12-Lead Plastic MSOP TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 24613f 2 LTC2461/LTC2463 ELECTRICAL CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Includes Contributions of ADC and Internal Reference Includes Contributions of ADC and Internal Reference C-Grade I-Grade l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) CONDITIONS (Note 3) (Note 4) LTC2461, 30Hz, LTC2463 LTC2461, 60Hz l l l MIN 16 TYP 1 2 5 0.02 ±0.01 ±2 ±5 2.2 80 MAX 8 15 UNITS Bits LSB LSB LSB LSB/°C % of FS ppm/°C ppm/°C μVRMS dB ±0.25 ±10 Transition Noise Power Supply Rejection DC ANALOG INPUTS specifications are at TA = 25°C. PARAMETER + The l denotes the specifications which apply over the full operating temperature range, otherwise CONDITIONS LTC2463 LTC2463 LTC2461 VIN – = 0.625V (See Figure 3) SYMBOL VIN VIN VOR+, VUR+ VOR–, VUR– CIN VIN– MIN l l l TYP MAX VREF VREF VREF UNITS V V V LSB LSB pF Positive Input Voltage Range Negative Input Voltage Range Input Voltage Range Overrange/Underrange Voltage, IN+ Overrange/Underrange Voltage, IN– IN+, IN–, IN Sampling Capacitance 0 0 0 8 8 0.35 VIN+ = 0.625V (See Figure 3) VIN = GND or VCC (Note 8) VIN = GND or VCC (Note 8) l l l l IDC_LEAK(IN+, IN–, IN) IN+, IN– DC Leakage Current (LTC2463) IN DC Leakage Current (LTC2461) ICONV VREF Input Sampling Current (Note 5) REFOUT Output Voltage –10 –10 1.247 1 1 50 1.25 ±2 ±5 –90 10 10 1.253 ±10 nA nA nA V ppm/°C ppm/°C dB mA μA mV/mA nV/√Hz REFOUT Voltage Temperature Coefficient (Note 9) C-Grade I-Grade Reference Line Regulation Reference Short Circuit Current COMP Pin Short Circuit Current Reference Load Regulation Reference Output Noise Density 2.7V ≤ VCC ≤ 5.5V VCC = 5.5, Forcing REFOUT to GND VCC = 5.5, Forcing REFOUT to GND 2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing , , CCOMP= 0.1μF CREFOUT = 0.1μF At f = 1kHz l l 35 200 3.5 30 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Nap Sleep CONDITIONS l l l l POWER REQUIREMENTS MIN 2.7 TYP MAX 5.5 UNITS V mA μA μA 1.5 800 0.2 2.5 1500 2 24613f 3 LTC2461/LTC2463 I2C INPUTS AND OUTPUTS SYMBOL VIH VIL II VHYS VOL IIN CI CB VIH(A0) VIL(A0) PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Hysteresis of Schmidt Trigger Inputs Low Level Output Voltage (SDA) Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line High Level Input Voltage for Address Pin Low Level Input Voltage for Address Pin (Note 3) I = 3mA 0.1VCC ≤ VIN ≤ 0.9VCC The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) CONDITIONS l l l l l l l l l l MIN 0.7VCC TYP MAX 0.3VCC UNITS V V μA V V μA pF pF V V –10 0.05VCC 10 0.4 1 10 400 0.95VCC 0.05VCC I2C TIMING CHARACTERISTICS SYMBOL tCONV fSCL tHD(SDA,STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF tOF tSP PARAMETER Conversion Time SCL Clock Frequency Hold Time (Repeated) START Condition LOW Period of the SCL Pin HIGH Period of the SCL Pin The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) CONDITIONS l l l l l l l l l l l l l l MIN 13 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 20 + 0.1CB TYP 16.6 MAX 23 400 UNITS ms kHz μs μs μs μs Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Rise Time for SDA, SCL Signals Fall Time for SDA, SCL Signals Set-Up Time for STOP Condition Bus Free Time Between a Stop and Start Condition Output Fall Time VIHMIN to VILMAX Input Spike Suppression Bus Load CB = 10pF to 400pF (Note 6) (Note 6) (Note 6) 0.9 300 300 μs ns ns ns μs μs 250 50 ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. Note 3: Guaranteed by design, not subject to test. Note 4: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Guaranteed by design and test correlation. Note 5: Input sampling current is the average input current drawn from the input sampling network while the LTC2461/LTC2463 are converting. Note 6: CB = capacitance of one bus line in pF . Note 7: All values refer to VIH(MIN) and VIL(MAX) levels. Note 8: A positive current is flowing into the DUT pin. Note 9: Voltage temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 24613f 4 LTC2461/LTC2463 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5.5V) 3 2 1 INL (LSB) INL (LSB) 0 –1 –2 –3 –1.25 TA = –45°C, 25°C, 90°C 3 2 1 0 –1 –2 –3 –1.25 INL (LSB) (TA = 25°C, unless otherwise noted) Integral Nonlinearity (VCC = 2.7V) TA = –45°C, 25°C, 90°C 3 2 1 0 –1 –2 INL vs Temperature VCC = 5.5V, 4.1V, 2.7V 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 1.25 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 1.25 –3 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 24613 G03 24613 G01 24613 G02 Offset Error vs Temperature 5 4 3 OFFSET ERROR (LSB) 2 1 0 –1 –2 –3 –4 –5 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 VCC = 2.7V VCC = 4.1V VCC = 5.5V ADC GAIN ERROR (LSB) 25 ADC Gain Error vs Temperature 10 VCC = 5.5V 20 TRANSITION NOISE RMS (μV) 9 8 7 6 5 4 3 2 1 75 100 24613 G05 Transition Noise vs Temperature 15 10 VCC = 4.1V VCC = 2.7V 5 VCC = 2.7V 0 –50 VCC = 5.5V –25 0 25 50 TEMPERATURE (°C) 0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 24613 G04 24613 G06 Conversion Mode Power Supply Current vs Temperature 2.0 1.9 CONVERSION CURRENT (mA) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 50 VCC = 2.7V SLEEP CURRENT (nA) VCC = 5.5V VCC = 4.1V 350 300 250 200 150 Sleep Mode Power Supply Current vs Temperature 1.2508 REFERENCE OUTPUT VOLTAGE (V) 1.2507 1.2506 1.2505 1.2504 1.2503 VREF vs Temperature VCC = 5V VCC = 5.5V VCC = 4.1V 100 VCC = 2.7V –30 50 –10 10 30 TEMPERATURE (°C) 70 90 0 –50 1.2502 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 24613 G07 24613 G08 24613 G09 24613f 5 LTC2461/LTC2463 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Rejection vs Frequency at VCC 0 –20 CONVERSION TIME (ms) REJECTION (dB) –40 –60 –80 TA = 25°C VCC = 4.1V 21 20 19 18 17 16 15 14 –50 VREF (V) VCC = 5V, 4.1V, 3V (TA = 25°C, unless otherwise noted) Conversion Time vs Temperature 1.24892 1.24891 1.24890 1.24889 1.24888 1.24887 1.24886 1.24885 –25 25 50 0 TEMPERATURE (°C) 75 100 24613 G11 VREF vs VCC TA = 25°C –100 –120 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 10M 1.24884 2.0 2.5 3.0 3.5 24613 G10 4.0 4.5 VCC (V) 5.0 5.5 6.0 24613 G12 24613f 6 LTC2461/LTC2463 PIN FUNCTIONS REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V, this voltage sets the fullscale input range of the ADC. For noise and reference stability connect to a 0.1μF capacitor tied to GND. This capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (COMP). REFOUT cannot be overdriven by an external reference. For applications that require an input range greater than 0V to 1.25V, please refer to the LTC2451/ LTC2453. COMP (Pin 2): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1μF capacitor to GND. A0 (Pin 3): Chip Address Control Pin. The A0 pin can be tied to GND or VCC. If A0 is tied to GND, the LTC2461/ LTC2463 I2C address is 0010100. If A0 is tied to VCC, the LTC2461/LTC2463 I2C address is 1010100. GND (Pins 4, 7, 11): Ground. Connect directly to the ground plane through a low impedance connection. Interface. The SCL (Pin 5): Serial Clock Input of the LTC2461/LTC2463 can only act as a slave and the SCL pin only accepts external serial clock. Data is shifted into the SDA pin on the rising edges of SCL and output through the SDA pin on the falling edges of SCL. I2C SDA (Pin 6): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin. The pin is high impedance unless the LTC2461/LTC2463 is in the data output mode. While the LTC2461/LTC2463 is in the data output mode, SDA is an open drain pull down (which requires an external 1.7k pull-up resistor to VCC). REF– (Pin 8): Negative Reference Input to the ADC. The voltage on this pin sets the zero input to the ADC. This pin should tie directly to ground or the ground sense of the input sensor. IN+ (LTC2463), IN (LTC2461) (Pin 9): Positive input voltage for the LTC2463 differential device. ADC input for the LTC2461 single-ended device. IN– (LTC2463), GND (LTC2461) (Pin 10): Negative input voltage for the LTC2463 differential device. GND for the LTC2461 single-ended device. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to pin 12 as possible. Exposed Pad (Pin 13 – DFN Package): Ground. Connect directly to the ground plane through a low impedance connection. 24613f 7 LTC2461/LTC2463 BLOCK DIAGRAM 1 REFOUT 2 COMP 12 VCC 3 5 6 9 IN+ (IN) A/D CONVERTER INTERNAL REFERENCE I2C INTERFACE A0 SCL SDA – 10 IN– (GND) A/D CONVERTER DECIMATING SINC FILTER INTERNAL OSCILLATOR REF– 4, 7, 11, 13 (DD PACKAGE) GND 24613 BD 8 ( ) PARENTHESIS INDICATE LTC2461 Figure 1. Functional Block Diagram APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2461/LTC2463 are low power, delta sigma, analog to digital converters with a simple I2C interface (see Figure 1). The LTC2463 has a fully differential input while the LTC2461 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct states: CONVERT, SLEEP/NAP and DATA INPUT/OUTPUT , (see Figure 2). The operation begins with the CONVERT state. Once the conversion is finished, the converter automatically powers down (NAP) or, under user control, both the converter and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read the device begins a new conversion. The CONVERT state duration is determined by the LTC2461/ LTC2463 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. After the completion of a conversion, the LTC2461/LTC2463 enters the SLEEP/NAP state and remains there until a valid POWER-ON RESET CONVERT SLEEP/NAP NO READ/WRITE ACKNOWLEDGE YES DATA INPUT/OUTPUT NO STOP OR READ 16 BITS YES 24613 F02 Figure 2. LTC2461/LTC2463 State Transition Diagram read/write is acknowledged. Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state. While in the SLEEP/NAP state, the LTC2461/LTC2463’s converters are powered down. This reduces the supply 24613f 8 LTC2461/LTC2463 APPLICATIONS INFORMATION current by approximately 50%. While in the Nap state, the reference remains powered up. To power down the reference in addition to the converter, the user can select the SLEEP mode during the DATA INPUT/OUTPUT state. Once the next conversion is complete, SLEEP state is entered and power is reduced to 200nA. The reference is powered up once a valid read/write is acknowledged. The reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1μF). Power-Up Sequence When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2461/LTC2463 start a conversion cycle and follow the succession of states shown in Figure 2. The reference startup time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conversion following power-up will be invalid since the reference voltage has not completely settled. The first conversion following power up can be discarded using the data abort command or simply read and ignored. The following conversions are accurate to the device specifications. Ease of Use The LTC2461/LTC2463 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2461/LTC2463 perform offset calibrations every conversion cycle. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature. The LTC2461/LTC2463 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional deltasigma architectures. This allows external filter networks to interface directly to the LTC2461/LTC2463. Since the average input sampling current is 50nA, an external RC lowpass filter using 1kΩ and 0.1μF results in