LTC2605IGN

LTC2605/LTC2615/LTC2625 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTIO The LTC®2605/LTC2615/LTC2625 are octal 16-, 14and 12-bit, 2.7V to 5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP packages. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in single-supply, voltage-output multiples. The parts use the 2-wire I2C compatible serial interface. The LTC2605/LTC2615/LTC2625 operate in both the standard mode (maximum clock rate of 100kHz) and the fast mode (maximum clock rate of 400kHz). The LTC2605/LTC2615/LTC2625 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. The power-on reset circuit resets the LTC2605-1/ LTC2615-1/LTC2625-1 to midscale. The voltage output stays at midscale until a valid write and update takes place. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Smallest Pin-Compatible Octal DACs: LTC2605: 16 Bits LTC2615: 14 Bits LTC2625: 12 Bits Guaranteed Monotonic Over Temperature 400kHz I2C Interface Wide 2.7V to 5.5V Supply Range Low Power Operation: 250µA per DAC at 3V Individual Channel Power-Down to 1µA, Max Ultralow Crosstalk Between DACs (1GΩ) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the updated command, the power-up delay is 5µs. If, on the other hand, all eight DACs are powered down, then the bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12µs for VCC = 5V, 30µs for VCC = 3V. Voltage Outputs Each of the eight rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. 2605f LTC2605/LTC2615/LTC2625 OPERATIO DC output impedance is equivalent to load regulation and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifier’s DC output impedance is 0.020Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30Ω • 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance to just 0.005Ω. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. U Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.020Ω), and will degrade DC crosstalk. Note that the LTC2605/LTC2615/LTC2625 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 4b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 4c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 2605f 13 LTC2605/LTC2615/LTC2625 SLAVE ADDRESS COMMAND MS DATA A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 SA0 WR C3 C2 C1 C0 A3 LS DATA D5 D4 D3 D2 D1 D0 STOP SA6 SA5 SA4 SA3 SA2 SA1 START SA0 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 ACK ACK ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK SDA SA6 SA5 SA4 SA3 SA2 SA1 SCL 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE VOUT Figure 3. Typical LTC2605 Input Waveform—Programming DAC Output for Full Scale 2605/15/25 O02 U OPERATIO 14 2605f LTC2605/LTC2615/LTC2625 OPERATIO U VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) 65, 535 INPUT CODE (b) 2605/15/25 O05 0V NEGATIVE OFFSET Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full Scale PACKAGE DESCRIPTIO .254 MIN .0165 .0015 RECOMMENDED SOLDER PAD LAYOUT .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0250 TYP 1 .015 .004 × 45° (0.38 0.10) 0 – 8 TYP .053 – .068 (1.351 – 1.727) 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC GN16 (SSOP) 0502 2605f 15 LTC2605/LTC2615/LTC2625 TYPICAL APPLICATIO ADDRESS SELECTION VCC VCC VCC Demonstration Circuit—LTC2428 20-Bit ADC Measures Key Performance Parameters VREF C1 0.1µF C2 0.1µF VCC VOUT A VOUT B VOUT C VOUT D VOUT E 10k I2C BUS 10k 9 8 SDA SCL GND 1 U2 LTC2605CGN VOUT F VOUT G VOUT H 16 2 3 4 5 12 13 14 15 TP3 DAC A TP4 DAC B TP5 DAC C TP6 DAC D DAC OUTPUTS TP7 DAC E TP8 DAC F TP9 DAC G TP10 DAC H VIN 2 U4 LT1236ACS8-5 VIN GND C6 0.1µF 4 VOUT 6 1 5V 4.096V 2 3 JP2 VREF C7 4.7µF 6.3V TP11 VREF VREF 9 10 11 12 13 14 6 1 5VREF C8 REGULATOR 1µF 16V 2 3 JP3 VCC 5V TP12 VCC TP13 GND 5 ZSSET FO GND GND GND GND GND GND GND 6 16 18 22 27 28 VCC 15 17 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 26 R7 7.5k 2605 TA01 VCC U5 LT1461ACS8-4 2 3 C9 0.1µF VIN SHDN GND 4 VOUT RELATED PARTS PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 LTC2600/LTC2610/ LTC2620 LTC2601/LTC2611/ LTC2621 LTC2602/LTC2612/ LTC2622 LTC2604/LTC2614/ LTC2624 LTC2606/LTC2616/ LTC2626 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10-/8-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs with I2C Interface in 10-Lead DFN COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2µs for 10V Step 250µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail Output, SPI Interface 300µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail Output, SPI Interface 300µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail Output, SPI Interface 250µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail Output, SPI Interface 270µA per DAC, 2.7V–5.5V Supply Range, Rail-to-Rail Output, I2C Interface 2605f LT/LWI/TP 0405 500 • PRINTED IN THE USA 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U VCC 6 REF 11 10 7 CA0 CA1 CA2 VREF VCC VCC R5 7.5k C10 100pF 7 MUXOUT 4 ADCIN 3 FSSET R8 22 2 8 C4 0.1µF C5 0.1µF JP1 ON/OFF DISABLE ADC 3 2 1 VCC VCC CSADC CSMUX 4-/8-CHANNEL MUX SCK CLK DIN SD0 23 20 25 19 21 24 SCK SPI BUS R6 7.5k CS + 20-BIT ADC – 1 U3 LTC2428CG www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005