LTC2605IGN#PBF

LTC2605/LTC2615/LTC2625 Octal 16-/14-/12-Bit Rail-to Rail DACs in 16-Lead SSOP FEATURES DESCRIPTION n The LTC®2605/LTC2615/LTC2625 are octal 16-, 14- and 12-bit, 2.7V to 5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP packages. They have built-in high performance output buffers and are guaranteed monotonic. n n n n n n n n n n n n Smallest Pin-Compatible Octal DACs: LTC2605: 16 Bits LTC2615: 14 Bits LTC2625: 12 Bits Guaranteed Monotonic Over Temperature 400kHz I2C Interface Wide 2.7V to 5.5V Supply Range Low Power Operation: 250μA per DAC at 3V Individual Channel Power-Down to 1μA (Max) Ultralow Crosstalk Between DACs (1GΩ) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the updated command, the power-up delay is 5μs. If, on the other hand, all eight DACs are powered down, then the bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12μs for VCC = 5V, 30μs for VCC = 3V. 2605fa 13 14 2 1 SCL 3 SA4 4 SA3 SA3 5 SA2 SA2 6 SA1 SA1 SLAVE ADDRESS SA4 7 SA0 SA0 8 WR 1 C3 2 C2 C2 3 C1 C1 4 C0 C0 5 A3 A3 COMMAND 6 A2 A2 7 A1 A1 8 A0 A0 9 ACK 1 D15 2 D14 3 D13 4 5 D11 MS DATA D12 6 D10 7 D9 8 D8 9 ACK 1 D7 2 D6 3 D5 Figure 3. Typical LTC2605 Input Waveform—Programming DAC Output for Full-Scale 9 ACK C3 4 5 D3 LS DATA D4 6 D2 7 D1 8 D0 9 ACK 2605 F03 ZERO-SCALE VOLTAGE FULL-SCALE VOLTAGE STOP OPERATION VOUT SA5 SA6 SA5 SDA START SA6 LTC2605/LTC2615/LTC2625 2605fa LTC2605/LTC2615/LTC2625 OPERATION Voltage Outputs Each of the eight rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifier’s DC output impedance is 0.020Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30Ω • 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC-crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance to just 0.005Ω. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.020Ω), and will degrade DC crosstalk. Note that the LTC2605/LTC2615/LTC2625 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 4b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 4c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. 2605fa 15 LTC2605/LTC2615/LTC2625 OPERATION VREF = VCC VREF = VCC POSITIVE FSE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (4c) 2605 F04 OUTPUT VOLTAGE 0 0V NEGATIVE OFFSET 32, 768 INPUT CODE (4a) 65, 535 INPUT CODE (4b) Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (4a) Overall Transfer Function, (4b) Effect of Negative Offset for Codes Near Zero-Scale, (4c) Effect of Positive Full-Scale Error for Codes Near Full-Scale PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 p.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 p.0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 p .004 s 45o (0.38 p 0.10) .007 – .0098 (0.178 – 0.249) .0532 – .0688 (1.35 – 1.75) 2 3 4 5 6 7 8 .004 – .0098 (0.102 – 0.249) 0o – 8o TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2605fa 16 LTC2605/LTC2615/LTC2625 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 11/09 Added Text to Serial Digital Interface Section 11 2605fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 17 LTC2605/LTC2615/LTC2625 TYPICAL APPLICATION Demonstration Circuit—LTC2428 20-Bit ADC Measures Key Performance Parameters ADDRESS SELECTION VCC VCC VCC VREF VCC C1 0.1μF C2 0.1μF 6 REF 11 10 7 VCC CA0 VOUT A CA1 VOUT B VOUT C CA2 VOUT D VCC VOUT E 10k 10k VOUT F 9 I2C BUS 8 SDA VOUT G SCL VOUT H 16 2 3 4 5 12 13 14 15 GND 1 U2 LTC2605CGN TP3 DAC A TP4 DAC B TP5 DAC C TP6 DAC D DAC OUTPUTS TP7 DAC E VREF TP8 DAC F TP10 DAC H 2 VIN VOUT 6 1 5V 4.096V 4 2 3 JP2 VREF TP11 VREF C7 4.7μF 6.3V U5 LT146 1ACS8-4 2 3 C9 0.1μF VOUT VIN SHDN GND 4 7 4 MUXOUT ADCIN JP1 ON/OFF 3 2 3 2 8 DISABLE ADC 1 VCC VCC FSSET VREF GND C6 0.1μF C5 0.1μF R8 22 C10 100pF U4 LT1236ACS8-5 VCC C4 0.1μF R5 7.5k TP9 DAC G VIN VCC 6 VCC 9 CH0 10 CH1 CSADC 23 11 CH2 CSMUX 20 12 CH3 13 CH4 14 CH5 15 CH6 17 CH7 5 ZSSET 4-/8-CHANNEL MUX + 20-BIT ADC SCK – DIN CLK SD0 1 5VREF C8 REGULATOR 1μF 16V TP12 VCC 2 3 JP3 TP13 GND VCC FO GND GND GND GND GND GND GND 1 U3 LTC2428CG 6 16 18 22 27 28 R6 7.5k CS 25 19 SCK 21 SPI BUS 24 26 R7 7.5k 2605 TA01 5V RELATED PARTS PART NUMBER DESCRIPTION LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 LTC2600/LTC2610/ LTC2620 LTC2601/LTC2611/ LTC2621 LTC2602/LTC2612/ LTC2622 LTC2604/LTC2614/ LTC2624 LTC2606/LTC2616/ LTC2626 COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA Dual 14-Bit Rail-to-Rail VOUT DAC VCC = 5V(3V), Low Power, Deglitched Single 16-Bit VOUT DAC with Serial Interface in SO-8 Low Power, Deglitched, Rail-to-Rail VOUT Parrallel 5V/3V 16-Bit VOUT DAC Octal 10-/8-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2μs for 10V Step 250μA per DAC, 2.5V to 5.5V Supply Range, Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Rail-to-Rail Output, SPI Interface Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Interface Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Interface Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Interface Single 16-/14-/12-Bit VOUT DACs with I2C Interface in 10-Lead DFN 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface 2605fa 18 Linear Technology Corporation LT 1109 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009