LTC3718EG

FEATURES s s s s LTC3718 Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination DESCRIPTIO The LTC®3718 is a high current, high efficiency synchronous switching regulator controller for DDR and QDRTM memory termination. It operates from an input as low as 1.5V and provides a regulated output voltage equal to (0.5)VIN. The controller uses a valley current control architecture to enable high frequency operation with very low on-times without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. The LTC3718 uses a pair of standard 5V logic level N-channel external MOSFETs, eliminating the need for expensive P-channel or low threshold devices. Forced continuous operation reduces noise and RF interference. Fault protection is provided by internal foldback current limiting, an output overvoltage comparator and an optional short-circuit timer. Soft-start capability for supply sequencing can be accomplished using an external timing capacitor. OPTI-LOOP® compensation allows the transient response to be optimized over a wide range of loads and output capacitors. , LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc. s s s s s s s s s s s s Very Low VIN(MIN): 1.5V Ultrafast Transient Response True Current Mode Control 5V Drive for N-Channel MOSFETs Eliminates Auxillary 5V Supply No Sense Resistor Required Uses Standard 5V Logic-Level N-Channel MOSFETs VOUT(MIN): 0.4V VOUT Tracks 1/2 VIN or External VREF Symmetrical Source and Sink Output Current Limit Adjustable Switching Frequency tON(MIN) < 100ns Power Good Output Voltage Monitor Programmable Soft-Start Output Overvoltage Protection Optional Short-Circuit Shutdown Timer Small 24-Lead SSOP Package APPLICATIO S s s s s Bus Termination: DDR/QDR Memory, SSTL, HSTL, ... Servers, RAID Systems Distributed Power Systems Synchronous Buck with General Purpose Boost TYPICAL APPLICATIO SHDN VREF LTC3718 ION VOUT CSS 0.1µF C1 820pF X7R VFB1 PGOOD SW1 SENSE + PGND1 SENSE RUN/SS RC 4.75k ITH SGND1 SGND2 VFB2 RF1 12.1k COUT: SANYO POSCAP 4TPB470M – BOOST TG DB CMDSH-3 CB 0.33µF M1 Si7440DP CIN1 22µF ×2 D1 B340A VIN 2.5V RON 237k L1 0.8µH + M2 Si7440DP D2 B340A BG INTVCC VIN1 VIN2 PGND2 SW2 CIN2 4.7µF COUT 470µF ×2 EFFICIENCY (%) VOUT 1.25V ±10A VIN L2 4.7µH D3 MBR0520 RF2 37.4k CVCC1 10µF L1: SUMIDA CEP125-0R8MC L2: PANASONIC ELJPC4R7MF 3718 TA01 Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply 3718fa U U U Efficiency vs Load Current 100 90 80 70 60 50 40 30 20 10 0 0.01 0.1 FIGURE 1 CIRCUIT 1 10 LOAD CURRENT (A) 100 3718 G05/TA01a VIN = 2.5V VOUT = 1.25V 1 LTC3718 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW RUN/SS VON PGOOD VRNG ITH SGND1 ION VFB1 VREF 1 2 3 4 5 6 7 8 9 24 BOOST 23 TG 22 SW1 21 SENSE + 20 SENSE – 19 PGND1 18 BG 17 INTVCC 16 VIN1 15 VIN2 14 PGND2 13 SW2 Input Supply Voltage (VIN2) .......................10V to – 0.3V Boosted Topside Driver Supply Voltage (BOOST) ............................................... 42V to – 0.3V VIN1, ION, SW1 Voltage ............................. 36V to – 0.3V RUN/SS, PGOOD Voltages ......................... 7V to – 0.3V VON, VREF, VRNG Voltages .......(INTVCC + 0.3V) to – 0.3V ITH, VFB1 Voltages .................................... 2.7V to – 0.3V SW2 Voltage ............................................. 36V to – 0.4V VFB2 Voltage ................................................. VIN2 + 0.3V SHDN Voltage ......................................................... 10V TG, BG, INTVCC Peak Currents .................................. 2A TG, BG, INTVCC RMS Currents ............................ 50mA Operating Ambient Temperature Range (Note 4) ................................... – 40°C to 85°C Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC3718EG SHDN 10 SGND2 11 VFB2 12 G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL Buck Regulator IQ(VIN1) Input DC Supply Current (VIN1) Normal Shutdown Supply Current Feedback Voltage Accuracy Feedback Voltage Line Regulation Feedback Voltage Load Regulation Error Amplifier Transconductance On-Time Minimum On-Time Minimum Off-Time Maximum Current Sense Threshold VPGND – VSW1 (Source) Minimum Current Sense Threshold VPGND – VSW1 (Sink) Output Overvoltage Fault Threshold Output Undervoltage Fault Threshold RUN Pin Start Threshold RUN Pin Latchoff Enable PARAMETER The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN1 = 15V, VIN2 = 1.5V unless otherwise noted. CONDITIONS MIN TYP MAX UNITS VRUN/SS = 0V ITH = 1.2V (Note 3) VIN1 = 4V to 36V, ITH = 1.2V (Note 3) ITH = 0.5V to 1.9V (Note 3) ITH = 1.2V (Note 3) ION = 60µA, VON = 1.5V ION = 30µA, VON = 1.5V ION = 180µA VRNG = 1V, VFB1 = VREF/2 – 50mV VRNG = 0V, VFB1 = VREF/2 – 50mV VRNG = INTVCC, VFB1 = VREF/2 – 50mV VRNG = 1V, VFB1 = VREF/2 + 50mV VRNG = 0V, VFB1 = VREF/2 + 50mV VRNG = INTVCC, VFB1 = VREF/2 + 50mV q q q q q 1000 15 – 0.65 0.1 0.002 – 0.05 0.93 200 400 1.13 250 500 50 300 108 76 148 –140 –97 – 200 8 q 2000 30 0.65 – 0.3 1.33 300 600 100 400 162 114 222 –190 –133 – 270 12 2 4.5 VFB1 ∆VFB1(LINE) ∆VFB1(LOAD) gm(EA) tON tON(MIN) tOFF(MIN) VSENSE(MAX) 135 95 185 –165 –115 – 235 10 – 25 1.5 4 VSENSE(MIN) ∆VFB1(OV) ∆VFB1(UV) VRUN/SS(ON) VRUN/SS(LE) 0.8 RUN/SS Pin Rising 2 U µA µA % %/V % mS ns ns ns ns mV mV mV mV mV mV % % V V 3718fa W U U WW W LTC3718 ELECTRICAL CHARACTERISTICS SYMBOL VRUN/SS(LT) IRUN/SS(C) IRUN/SS(D) VIN(UVLO) TG RUP TG RDOWN BG RUP BG RDOWN TG tr TG tf BG tr BG tf VINTVCC ∆VLDO(LOAD) PGOOD Output ∆VFB1H ∆VFB1L ∆VFB1(HYS) VPGL Boost Regulator VIN2(MIN) VIN2(MAX) IQ(VIN2) Minimum Operating Voltage Maximum Operating Voltage Input DC Supply Current (VIN2) Normal Shutdown Supply Current VFB2 Feedback Voltage VFB2 Pin Bias Current Boost Reference Line Regulation BOOST Switching Frequency BOOST Maximum Duty Cycle BOOST Switch Current Limit BOOST Switch VCESAT BOOST Switch Leakage Current SHDN Input Voltage High SHDN Input Voltage Low SHDN Pin Bias Current PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysterisis PGOOD Low Voltage PARAMETER RUN Pin Latchoff Threshold Soft-Start Charge Current Soft-Start Discharge Current VIN1 Undervoltage Lockout TG Driver Pull-Up On Resistance TG Driver Pull-Down On Resistance BG Driver Pull-Up On Resistance BG Driver Pull-Down On Resistance TG Rise Time TG Fall Time BG Rise Time BG Fall Time Internal VCC Voltage Internal VCC Load Regulation The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN1 = 15V, VIN2 = 1.5V unless otherwise noted. CONDITIONS RUN/SS Pin Falling VRUN/SS = 0V VRUN/SS = 4.5V, VFB = 0V VIN Falling VIN Rising TG High TG Low BG High BG Low CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF 6V < VIN1 IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. Minimum Off-time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3718 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, 3718fa W UU 13 LTC3718 APPLICATIO S I FOR ATIO due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON Output Voltage Programming When VFB is connected to VOUT, the output voltage is regulated to one half of the voltage at the VREF pin. A resistor connected between VFB and VOUT can be used to further adjust the output voltage according to the following equation:  60k + RFB  VOUT = VREF    120k  If VREF exceeds 3V, resistors should be placed in series with the VREF pin and the VFB pin to avoid exceeding the input common mode range of the internal error amplifier. To maintain the VOUT = VREF/2 relationship, the resistor in series with the VREF pin should be made twice as large as the resistor in series with the VFB pin. RFB 249k VOUT RFB 499k VREF VREF 3718 F04 VFB1 LTC3718 Figure 4 External Gate Drive Buffers The LTC3718 drivers are adequate for driving up to about 30nC into MOSFET switches with RMS currents of 50mA. Applications with larger MOSFET switches or operating at frequencies requiring greater RMS currents will benefit from using external gate drive buffers such as the LTC1693. BOOST Q1 FMMT619 10Ω TG Q2 FMMT720 SW GATE OF M1 10Ω BG Q4 FMMT720 PGND 3718 F05 INTVCC Q3 FMMT619 GATE OF M2 Figure 5. Optional External Gate Driver 14 U Alternately, the external buffer circuit shown in Figure 5 can be used. Note that the bipolar devices reduce the signal swing at the MOSFET gate. Soft-Start and Latchoff with the RUN/SS Pin The RUN/SS pin provides a means to shut down the LTC3718 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 0.8V puts the LTC3718 into a low quiescent current shutdown (IQ < 30µA). Releasing the pin allows an internal 1.2µA current source to charge up the external timing capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about: W UU tDELAY = 1.5V C SS = 1.3s/µF C SS 1.2µA ( ) When the voltage on RUN/SS reaches 1.5V, the LTC3718 begins operating with a clamp on ITH of approximately 0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH is raised until its full 2.4V range is available. This takes an additional 1.3s/µF, during which the load current is folded back. During start-up, the maximum load current is reduced until either the RUN/SS pin rises to 3V or the output reaches 75% of its final value. The pin can be driven from logic as shown in Figure 6. Diode D1 reduces the start delay while allowing CSS to charge up slowly for the softstart function. INTVCC RSS* RUN/SS RSS* D2* RUN/SS VIN 3.3V OR 5V D1 CSS CSS 3718 F06 *OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF (6a) (6b) Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated After the controller has been started and given adequate time to charge up the output capacitor, CSS is used as a short-circuit timer. After the RUN/SS pin charges above 4V, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. A 1.8µA current then begins discharging CSS. If the fault condition 3718fa LTC3718 APPLICATIO S I FOR ATIO persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 4V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: CSS > COUT VOUT RSENSE (10 – 4 [F/V s]) Generally 0.1µF is more than sufficient. Overcurrent latchoff operation is not always needed or desired. The feature can be overridden by adding a pullup current greater than 5µA to the RUN/SS pin. The additional current prevents the discharge of C SS during a fault and also shortens the soft-start period. Using a resistor to VIN as shown in Figure 6a is simple, but slightly increases shutdown current. Connecting a resistor to INTVCC as shown in Figure 6b eliminates the additional shutdown current, but requires a diode to isolate CSS. Any pull-up network must be able to pull RUN/SS above the 4.2V maximum threshold of the latchoff circuit and overcome the 4µA maximum discharge current. INTVCC Supply The 5V supply that powers the drivers and internal circuitry within the LTC3718 can be supplied by either an internal P-channel low dropout regulator if VIN is greater than 5V or the internal boost regulator if VIN is less than 5V. The INTVCC pin can supply up to 50mA RMS and must be bypassed to ground with a minimum of 4.7µF tantalum or other low ESR capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and high frequency of operation may cause the LTC3718 to exceed its maximum junction temperature rating or RMS current rating. In continuous mode operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics. U Inductor Selection for Boost Converter For the boost converter, the inductance should be 4.7µH for input voltages less then 3.3V and 10µH for inputs above 3.3V. The inductor should have a saturation current rating of approximately 0.5A or greater. A guide for selecting an inductor for the boost converter is to choose a ripple current that is 40% of the current supplied by the boost converter. To ensure that the ripple current doesn’t exceed a specified amount, the inductance can be chosen according to the following equation: W UU  VIN2(MAX)  VIN2(MIN)  1 –   VOUT (BOOST)  L= ∆I • f Diode D3 Selection A Schottky diode is recommended for use in the boost converter section. The Motorola MBR0520 is a very good choice. Boost Converter Output Capacitor Because the LTC3718’s boost converter is internally compensated, loop stability must be carefully considered when choosing its output capacitor. Small, low cost tantalum capacitors have some ESR, which aids stability. However, ceramic capacitors are becoming more popular, having attractive characteristics such as near-zero ESR, small size and reasonable cost. Simply replacing a tantalum output capacitor with a ceramic unit will decrease the phase margin, in some cases to unacceptable levels. With the addition of a phase-lead capacitor and isolating resistor, the boost converter portion of the LTC3718 can be used successfully with ceramic output capacitors. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3718 circuits: 3718fa 15 LTC3718 APPLICATIO S I FOR ATIO 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 1% up to 10% as the output current varies from 1A to 10A for a 1.5V output. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f 3. INTVCC current. This is the sum of the MOSFET driver and control currents. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or 16 U discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 1 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. Design Example As a design example, take a supply with the following specifications: VIN = 2.5V, VOUT = 1.25V ± 100mV, IOUT(MAX) = ± 6A, f = 300kHz. First, calculate the timing resistor with VON = VOUT: RON = 2.5V − 0.7V = 240k (2.5V)(300kHz)(10pF ) W UU Next, use a standard value of 237k and choose the inductor for about 40% ripple current at the maximum VIN: L=  1.25V  1.25V 1–  = 0.87µH (300kHz)(0.4)(6A)  2.5V  Selecting a standard value of 1µH results in a maximum ripple current of: ∆IL =  1.25V  1.25V 1–  = 2.1A (300kHz)(1µH)  2.5V  Next, choose the synchronous MOSFET switch. Choosing an IRF7811A (RDS(ON) = 0.013Ω, CRSS = 60pF, θJA = 50°C/W) yields a nominal sense voltage of: VSNS(NOM) = (6A)(1.3)(0.013Ω) = 101.4mV Tying VRNG to 1V will set the current sense voltage range for a nominal value of 100mV with current limit occurring at 133mV. To check if the current limit is acceptable, assume a junction temperature of about 10°C above a 50°C ambient with ρ60°C = 1.15: ILIMIT ≥ 133mV 1 + (2.1A) = 9.9A (1.15)(0.013Ω) 2 3718fa LTC3718 APPLICATIO S I FOR ATIO 2 and double check the assumed TJ in the MOSFET: PBOT 2.5V – 1.25V  9.9A  =   (1.15)(0.013Ω) 2.5V 2 = 0.18W TJ = 50°C + (0.18W)(50°C/W) = 59°C Now check the power dissipation of the top MOSFET at current limit with ρ90°C = 1.35: PTOP = = 0.87 W ( ) (1.35)(0.013Ω) 2 + (1.7)(2.5V )(9.9A ) (60pF )(300kHz ) 1.25V 9.9A 2.5V 2 TJ = 50°C + (0.87W)(50°C/W) = 93.5°C CIN is chosen for an RMS current rating of about 6A at temperature. The output capacitors are chosen for a low RPG 100k RR2 39.2k CSS 0.1µF 1 2 3 RUN/SS VON PGOOD VRNG ITH SGND1 ION VFB1 VREF SHDN SGND2 VFB2 RF2 37.4k CF4 1000pF BOOST TG SW1 SENSE + SENSE – PGND1 BG INTVCC VIN1 VIN2 PGND2 SW2 24 23 22 21 20 19 18 17 16 15 14 13 PGOOD RR1 10k RC 4.75k C1 820pF C2 100pF RON 237k 4 5 6 7 8 9 10 11 12 RF1 12.1k RF3 10k Figure 7. Design Example: 1.25V/± 6A at 300kHz from 2.5V 3718fa U ESR of 0.005Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: ∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (2.6A) (0.005Ω) = 13mV However, a 0A to 6A load step will cause an output change of up to: ∆VOUT(STEP) = ∆ILOAD (ESR) = (6A) (0.005Ω) = 30mV The inductor for the boost converter is selected by first choosing an allowable ripple current. The boost converter will be operating in discontinous mode. If we select a ripple current of 170mA for the boost converter, then:  3.3V  3.3V 1 −  5V   (170mA)(1.4MHz) L= = 4.7µH W UU The complete circuit is shown in Figure 7. VIN 2.5V DB CMDSH-3 CB 0.33µF CIN1 22µF ×2 CIN2 330µF M1 IRF7811A D1 B340A L1 1µH COUT 270µF ×2 VOUT 1.25V ± 6A LTC3718 M2 IRF7811A D2 B340A CIN2 4.7µF L2 4.7µH CVCC1 10µF 3718 F07 D3 MBR0520 17 LTC3718 APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. • The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. • Place CIN, COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. • Place LTC3718 chip with Pins 13 to 24 facing the power components. Keep the components connected to Pins 1 to 12 close to LTC3718 (noise sensitive components). • Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3718. Use several bigger vias for power components. • Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. • Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. CSS 1 2 3 4 C1 RC 5 6 RON C2 7 8 9 10 11 12 RF5 RUN/SS VON PGOOD VRNG ITH BOOST TG SW1 SENSE + SENSE – 24 23 22 21 20 19 18 17 16 15 3718 F08 SGND1 PGND1 LTC3718 ION BG VFB1 VREF SHDN SGND2 VFB2 RF4 INTVCC VIN1 VIN2 PGND2 SW2 RF3 Figure 8. LTC3718 Layout Diagram 3718fa 18 U • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 8. • Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. • Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. • Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. • Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes. • Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and PGND pins. • Connect the top driver boost capacitor CB closely to the BOOST and SW pins. + CB M1 DB L1 VOUT CIN VIN COUT M2 D2 CVCC W UU – 14 13 CIN2 L2 D3 BOLD LINES INDICATE HIGH CURRENT PATHS LTC3718 TYPICAL APPLICATIO RPG 100k PGOOD C1 820pF X7R RC 4.75k C2 100pF RON 237k RF1 12.1k *SANYO POSCAP 4TPB470M **SUMIDA CEP125-0R8MC ***PANASONIC ELJPC4R7MF ****SANYO POSCAP 6TPB330M PACKAGE DESCRIPTIO 7.8 – 8.2 0.42 ± 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 0.22 – 0.38 0.05 (.009 – .015) (.002) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 3. DRAWING NOT TO SCALE 0.09 – 0.25 (.0035 – .010) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U One Half VIN, ± 10A Bus Terminator CIN1 22µF X5R ×2 VIN 2.5V CIN2**** 330µF CSS 0.1µF X7R 1 2 3 4 5 6 7 8 9 10 11 12 RF3 10k RUN/SS VON PGOOD VRNG ITH SGND1 ION VFB1 VREF SHDN SGND2 VFB2 RF2 37.4k CF4 1000pF X7R BOOST TG SW1 SENSE + SENSE – PGND1 BG INTVCC VIN1 VIN2 PGND2 SW2 24 23 22 21 20 19 18 17 16 15 14 13 CVCC1 10µF 6.3V X5R 3718 TA02 DB CMDSH-3 CB 0.33µF X7R M1 Si7440DP D1 B340A L1** 0.8µH + M2 Si7440DP D2 B340A LTC3718 COUT* 470µF ×2 VOUT 1.25V ±10A 22µF X5R 4.7µF 6.3V X7R L2*** 4.7µH D3 MBR0520 G Package 24-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 1.25 ± 0.12 7.90 – 8.50* (.311 – .335) 24 23 22 21 20 19 18 17 16 15 14 13 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 2.0 (.079) 0 ° – 8° 0.55 – 0.95 (.022 – .037) 0.65 (.0256) BSC G24 SSOP 0802 3718fa 19 LTC3718 TYPICAL APPLICATIO Dual Output 2.5V, ± 10A Buck Converter and 5V to 12V/130mA Boost Converter VIN 6V TO 24V CIN1**** 33µF ×2 25V M1 Si7440DP D1 B340A RPG 100k PGOOD C1 3300pF X7R RFB 249k RREF 499k RF1 12.3k RELATED PARTS PART NUMBER LT 1613 LTC1735 LTC1772 LTC1773 LTC1778 LTC1876 LTC3413 LTC3711 LTC3713 LTC3717 LTC3778 LTC3831 ® DESCRIPTION ThinSOT Step-Up DC/DC Converter High Efficiency Synchronous Switching Regulator ThinSOT Current Mode Step-Down Controller Synchronous Current Mode Step-Down Controller No RSENSETM Synchronous Step-Down Controller 2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator 3A Monolithic DDR Memory Termination Regulator 5-Bit, Adjustable, No RSENSE Synchronous Step-Down Controller Low Input Voltage, High Power, No RSENSE Synchronous Controller High Power DDR Memory Termination Regulator No RSENSE Synchronous Step-Down Controller High Power DDR Memory Termination Regulator TM No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. 3718fa 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U CSS 0.1µF X7R 1 2 3 4 RC 10k C2 100pF RON 237k 5 6 7 8 9 10 11 12 RF3 10k RUN/SS VON PGOOD VRNG ITH SGND1 ION VFB1 VREF SHDN SGND2 VFB2 RF2 107k CF4 200pF X7R BOOST TG SW1 SENSE + SENSE – 24 23 22 21 20 19 18 17 16 15 14 13 CVCC2 4.7µF DB CMDSH-3 CB 0.33µF X7R L1** 1.8µH PGND1 BG INTVCC VIN1 VIN2 PGND2 SW2 LTC3718 RF 1Ω M2 Si7440DP CF 0.1µF D2 B340A + COUT* 470µF ×2 VOUT1 2.5V ±10A CIN2 22µF X5R VIN2 5V L2*** 10µH CVCC1 4.7µF X5R D3 MBR0520 *SANYO POSCAP 4TPB470M **TOKO D104C ***PANASONIC ELJPC4R7MF ****KEMET T495X336K025AS VOUT2 12V 130mA 3718 TA03 COMMENTS 1.4MHz, 1.1V < VIN < 10V 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, SSOP-16 Small Solution, 2.5V ≤ VIN ≤ 9.8V, 0.8V ≤ VOUT ≤ VIN 2.65V ≤ VIN ≤ 8.5V, 0.8V ≤ VOUT ≤ VIN, 550kHz Operation, > 90% Efficiency No Sense Resistor Required, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ VIN 2.6V ≤ VIN ≤ 36V, Dual Output: 0.8V ≤ VOUT ≤ (0.9)VIN ±3A Output Current, 2.25V ≤ VIN ≤ 5.5V 0.925V ≤ VOUT ≤ 2V, 4V ≤ VIN ≤ 36V No Sense Resistor Required, VIN(MIN) = 1.5V 4V ≤ VIN ≤ 36V, VOUT Tracks VIN or VREF, IOUT from 1A to 20A Optional Sense Resistor, 4V ≤ VIN ≤ 36V, 0.6V ≤ VOUT ≤ VIN VOUT Tracks 1/2 VIN or VREF, 3V ≤ VIN ≤ 8V, IOUT from 1A to 20A LT/TP 1103 1K REV A • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2002