L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
DESCRIPTION
The L4C383 is a flexible, high speed, cascadable 16-bit Arithmetic and Logic Unit. The L4C383 is capable of performing up to 32 different arithmetic or logic functions. The L4C383 can be cascaded to perform 32-bit or greater operations. See “Cascading the L4C383” on the next page. ARCHITECTURE The L4C383 operates on two 16-bit operands (A and B) and produces a 16bit result (F). Five select lines control the ALU and provide 19 arithmetic and 13 logical functions. Registers are provided on both the ALU inputs and the output, but these may be bypassed under user control. An internal feedback path allows the registered ALU output to be routed to one or both of the ALU inputs, accommodating chain operations and accumulation. ALU OPERATIONS The S4–S0 lines specify the operation to be performed. The ALU functions and their select codes are shown in Table 1. ALU STATUS
A15-A0 16 B15-B0 16
FEATURES
u High-Speed (15ns), Low Power 16-bit Cascadable ALU u Extended Function Set (32 Advanced ALU Functions) u All Registers Have a Bypass Path for Complete Flexibility u Replaces IDT7383 u 68-pin PLCC, J-Lead
L4C383 BLOCK DIAGRAM
ENA
A REGISTER
B REGISTER
ENB
FTAB FFFFH FFFFH
The ALU provides Overflow and Zero status bits. A Carry output is also provided for cascading multiple devices, however it is only defined for the 19 arithmetic functions. The ALU sets the Zero output when all 16 output bits are zero. The N, C16 and OVF flags for the arithmetic operations are defined in Table 2. OPERAND REGISTERS The L4C383 has two 16-bit wide input registers for operands A and B. These registers are rising edge triggered by a common clock. The A register is enabled for input by setting the ENA control LOW, and the B register is enabled for input by setting the ENB control LOW. When either the ENA control or ENB control is HIGH, the data in the corresponding input register will not change. This architecture allows the L4C383 to accept arguments from a single 16-bit data bus. For those applications that do not require registered inputs, both the A and B operand registers can be bypassed with the FTAB control line.
5
S4-0
N, C16 OVF, Z
4
ALU
16
C0
RESULT REGISTER
ENF
FTF 16 OE 16
CLK
TO ALL REGISTERS
F15-F0
Arithmetic Logic Units
1
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
TABLE 2. ALU STATUS FLAGS
for i = 0 ... 15 for i = 0 ... 15
TABLE 1. ALU FUNCTIONS
S4-S0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 FUNCTION A + B + C0 A OR B A + B + C0 A + B + C0 A + C0 A OR F A – 1 + C0 A + C0 A + F + C0 A OR F A + F + C0 A + F + C0 F + B + C0 A OR B F + B + C0 F + B + C0 A XOR B A AND B A AND B A XNOR B A XOR F A AND F A AND F ALL 1's + C0 B + C0 A AND B B + C0 B – 1 + C0 F + C0 A OR B F – 1 + C0 F + C0
Bit Carry Generate = gi = AiBi Bit Carry Propagate = pi = Ai + Bi P0 = p0 Pi = pi (Pi–1) and G0 = g0 Gi = gi + pi (Gi–1) Ci = Gi–1 + Pi–1 (C0) then C16 OVF Zero N= = G15 + P15C0 = C15 XOR C16 = All Output Bits Equal Zero Sign Bit of ALU Operation
for i = 1 ... 15
for i = 1 ... 15 for i = 1 ... 15
OUTPUT REGISTER The output of the ALU drives the input of a 16-bit register. This rising-edgetriggered register is clocked by the same clock as the input registers. When the ENF control is LOW, data from the ALU will be clocked into the output register. By disabling the output register, intermediate results can be held while loading new input operands. Three-state drivers controlled by the OE input allow the L4C383 to be configured in a single bidirectional bus system. The output register can be bypassed by asserting the FTF control signal (FTF = HIGH). When the FTF control is asserted, output data is routed around the output register, however, it continues to function normally via the ENF control. The contents of the output register will again be available on the output pins if FTF is released. CASCADING THE L4C383 Cascading the L4C383 to 32 bits is accomplished simply by connecting the C16 output of the least significant slice to the C0 input of the most sig-nificant slice. The S4-S0, ENA, ENB, and ENF lines are
common to both devices. The Zero output flags should be logically ANDed to produce the Zero flag for the 32-bit result. The OVF and C16 outputs of the most significant slice are valid for the 32-bit result. Propagation delay calculations for this configuration require two steps: First determine the propagation delay from the input of interest to the C16 output of the lower slice. Add this number to the delay from the C0 input of the upper slice to the output of interest (of the C0 setup time, if the F register is used). The sum gives the overall input-to-output delay (or setup time) for the 32-bit configuration. This method gives a conservative result, since the C16 output is very lightly loaded. Formulas for calculation of all critical delays for a 32-bit system are shown in Figures 4A through 4D. Cascading to greater than 32 bits can be accomplished by simply connecting the C16 output of each slice to the C0 input of the next more significant slice. Propagation delays are calculated as for the 32-bit case, except that the C0 to C16 delays for all intermediate slices must be added to the overall delay for each path.
When the FTAB control is asserted (FTAB = HIGH), data is routed around the A and B input registers; however, they continue to function normally via the ENA and ENB controls. The contents of the input registers will again be available to the ALU if the FTAB control is released.
Arithmetic Logic Units
2
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
FIGURE 4A.
FTAB = 0, FTF = 0
From Clock Clock C0 S4-S0 A, B C0 S4-S0 ENA, ENB, ENF Minimum cycle time
A 31 -A 16
To ©F © Other © Other © Other Setup time Setup time Setup time Setup time
= = = = = = = = =
Calculated Specification Limit Same as 16-bit case (Clock © C16) + (C0 © Out) (C0 © C16) + (C0 © Out) (S4-S0 © C16) + (C0 © Out) Same as 16-bit case (C0 © C16) + (C0 Setup time) (S4-S0 © C16) + (C0 Setup time) Same as 16-bit case (Clock © C16) + (C0 Setup time)
B 15 -B 0
B 31 -B 16
A 15 -A 0
D Q
D Q
D Q
D Q
CLOCK C0, S 4 –S 0
A F
B C0
A C 16 F
B C0
D Q
CLOCK 16
D Q
CLOCK
MOST SIGNIFICANT SLICE
16 F 31 -F 16
F 15 -F 0
LEAST SIGNIFICANT SLICE
FIGURE 4B.
FTAB = 0, FTF = 1
From Clock Clock C0 C0 S4-S0 S4-S0 A, B C0 S4-S0 ENA, ENB, ENF Minimum cycle time To ©F © Other ©F © Other ©F © Other Setup time Setup time Setup time Setup time = = = = = = = = = = = Calculated Specification Limit (Clock © C16) + (C0 © F) (Clock © C16) + (C0 © Out) (C0 © C16) + (C0 © F) (C0 © C16) + (C0 © Out) (S4-S0 © C16) + (C0 © F) (S4-S0 © C16) + (C0 © Out) Same as 16-bit case (C0 © C16) + (C0 Setup time) (S4-S0 © C16) + (C0 Setup time) Same as 16-bit case (Clock © C16) + (C0 Setup time)
A 31 -A 16
B 31 -B 16
A 15 -A 0
B 15 -B 0
D Q
D Q
D Q
D Q
CLOCK C0, S 4 –S 0
A F
B C0
A C 16 16 F 15 -F 0 F
B C0
MOST SIGNIFICANT SLICE
16 F 31 -F 16
LEAST SIGNIFICANT SLICE
Arithmetic Logic Units
3
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
FIGURE 4C.
FTAB = 1, FTF = 0
From To Clock ©F A, B © Other C0 © Other S4-S0 © Other A, B Setup time C0 Setup time S4-S0 Setup time ENA, ENB, ENF Setup time Minimum cycle time (F register accumulate loop) = = = = = = = = = Calculated Specification Limit Same as 16-bit case (A, B © C16) + (C0 © Out) (C0 © C16) + (C0 © Out) (S4-S0 © C16) + (C0 © Out) (A, B © C16) + (C0 Setup time) (C0 © C16) + (C0 Setup time) (S4-S0 © C16) + (C0 Setup time) Same as 16-bit case (Clock © C16) + (C0 Setup time)
A 31 -A 16
B 31 -B 16
A 15 -A 0
B 15 -B 0 C0, S 4 –S 0
A F
B C0
A C 16 F
B C0
D Q
CLOCK 16
D Q
CLOCK
MOST SIGNIFICANT SLICE
16 F 31 -F 16
F 15 -F 0
LEAST SIGNIFICANT SLICE
FIGURE 4D.
FTAB = 1, FTF = 1
From To A, B ©F A, B © Other C0 ©F C0 © Other S4-S0 ©F © Other S4-S0 A, B Setup time C0 Setup time S4-S0 Setup time ENA, ENB, ENF Setup time Minimum cycle time (F register accumulate loop) = = = = = = = = = = = Calculated Specification Limit (A, B © C16) + (C0 © F) (A, B © C16) + (C0 © Out) (C0 © C16) + (C0 © F) (C0 © C16) + (C0 © Out) (S4-S0 © C16) + (C0 © F) (S4-S0 © C16) + (C0 © Out) (A, B © C16) + (C0 Setup time) (C0 © C16) + (C0 Setup time) (S4-S0 © C16) + (C0 Setup time) Same as 16-bit case (Clock © C16) + (C0 Setup time)
A 31 -A 16
B 31 -B 16
A 15 -A 0
B 15 -B 0 C0, S 4 –S 0
A F
B C0
A C 16 16
F
B C0
MOST SIGNIFICANT SLICE
16 F 31 -F 16
F 15 -F 0
LEAST SIGNIFICANT SLICE
Arithmetic Logic Units
4
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent
(Note 3)
Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA
Min 2.4
Typ
Max
Unit V
0.5 2.0 0.0 VCC 0.8 ±20 ±20 15 30 1.5
V V V µA µA mA mA
Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6) (Note 7)
Arithmetic Logic Units
5
08/16/2000–LDS.383-E
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE tDIS tENA ENA, ENB, ENF S4-S0 C0 A15-A0, B15-B0 Input FTAB = 1, FTF = 1 A15-A0, B15-B0 Clock C0 S4-S0 FTAB = 1, FTF = 0 A15-A0, B15-B0 Clock C0 S4-S0 FTAB = 0, FTF = 1 Clock C0 S4-S0 FTAB = 0, FTF = 0 Clock C0 S4-S0 From Input L4C383-55* To Output 20 20 18 16
DEVICES INCORPORATED
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321
Setup Hold FTAB = 0 55 56 37 55 10 44 21 8 L4C383-55* 36 38 — 42 2 0 0 2 Setup Hold FTAB = 1 10 44 21 35 46 53 34 42 2 0 0 2 37 36 22 42 Setup Hold FTAB = 0 40 46 30 40 10 32 16 8 L4C383-40* 30 30 — 32 2 2 0 0 FTAB = 1 28 10 32 16 40 44 28 34 2 2 0 0 32 32 20 35
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321
F15-F0 — 32 — — 56 37 55 32 — — L4C383-55* 38 — 42 38 — 42 36 — — 42 N OVF, Z 46 — 34 42 53 34 42 53 34 42 C16 F15-F0 37 — 22 42 36 22 42 36 22 42 — 26 — — 46 30 40 26 — — L4C383-40* 30 — — 32 30 — 32 30 — 32 N OVF, Z 40 — 28 34 44 28 34 44 28 34 32 — 20 35 32 20 35 32 20 35
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 1 65432109876543210987654321 6543210987654321098765432
L4C383-55* 15 15 43 L4C383-40* 10 10 34
65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321
L4C383-40* 18
L4C383-26
16
Lowgoing Pulse
Highgoing Pulse
Minimum Cycle Time
6
16-bit Cascadable ALU (Extended Set)
Setup Hold Setup Hold
C16 F15-F0
Arithmetic Logic Units
FTAB = 0 26 28 22 26 — 22 — — 28 22 26 22 — — 18 8 8 8 L4C383-26 L4C383-26 22 22 — 22 22 — — 22 22 — 22 22 — 22 2 0 0 2 N OVF, Z Setup Hold L4C383-26 FTAB = 1 18 16 22 — 18 22 26 18 22 22 26 18 22 26 18 22 8 8
08/16/2000–LDS.383-E
L4C383
10 10 20 C16 2 0 0 2 22 — 18 22 22 18 22 22 22 18 22 22 18 22
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE tDIS tENA ENA, ENB, ENF S4-S0 C0 A15-A0, B15-B0 Input FTAB = 1, FTF = 1 A15-A0, B15-B0 Clock C0 S4-S0 FTAB = 1, FTF = 0 A15-A0, B15-B0 Clock C0 S4-S0 FTAB = 0, FTF = 1 Clock C0 S4-S0 FTAB = 0, FTF = 0 Clock C0 S4-S0 From Input L4C383-20 To Output 8 8 6
DEVICES INCORPORATED
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321
Setup Hold 15 15 14 15 FTAB = 0 12 10 5 5 L4C383-15* 14 15 — 14 0 0 0 0 Setup Hold FTAB = 1 12 12 10 15 15 13 15 5 0 0 0 0 14 15 13 14
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 1 65432109876543210987654321 6543210987654321098765432
— 11 — — 15 14 15 11 — — L4C383-15* 14 — — 14 15 — 14 15 — 14 N OVF, Z 15 — 13 15 15 13 15 15 13 15 C16 14 — 13 14 15 13 14 15 13 14
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
F15-F0
Setup Hold
FTAB = 0
20 20 18 20
— 11 — —
20 18 20
11 — —
15
12
5
5
L4C383-20
L4C383-20
16 20 — 18
20 — 18
20 — 18
16 — — 18
0
0
0
0
N
OVF, Z
Setup Hold
FTAB = 1
15
12
14
20 20 14 20
20 — 14 20
20 14 20
20 14 20
5
C16 F15-F0
0
0
0
0
17 20 14 18
17 — 14 18
20 14 18
20 14 18
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 1 3210987654321 321098765432
L4C383-15* 14 4 4
3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321
L4C383-15* 6
Lowgoing Pulse
Highgoing Pulse
Minimum Cycle Time
7
16-bit Cascadable ALU (Extended Set)
L4C383-20
18
5
5
Arithmetic Logic Units L4C383
08/16/2000–LDS.383-E
DEVICES INCORPORATED
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 1 432109876543212109876543210987654321098765432121098765432109876543210987654321 43210987654321210987654321098765432109876543212109876543210987654321098765432
F15-F0 65 68 42 66 — 37 — — 68 42 66 37 — — L4C383-65* 44 44 — 48 44 — 48 44 — 48 44 — — 48 N OVF, Z 56 63 42 48 56 — 42 48 63 42 48 63 42 48 C16 F15-F0 44 45 25 48 44 — 25 48 45 25 48 45 25 48 45 56 32 46 — 28 — — 56 32 46 28 — — L4C383-45* 32 34 — 38 32 — — 38 34 — 38 34 — 38 N OVF, Z 46 50 32 38 46 — 32 38 50 32 38 50 32 38 C16 F15-F0 36 34 23 38 36 — 23 38 34 23 38 34 23 38 30 34 26 30 — 26 — — 34 26 30 26 — — L4C383-30* 28 28 — 28 28 — — 28 28 — 28 28 — 28 N OVF, Z 28 34 22 28 28 — 22 28 34 22 28 34 22 28 C16 28 — 22 28 28 22 28 28 28 22 28 28 22 28
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321
Setup Hold FTAB = 0 12 50 25 10 L4C383-65* 2 0 0 3 Setup Hold FTAB = 1 12 50 25 43 2 0 0 3 Setup Hold FTAB = 0 10 36 20 8 L4C383-45* 3 2 0 0 Setup Hold Setup Hold FTAB = 1 33 10 36 20 3 2 0 0 FTAB = 0 10 20 12 8 L4C383-30* 3 2 0 0 Setup Hold FTAB = 1 20 10 20 12 3 2 0 0
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
ENA, ENB, ENF
S4-S0
C0
A15-A0, B15-B0
Input
FTAB = 1, FTF = 1 A15-A0, B15-B0 Clock C0 S4-S0
FTAB = 1, FTF = 0 A15-A0, B15-B0 Clock C0 S4-S0
FTAB = 0, FTF = 1 Clock C0 S4-S0
FTAB = 0, FTF = 0 Clock C0 S4-S0
From Input
To Output
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 1 65432121098765432109876543210987654321 6543212109876543210987654321098765432
L4C383-65* 20 20 52 L4C383-45* 15 15 38 L4C383-30* 12 12 26
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5
*DISCONTINUED SPEED GRADE tDIS tENA L4C383-65* 22 22 L4C383-45* 20 20 L4C383-30* 18 18
Lowgoing Pulse
Highgoing Pulse
Minimum Cycle Time
8
16-bit Cascadable ALU (Extended Set)
Arithmetic Logic Units L4C383
08/16/2000–LDS.383-E
DEVICES INCORPORATED
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321
Setup Hold FTAB = 0 25 25 21 25 19 14 7 7 L4C383-25* 20 24 — 22 0 0 0 2 Setup Hold FTAB = 1 19 14 14 25 24 18 24 7 0 0 0 2 22 24 18 22 Setup Hold 20 20 17 20 FTAB = 0 16 12 6 6 L4C383-20* 17 20 — 18 0 2 0 0 Setup Hold FTAB = 1 12 16 12 20 20 16 20 6 0 2 0 0 17 20 16 18
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321 0987654321098765432121098765432109876543210987654321
F15-F0 — 14 — — 25 21 25 14 — — L4C383-25* 24 — 22 24 — 22 20 — — 22 N OVF, Z 25 — 18 24 24 18 24 24 18 24 C16 F15-F0 22 — 18 22 24 18 22 24 18 22 — 14 — — 20 17 20 14 — — L4C383-20* 17 — — 18 20 — 18 20 — 18 N OVF, Z 20 — 16 20 20 16 20 20 16 20 C16 17 — 16 18 20 16 18 20 16 18
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
ENA, ENB, ENF
S4-S0
C0
A15-A0, B15-B0
Input
FTAB = 1, FTF = 1 A15-A0, B15-B0 Clock C0 S4-S0
FTAB = 1, FTF = 0 A15-A0, B15-B0 Clock C0 S4-S0
FTAB = 0, FTF = 1 Clock C0 S4-S0
FTAB = 0, FTF = 0 Clock C0 S4-S0
From Input
To Output
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 65432109876543210987654321 1 65432109876543210987654321 6543210987654321098765432
L4C383-25* 20 8 8 L4C383-20* 18 6 6
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
*DISCONTINUED SPEED GRADE tDIS tENA L4C383-25* 14 14 L4C383-20* 10 10
Lowgoing Pulse
Highgoing Pulse
Minimum Cycle Time
9
16-bit Cascadable ALU (Extended Set)
Arithmetic Logic Units L4C383
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
NOTES
9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
DUT
S1 IOL CL IOH VTH
FIGURE B. THRESHOLD LEVELS
tENA OE
Z 0
1.5 V 1.5 V 1.5 V
tDIS
3.5V Vth VOL*
0.2 V
0 1
Z Z
1.5 V
VOH*
0.2 V
Z
1
0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Arithmetic Logic Units
10
08/16/2000–LDS.383-E
DEVICES INCORPORATED
ORDERING INFORMATION
7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321
Speed
26 ns 20 ns
–55°C to +125°C — MIL-STD-883 COMPLIANT
–55°C to +125°C — COMMERCIAL SCREENING
0°C to +70°C — COMMERCIAL SCREENING
Plastic J-Lead Chip Carrier (J2)
A9 A10 A11 A12 A13 A14 A15 CLK VCC GND C16 GND N ZERO OVF ENF FTF
68-pin
L4C383JC26 L4C383JC20
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9
8
7
6
5
4
3
2
Top View
1 68 67 66 65 64 63 62 61 60
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
B7 B6 B5 B4 B3 B2 B1 B0 ENA ENB FTAB S4 S3 S2 S1 S0 C0
11
OE F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
16-bit Cascadable ALU (Extended Set)
68-pin
G
H
D
C
K
E
B
A
F
L
J
ZERO
GND C16
GND VCC
ENF OVF
CLK
FTF
A14
A12
A10
1
A15
A13
A11
F15
OE
A9
A8
N
2
F13
F14
A6
A7
3
Ceramic Pin Grid Array (G1)
Discontinued Package
(i.e., Component Side Pinout)
F11
F12
A4
A5
4
Arithmetic Logic Units
Through Package F10 A2 A3 F9
5
Top View
A0
A1
F7
F8
6
B14
B15
F5
F6
7
B12
B13
F3
F4
8
B10
B11
F1
F2
9
08/16/2000–LDS.383-E
FTAB ENB
ENA
10
C0 S3 S1 B1 B3 B5 B8 B9
F0
L4C383
11
S4
S0 S2 B0 B2 B4 B6 B7
A8 A7 A6 A5 A4 A3 A2 A1 A0 B15 B14 B13 B12 B11 B10 B9 B8
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