LSH33

LSH33 DEVICES INCORPORATED 32-bit Barrel Shifter with Registers LSH33 DEVICES INCORPORATED 32-bit Barrel Shifter with Registers DESCRIPTION The LSH33 is a 32-bit high speed shifter designed for use in floating point normalization, word pack/ unpack, field extraction, and similar applications. It has 32 data inputs, and 16 output lines. Any shift configuration of the 32 inputs, including circular (barrel) shifting, left shifts with zero fill, and right shifts with sign extension are possible. In addition, a built-in priority encoder is provided to aid floating point normalization. Input/Output registers provide complete pipelined operation. Both have independent bypass paths for complete flexibility. When FTI = 1, the input registers are bypassed. Likewise, when FTO= 1, the output registers are bypassed. SHIFT ARRAY The 32 inputs, which can be registered, to the LSH33 are applied to a 32-bit shift array. The 32 outputs, which can also be registered, of this array are then multiplexed down to 16 lines for presentation at the device outputs. The array may be configured such that any contiguous 16-bit field (including wraparound of the 32 inputs) may be presented to the output pins under control of the shift code field (wrap mode). Alternatively, the wrap feature may be disabled, resulting in zero or sign bit fill, as appropriate (fill mode). The shift code control assignments and the resulting input to output mapping for the wrap mode are shown in Table 1. Essentially the LSH33 is configured as a left shift device. That is, a shift code of 000002 results in no shift of the input field. A code of 000012 provides an effective left shift of 1 position, etc. When viewed as a right shift, the shift code corresponds to the two’s complement of the shift distance, i.e., a shift code of 111112 (–110) results in a right shift of one position, etc. When not in the wrap mode, the LSH33 fills bit positions for which there is no corresponding input bit. The fill value and the positions filled depend on the RIGHT/LEFT (R/L) direction pin. This pin is a don’t care input when in wrap mode. For left shifts in fill mode, lower bits are filled with zero as shown in Table 2. For right shifts, however, the SIGN input is used as the fill value. Table 3 depicts the bits to be filled as a function of shift code for the right shift case. Note that the R/L input changes only the fill convention, and does not affect the definition of the shift code. FEATURES u 32-bit Input, 32-bit Output Multiplexed to 16 Lines u Full 0-31 Position Barrel Shift Capability u Integral Priority Encoder for 32-bit Floating Point Normalization u Sign-Magnitude or Two’s Complement Mantissa Representation u 32-bit Linear Shifts with Sign or Zero Fill u Independent Priority Encoder Outputs for Block Floating Point u 68-pin PLCC, J-Lead LSH33 BLOCK DIAGRAM SIGN I 31 -I 0 G G CLK ENI 2:1 32 2:1 FTI 32:5 PRIORITY ENCODE 32 5 2:1 RIGHT/LEFT FILL/WRAP 16 32-bit BARREL SHIFT ARRAY 16 CLK ENO FTO G G G 2:1 5 NORM 5 2:1 2:1 2:1 16 SI/O 4 -SI/O 0 MS/LS OE Y 15 -Y 0 Special Arithmetic Functions 1 08/16/2000–LDS.33-O LSH33 DEVICES INCORPORATED 32-bit Barrel Shifter with Registers In fill mode, as in wrap mode, the shift code input represents the number of shift positions directly for left shifts, but the two’s complement of the shift code results in the equivalent right shift. However, for fill mode the R/L input can be viewed as the most significant bit of a 6-bit two’s complement shift code, comprised of R/L concatenated with the SI4–SI0 lines. Thus, a positive shift code (R/L = 0) results in a left shift of 0–31 positions, and a negative code (R/L = 1) a right shift of up to 32 positions. The LSH33 can thus effectively select any contiguous 32-bit field out of a (sign extended and zero filled) 96-bit "input." OUTPUT MULTIPLEXER The shift array outputs can be registered and then applied to a 2:1 multiplexer controlled by the MS/LS select line. This multiplexer makes available at the output pins either the most significant or least significant 16 outputs of the shift array. PRIORITY ENCODER Y1 I 1 I 0 0 0 • • • TABLE 1. WRAP MODE SHIFT CODE DEFINITIONS Shift Code 00000 00001 00010 00011 • • • Y 31 I 31 I 30 I 29 I 28 • • • Y 30 I 30 I 29 I 28 I 27 • • • Y 29 I 29 I 28 I 27 I 26 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y 16 I 16 I 15 I 14 I 13 • • • Y 15 I 15 I 14 I 13 I 12 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y2 I 2 I 1 I 0 I 31 • • • Y1 I 1 I 0 I 31 I 30 • • • Y0 I 0 I 31 I 30 I 29 • • • 01111 10000 10001 10010 • • • I 16 I 15 I 14 I 13 • • • I 15 I 14 I 13 I 12 • • • I 14 I 13 I 12 I 11 • • • I 1 I 0 I 31 I 30 • • • I 0 I 31 I 30 I 29 • • • I 19 I 18 I 17 I 16 • • • I 18 I 17 I 16 I 15 • • • I 17 I 16 I 15 I 14 • • • 11100 11101 11110 11111 I 3 I 2 I 1 I 0 I 2 I 1 I 0 I 31 I 1 I 0 I 31 I 30 I 20 I 19 I 18 I 17 I 19 I 18 I 17 I 16 I 6 I 5 I 4 I 3 I 5 I 4 I 3 I 2 I 4 I 3 I 2 I 1 TABLE 2. Shift Code 00000 00001 00010 00011 • • • FILL MODE SHIFT CODE DEFINITIONS — LEFT SHIFT Y 31 I 31 I 30 I 29 I 28 • • • Y 30 I 30 I 29 I 28 I 27 • • • Y 29 I 29 I 28 I 27 I 26 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y 16 I 16 I 15 I 14 I 13 • • • Y 15 I 15 I 14 I 13 I 12 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y2 I 2 I 1 I 0 0 • • • Y0 I 0 0 0 0 • • • 01111 10000 10001 10010 • • • I 16 I 15 I 14 I 13 • • • I 15 I 14 I 13 I 12 • • • I 14 I 13 I 12 I 11 • • • I 1 I 0 0 0 • • • I 0 0 0 0 • • • 0 0 0 0 • • • 0 0 0 0 • • • 0 0 0 0 • • • 11100 11101 11110 11111 I 3 I 2 I 1 I 0 I 2 I 1 I 0 0 I 1 I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The 32-bit input bus drives a priority encoder which is used to determine the first significant position for purposes of normalization. The priority encoder produces a five-bit code representing the location of the first non-zero bit in the input word. Code assignment is such that the priority encoder output represents the number of shift positions required to left align the first non-zero bit of the input word. Prior to the priority encoder, the input bits are individually exclusive OR’ed with the SIGN input. This allows normalization in floating point systems using two’s complement mantissa representation. A negative value in two’s complement representation will cause the exclusive OR gates to invert the input data to the encoder. As a result, the leading significant digit will always be "1." Special Arithmetic Functions 2 0 8/16/2000–LDS.33-O LSH33 DEVICES INCORPORATED 32-bit Barrel Shifter with Registers This affects only the encoder inputs; the shift array always operates on the raw input data. The priority encoder function table is shown in Table 4. NORMALIZE MULTIPLEXER The NORM input, when asserted, results in the priority encoder output driving the internal shift code inputs directly. When using the NORM function, the LSH33 should be placed in fill mode, with the R/L input low. When NORM is high (not asserted), the SI/O 4–SI/O 0 port acts as the shift code input to the shifter. APPLICATIONS EXAMPLES Normalization of mantissas up to 32 bits can be accomplished directly by a single LSH33. To do this, the NORM input is asserted, and fill mode and left shift are selected. The normalized mantissa is then available at the device output in two 16-bit segments, under the control of the output data multiplexer select, the MS/LS signal. If it is desirable to avoid the necessity of multiplexing output data in 16-bit segments, two LSH33 devices can be used in parallel. Both devices receive the same input word, with the MS/LS select line of one wired high, and the other low. Each device will then independently determine the shift distance required for normalization, and the full 32 bits of output data will be available simultaneously. TABLE 3. Shift Code 00000 00001 00010 00011 • • • FILL MODE SHIFT CODE DEFINITIONS — RIGHT SHIFT Y 31 S S S S • • • Y 30 S S S S • • • Y 29 S S S S • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y 16 S S S S • • • Y 15 S S S S • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y2 S S S I 31 • • • Y1 S S I 31 I 30 • • • Y0 S I 31 I 30 I 29 • • • 01111 10000 10001 10010 • • • S S S S • • • S S S S • • • S S S S • • • S S I 31 I 30 • • • S I 31 I 30 I 29 • • • I 19 I 18 I 17 I 16 • • • I 18 I 17 I 16 I 15 • • • I 17 I 16 I 15 I 14 • • • 11100 11101 11110 11111 S S S S S S S I 31 S S I 31 I 30 I 20 I 19 I 18 I 17 I 19 I 18 I 17 I 16 I 6 I 5 I 4 I 3 I 5 I 4 I 3 I 2 I 4 I 3 I 2 I 1 TABLE 4. 31 I 30 I PRIORITY ENCODER FUNCTION TABLE 29 I ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• 16 I 15 I ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• 2 I 1 I 0 I Shift Code 00000 00001 00010 • • 1 0 0 • • X 1 0 • • X X 1 • • X X X • • X X X • • X X X • • X X X • • X X X • • 0 0 0 • • 0 0 0 • • 0 0 0 • • 1 0 0 • • X 1 0 • • X X X • • X X X • • X X X • • 01111 10000 10001 • • 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 X 1 0 11110 11111 11111 Special Arithmetic Functions 3 08/16/2000–LDS.33-O LSH33 DEVICES INCORPORATED 32-bit Barrel Shifter with Registers MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent (Note 3) Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±20 ±20 10 30 1.5 V V V µA µA mA mA Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) Special Arithmetic Functions 4 0 8/16/2000–LDS.33-O 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Lowgoing Pulse DEVICES INCORPORATED GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns) 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 7654321098765 765432109876543210987654321 765432109876543210987654321 65432109876543210987654321 765432109876543210987654321 7 43210987654321 Y15-Y0 20 / 20 20 20 15 20 / 20 15 15 20 20 15 15 15 LSH33-20* SO4-SO0 20 / — — — — 20 / — — — — 15 — 15 — GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns) 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 76543210987654321098765432 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 1 765432109876543210987654321 8 8 8 8 FTI = 0 LSH33-20* 0 0 0 0 Setup Hold 8 8 8 8 FTI = 1 0 0 0 2 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 Setup Hold 12 12 17 12 FTI = 0 52 52 28 LSH33-40* 0 0 0 3 Setup Hold 12 12 17 20 FTI = 1 55 / — — — — 0 0 0 2 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 65432109876543210987654321 765432109876543210987654321 765432109876543210987654321 765432109876543210987654321 7 Y15-Y0 73 / 40 73 / 40 52 52 28 28 28 28 28 LSH33-40* SO4-SO0 55 / — — — — 28 — 28 — TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns) SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C) ENI, ENO R/L, F/W SI4-SI0 I31-I0, SIGN Input FTI = 1, FTO = 1 I31-I0, SIGN (NORM = 0/1) SI4-SI0 R/L, F/W MS/LS FTI = 1, FTO = 0 CLK MS/LS FTI = 0, FTO= 1 CLK (NORM = 0/1) SI4-SI0 FTI = 0, FTO = 0 CLK MS/LS From Input R/L, F/W MS/LS To Output CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns) 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 LSH33-20* 15 7 7 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 LSH33-40* 12 12 30 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 LSH33-20* 15 15 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 LSH33-40* 20 20 tDIS tENA LSH33-30 17 17 Highgoing Pulse Minimum Cycle Time 5 Setup Hold 10 10 15 10 FTI = 0 Y15-Y0 58 / 30 58 / 30 40 40 24 40 40 24 24 24 24 24 32-bit Barrel Shifter with Registers LSH33-30 LSH33-30 0 0 0 3 Setup Hold Setup Hold Special Arithmetic Functions SO4-SO0 10 10 15 15 FTI = 1 42 / — — — — 42 / — — — — 24 — 24 — 0 0 0 2 LSH33-30 20 9 9 08/16/2000–LDS.33-O LSH33 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE tDIS tENA ENI, ENO R/L, F/W SI4-SI0 I31-I0, SIGN Input FTI = 1, FTO = 1 I31-I0, SIGN (NORM = 0/1) SI4-SI0 R/L, F/W MS/LS FTI = 1, FTO = 0 CLK MS/LS FTI = 0, FTO= 1 CLK (NORM = 0/1) SI4-SI0 FTI = 0, FTO = 0 CLK MS/LS From Input R/L, F/W MS/LS LSH33-50* To Output 22 22 Lowgoing Pulse DEVICES INCORPORATED GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns) 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 Y15-Y0 80 / 50 80 / 50 62 62 32 62 62 62 32 32 32 32 LSH33-50* SO4-SO0 65 / — — — — 65 / — — — — 32 — 32 — Y15-Y0 73 / 40 73 / 40 52 52 28 52 52 28 28 28 28 28 LSH33-40* SO4-SO0 55 / — — — — 55 / — — — — 28 — 28 — Y15-Y0 58 / 30 40 40 24 58 / 30 24 24 40 40 24 24 24 LSH33-30* SO4-SO0 42 / — — — — 42 / — — — — 24 — 24 — GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns) 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 432109876543212109876543210987654321098765432121098765432109876543210987654321 Setup Hold 15 15 20 15 FTI = 0 LSH33-50* 0 0 0 3 Setup Hold 15 15 20 20 FTI = 1 0 0 0 2 Setup Hold 12 12 17 12 FTI = 0 LSH33-40* 0 0 0 3 Setup Hold Setup Hold 12 12 17 20 FTI = 1 0 0 0 2 10 10 15 10 FTI = 0 LSH33-30* 0 0 0 0 Setup Hold 10 10 15 15 FTI = 1 0 0 0 2 TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns) SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C) CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns) 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 65432121098765432109876543210987654321 LSH33-50* 15 15 35 LSH33-40* 12 12 30 LSH33-30* 20 9 9 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 LSH33-40* 20 20 LSH33-30* 17 17 Highgoing Pulse Minimum Cycle Time 6 32-bit Barrel Shifter with Registers Special Arithmetic Functions LSH33 0 8/16/2000–LDS.33-O LSH33 DEVICES INCORPORATED 32-bit Barrel Shifter with Registers NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Special Arithmetic Functions 7 08/16/2000–LDS.33-O DEVICES INCORPORATED ORDERING INFORMATION 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 68-pin G H D C K E B A F L J Y31/15 Y30/14 Y28/12 Y26/10 Y24/8 Y22/6 Y20/4 Y18/2 Y16/0 VCC SI/O0 SI/O1 SI/O2 SI/O3 SI/O4 SIGN FTO ENO CLK NORM F/W FTI I31 Speed 30 ns –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING Plastic J-Lead Chip Carrier (J2) I30 I31 SIGN SI/O4 SI/O3 SI/O2 SI/O1 SI/O0 NORM CLK ENI FTI ENO FTO R/L F/W Y31/15 68-pin LSH33JC30 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 Top View 1 68 67 66 65 64 63 62 61 60 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 GND I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 VCC VCC 8 Y30/14 Y29/13 Y28/12 Y27/11 Y26/10 Y25/9 Y24/8 Y23/7 Y22/6 Y21/5 Y20/4 Y19/3 Y18/2 Y17/1 Y16/0 OE MS/LS I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 GND 32-bit Barrel Shifter with Registers 1 Y29/13 Y27/11 Y25/9 Y23/7 Y21/5 Y19/3 Y17/1 ENI R/L I30 I29 2 Special Arithmetic Functions I27 I28 Ceramic Pin Grid Array (G1) 3 Discontinued Package (i.e., Component Side Pinout) I25 I26 4 Through Package I23 I24 5 Top View I21 I22 6 I19 I20 7 I17 I18 8 OE MS/LS I15 I16 0 8/16/2000–LDS.33-O 9 GND GND 10 I12 I14 I10 I0 I2 I4 I6 I8 LSH33 VCC 11 I13 I11 I1 I3 I5 I7 I9