TB62747AFNAG

TB62747AFG/AFNG/AFNAG/BFNAG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62747AFG,TB62747AFNG, TB62747AFNAG,TB62747BFNAG 16-Output Constant Current LED Driver TB62747AFG The TB62747 series is comprised of constant-current drivers designed for LEDs and LED panel displays. The regulated current sources are designed to provide a constant current, which is adjustable through one external resistor. The TB62747 series incorporates 16 channels of shift registers, latches, AND gates and constant-current outputs. Fabricated using the Bi-CMOS process, the TB62747 series satisfies the system requirement of high-speed data transmission. The TB62747 series is RoHS compatible SSOP24-P-300-1.00B TB62747AFNG SSOP24-P-300-0.65A TB62747AFNAG/BFNAG SSOP24-P-150-0.64 Features • • • Power supply voltages: VDD = 3.3 V to 5.0 V 16-output built-in Output current setting range : 1.5 to 35 mA @ VDD = 3.3 V, VO = 0.4 to 1.0 V : 1.5 to 45 mA @ VDD = 5.0 V, VO = 0.4 to 1.2 V • • Constant current output voltage: VO = 26 V (max) Current accuracy (@ REXT = 1.2 kΩ, VO = 0.4 V, VDD = 3.3 V, 5.0 V) : Between outputs: ± 1.5 % (max) : Between devices: ± 1.5 % (max) Fast response of output current : twOE(L) = 100 ns (min) Control data format: serial-in, parallel-out Weight SSOP24-P-300-1.00B : 0.29 g (typ.) SSOP24-P-300-0.65A : 0.14 g (typ.) SSOP24-P-150-0.64: 0.14 g (typ.) • • • • • • • Input signal voltage level: 3.3 V and 5 V CMOS interfaces (Schmitt trigger input) Serial data transfer rate: 25 MHz (max) @cascade connection Operation temperature range: Topr = −40 to 85 °C Power on reset (POR) Package : AFG type : AFNG type : AFNAG type : BFNAG type : SSOP24-P-300-1.00B : SSOP24-P-300-0.65A : SSOP24-P-150-0.64 : SSOP24-P-150-0.64 1 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Pin Assignment (top view) TB62747AFG/AFNG/AFNAG TB62747BFNAG GND SIN SCK SLAT OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VDD REXT SOUT OE OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT14 OUT15 OE OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 SOUT REXT VDD GND SIN SCK SLAT OUT0 OUT1 OUT9 OUT8 Note1: Short circuiting an output pin to a power supply pin (VDD or VLED*), or short-circuiting the REXT pin to the GND pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. Please keep this in mind when determining the wiring layout for the power supply and GND pins. *VLED: LED power supply 2 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Block Diagram OUT0 OUT1 OUT15 VDD OUT0 OUT1 Constant current outputs OUT15 B.G POR GND REXT OE SLAT G Q15 Q0 Q1 16-bit D-latch D0 D1 D15 R SIN SCK D0 Q15 Q0 Q1 16-bit shift register Q15 R SOUT 3 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Truth Table SCK SLAT H L H OE L L L L H SIN Dn Dn + 1 Dn + 2 Dn + 3 Dn + 3 OUT0 … OUT7 … OUT15 *1 Dn … Dn − 7 … Dn − 15 No Change Dn + 2 … Dn − 5 … Dn − 13 Dn + 2 … Dn − 5 … Dn − 13 OFF SOUT Dn − 15 Dn − 14 Dn − 13 Dn − 13 Dn − 13 −*2 −*2 Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the respective output will be OFF. Note2: “-“ is irrelevant to the truth table. Timing Diagram n=0 SCK L H SIN L H SLAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H L H OE L ON OUT0 OFF ON OUT1 OFF ON OUT2 OFF ON OUT15 OFF H SOUT L Note 1: Note 2: The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit. Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin is set to “H” the latch circuit does not hold data. The data will instead pass onto output. When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to the data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of the data. 4 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Pin Functions Pin No AFG AFNG AFNAG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 GND SIN SCK SLAT OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OE SOUT REXT VDD BFNAG Pin Name I/O Function ⎯ I I I O O O O O O O O O O O O O O O O I O The ground pin. The serial data input pin. The serial data transfer clock input pin. The latch signal input pin. Data is saved at L level. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. The constant current output enable signal input pin. During the “H” level, the output will be forced off. The serial data output pin. The constant current value setting resistor connection pin. The power supply input pin. ⎯ ⎯ 5 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Absolute Maximum Ratings (Ta = 25°C) Characteristics Power supply voltage Output current Logic input voltage Output voltage Operating temperature Storage temperature Thermal resistance Symbol VDD IO VIN VO Topr Tstg Rth(j-a) Rating *1 Unit V mA V V °C °C °C/W −0.4 to 6.0 55 −0.3 to VDD + 0.3 *2 −0.3 to 26 −40 to 85 −55 to 150 94 (AFG) *3, 120 (AFNG) *3, 80.07(AFNAG/BFNAG) When mounted PCB 1.32 (AFG) *3, 1.04 (AFNG) *3, 1.56(AFNAG/BFNAG) When mounted PCB Power dissipation PD*4 W Note1: Voltage is ground referenced. Note2: However, do not exceed 6V. Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming) Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each degree (1°C) that the ambient temperature is exceeded (Ta = 25°C). Operating Conditions DC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C) Characteristics Power supply voltage Output voltage when OFF High level logic input voltage Low level logic input voltage High level SOUT output current Low level SOUT output current Constant current output Symbol VDD VO (ON) VIH VIL IOH IOL IO1 IO2 OUTn SIN,SCK, SLAT , OE SIN,SCK, SLAT , OE Test Conditions Min 3.0 0.4 0.7 × VDD GND Typ. Max 5.5 4.0 VDD 0.3 × VDD Unit V V V V mA mA mA 45 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ OUTn , VDD = 3.3 V, VO = 0.4 to 1.0 V OUTn , VDD = 5.0 V, VO = 0.4 to 1.2 V ⎯ ⎯ 1.5 1.5 −1 1 35 AC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C) Characteristics Serial data transfer frequency Hold time Symbol fSCK tHOLD1 tHOLD2 Setup time Maximum clock rise time Maximum clock fall time tSETUP1 tSETUP2 tr tf Test Circuits 6 6 6 6 6 6 6 *1 *1 Test Conditions Min Typ. Max 25 Unit MHz ns ns ns ns ns ns ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5 5 5 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 500 500 ⎯ ⎯ Note1: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform,it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when designing your application. 6 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Electrical Characteristics (Unless otherwise specified, VDD = 3.3V, Ta = 25°C) Characteristics High level logic output voltage Low level logic output voltage High level logic input current Low level logic input current Symbol VOH VOL IIH IIL IDD1 Power supply current IDD2 IDD3 Output current Constant current error(Ch to Ch) Constant current error(IC to IC) Output OFF leak current Constant current power supply voltage regulation Constant current regulation Pull-up resistor Pull-down resistor output voltage IO Test Circuits 1 1 2 3 4 4 4 5 5 5 5 5 5 3 2 Test Conditions IOH = −1 mA IOL = +1 mA VIN = VDD, OE , SIN, SCK VIN = GND, SLAT , SIN, SCK VO = 25 V, REXT = OPEN, SCK = “L”, OE = “H” REXT = 1.2 kΩ, All output off REXT = 1.2 kΩ, All output on VDD = 3.3 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 3.3 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 3.3 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 3.3 V, VO = 25 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 3.0 to 3.6 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 3.3 V, VO = 0.4 to 3.0 V, REXT = 1.2 kΩ, OUT0 to OUT15 OE SLAT Min VDD − 0.4 Typ. Max Unit V V ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 14 ⎯ 0.4 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 250 250 µA µA mA mA mA mA % % −1 1.0 4.0 8.0 ⎯ ±1.5 ±1.5 0.5 ∆IO ∆IO(IC) IOK %VDD %VO RUP RDOWN ±1 ±1 ⎯ ±1 ±1 500 500 µA % %/V kΩ kΩ ±2 ⎯ 800 800 Electrical Characteristics (Unless otherwise specified, VDD = 5.0V, Ta = 25°C) Characteristics High level logic output voltage Low level logic output voltage High level logic input current Low level logic input current Symbol VOH VOL IIH IIL IDD1 Power supply current IDD2 IDD3 Output current Constant current error(Ch to Ch) Constant current error(IC to IC) Output OFF leak current Constant current power supply voltage regulation Constant current regulation Pull-up resistor Pull-down resistor output voltage IO Test Circuits 1 1 2 3 4 4 4 5 5 5 5 5 5 3 2 Test Conditions IOH = −1 mA IOL = +1 mA VIN = VDD, OE , SIN, SCK VIN = GND, SLAT , SIN, SCK VO = 25 V, REXT = OPEN, SCK = “L”, OE = “H” REXT = 1.2 kΩ, All output off REXT = 1.2 kΩ, All output on VDD = 5.0 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 5.0 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 5.0 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 5.0 V, VO = 25 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 4.5 to 5.5 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 VDD = 5.0 V, VO = 0.4 to 3.0 V, REXT = 1.2 kΩ, OUT0 to OUT15 OE SLAT Min VDD − 0.4 Typ. Max Unit V V ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 14 ⎯ 0.4 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 250 250 µA µA mA mA mA mA % % −1 1.0 4.5 8.0 ⎯ ±1.5 ±1.5 0.5 ∆IO ∆IO(IC) IOK %VDD %VO RUP RDOWN ±1 ±1 ⎯ ±1 ±1 500 500 µA % %/V kΩ kΩ ±2 ⎯ 800 800 7 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Switching Characteristics (Unless otherwise specified, VDD = 3.3V, Ta = 25°C) Characteristics SCK- OUT0 SLAT - OUT0 OE - OUT0 Propagation time delay SCK-SOUT SCK- OUT0 SLAT - OUT0 OE - OUT0 SCK-SOUT Output rise time Output fall time Enable pulse width Clock pulse width Latch pulse width Symbol tpLH1 tpLH2 tpLH3 tpLH tpHL1 tpHL2 tpHL3 tpHL tor tof twOE(L) twSCK twSLAT Test Circuits 6 6 6 6 6 6 6 6 6 6 6 6 6 Test Conditions SLAT = “H”, OE = “L” OE = “L” SLAT = “H” CL=10.5 pF SLAT = “H”, OE = “L” OE = “L” SLAT = “H” CL=10.5 pF 10 to 90% of voltage waveform 90 to 10% of voltage waveform OE = “L” *1 SCK = “H” or “L” SLAT = “H” Min Typ. 20 20 20 20 30 70 70 20 20 25 Max 300 300 300 35 340 340 340 35 90 180 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ⎯ ⎯ ⎯ 10 ⎯ ⎯ ⎯ 10 ⎯ ⎯ 100 20 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note1: At the condition of twOE(H) = 250ns or more Switching Characteristics (Unless otherwise specified, VDD = 5.0V, Ta = 25°C) Characteristics SCK- OUT0 SLAT - OUT0 OE - OUT0 Propagation time delay SCK-SOUT SCK- OUT0 SLAT - OUT0 OE - OUT0 SCK-SOUT Output rise time Output fall time Enable pulse width Clock pulse width Latch pulse width Symbol tpLH1 tpLH2 tpLH3 tpLH tpHL1 tpHL2 tpHL3 tpHL tor tof twOE(L) twSCK twSLAT Test Circuits 6 6 6 6 6 6 6 6 6 6 6 6 6 Test Conditions SLAT = “H”, OE = “L” OE = “L” SLAT = “H” CL=10.5 pF SLAT = “H”, OE = “L” OE = “L” SLAT = “H” CL=10.5 pF 10 to 90% of voltage waveform 90 to 10% of voltage waveform OE = “L” *1 SCK = “H” or “L” SLAT = “H” Min Typ. 20 20 20 20 30 70 70 20 20 25 Max 300 300 30 35 340 340 340 35 90 180 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ⎯ ⎯ ⎯ 10 ⎯ ⎯ ⎯ 10 ⎯ ⎯ 100 20 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note1: At the condition of twOE(H) = 250ns or more 8 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG I/O Equivalent Circuits 1. SCK, SIN VDD (SCK) (SIN) GND 2. OE VDD OE GND 3. SLAT VDD SLAT 4. SOUT VDD SOUT GND GND 5. OUT0 to OUT15 OUT0 to OUT15 GND 9 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Test Circuits Test Circuit1: High level logic input voltage / Low level logic input voltage SCK SIN SLAT VDD OUT0 F.G OE OUT7 OUT15 VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) REXT GND SOUT IO = -1mA to 1mA CL = 10.5 pF V Test Circuit2: High level logic input current / Pull-down resistor VIN = VDD A A A SCK SIN SLAT VDD OUT0 A OE OUT7 OUT15 REXT GND SOUT Test Circuit3: Low level logic input current / Pull-up resistor A A A A SCK SIN SLAT VDD OUT0 OE OUT7 OUT15 REXT GND SOUT VDD = 3.3 V, 5.0 V CL = 10.5 pF REXT VDD = 3.3 V, 5.0 V CL = 10.5 pF REXT VDD = 3.3 V, 5.0 V REXT 10 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Test Circuit4: Power supply current SCK SIN SLAT VDD OUT0 F.G OE OUT7 OUT15 VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) A VDD = 3.3 V, 5.0 V VDD = 3.3 V, 5.0 V REXT GND SOUT REXT = 1.2kΩ CL = 10.5 pF Test Circuit5: Constant current output / Output OFF leak current / Constant current error Test Circuit5: Constant current power supply voltage regulation / Constant current output voltage regulation SCK SIN SLAT VDD OUT0 A F.G OE OUT7 A OUT15 VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) REXT GND SOUT A REXT = 1.2kΩ CL = 10.5 pF Test Circuit6: Switching Characteristics SCK SIN SLAT VDD RL = 300 Ω OUT0 CL OUT7 RL CL OUT15 RL F.G OE VLED = 4.9 V VDD = 3.0 V, 5.5 V REXT = 1.2kΩ CL = 10.5 pF VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) REXT GND SOUT CL = 10.5 pF VO = 0.4 V, 25 V VO = 0.4 V 11 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Timing Waveforms 1. SCK, SIN, SOUT twSCK SCK 50% tSETUP1 SIN 50% tHOLD1 SOUT 50% tpLH/tpHL 50% 50% twSCK 50% 90% 10% tr tf 90% 10% 2. SCK, SIN, SLAT , OE , OUT0 SCK 50% 50% SIN tHOLD2 SLAT 50% twSLAT OE tSETUP2 50% twOE(L) 50% 50% OUT0 tpHL1/tpLH1 tpHL2/tpLH2 50% 3. OE , OUT0 twOE 50% OE 50% tpHL3 tpLH3 OFF 90% OUT0 10% tof 10% tor ON 50% 50% 90% 12 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Reference data *This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Output Current – REXT Resistor 50 45 40 35 IOUT (mA) 30 25 20 15 10 5 0 100 VDD=5.0V VO=1.0V Ta=25°C IOUT - REXT Theoretical value IOUT (A) = 1.13 (V) ÷ REXT (Ω) × 14.9 All output on Ta=25°C VOUT=0.7V 1000 REXT (Ω ) 10000 17 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Reference data *This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Output Current – Duty (LED turn-on rate) IO - Duty 50 45 40 35 IO (mA) 25 20 15 10 5 0 0 20 40 60 Duty - Turn on rate (%) 80 100 IO (mA) 30 AFNG AFNAG/BFNAG AFG IO - Duty 50 45 40 35 30 25 20 15 10 5 0 0 20 40 60 Duty - Turn on rate (%) 80 100 AFNAG/BFNAG AFG AFNG Ta=25°C VDD=5.0V VO=1.0V ON PCB Ta=55°C VDD=5.0V VO=1.0V ON PCB IO - Duty 50 45 40 35 IO (mA) 30 25 20 15 10 5 0 0 20 40 60 Duty - Turn on rate (%) 80 100 AFNG AFG AFNAG/BFNAG Ta=85°C VDD=5.0V VO=1.0V ON PCB Power dissipation – Ta PD - Ta 1.8 1.6 1.4 1.2 PD (W) 1.0 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 Ta (℃) 60 70 80 90 AFG AFNG AFNAG/BFNAG 18 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Package Dimensions Weight: 0.29 g (typ.) 19 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Package Dimensions Weight: 0.14 g (typ.) 20 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Package Dimensions SSOP24-P-150-0.64 Unit : Inch 0.337 to 0.344 0.0325(REF) 0.150 to 0.157 0.025 0.054 to 0.068 0.008 to 0.012 0.010(TYP) 0.016 to 0.034 Weight: 0.14 g (typ.) 0.004 to 0.098 21 2009-01-21 0.229 to 0.244 TB62747AFG/AFNG/AFNAG/BFNAG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. 22 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG IC Usage Considerations Notes on handling of ICs [1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. [4] Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. Points to remember on handling of ICs (1) Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (TJ) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. (2) Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. 23 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 20070701-EN • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. • The products described in this document are subject to foreign exchange and foreign trade control laws. 24 2009-01-21