KSZ8841-PMQLI

KSZ8841-PMQL Single-Port Ethernet MAC Controller with PCI Interface Rev.1.5 General Description The KSZ8841-series single-port chip includes PCI and non-PCI CPU interfaces. This datasheet describes the KSZ8841-PMQL with PCI CPU interface chips. For information on the KSZ8841 non-PCI CPU interface chips, refer to the KSZ8841-MQL datasheet. The KSZ8841-PMQL is a single port Fast Ethernet MAC chip with a 32-bit/33MHz PCI processor interface. Designed to be fully compliant with the IEEE 802.3u standard, the KSZ8841-PMQL is also available in an industrial temperature-grade version of the KSZ8841PMQL, the KSZ8841-PMQLI. (See Ordering Information). Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower power consumption. The KSZ8841-PMQL is designed using a low-power CMOS process that features a single 3.3V power supply with 5V tolerant I/O. LinkMD® The KSZ8841-PMQL is a mixed signal analog/digital device offering Wake-on-LAN technology. Its extensive feature set includes management information base (MIB) counters and CPU control/data interfaces. The KSZ8841-PMQL includes a unique cable diagnostics feature called LinkMD®. This feature calculates the length of the cabling plant and determines if there is an open/short condition in the cable. Accompanying software allows the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8841PMQL supports Hewlett Packard (HP) Auto-MDIX thereby eliminating the need to differentiate between straight or crossover cables in applications. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Functional Diagram Figure 1. KSZ8841-PMQL Function Diagram LinkMD is a registered trademark of Micrel, Inc Magic Packet is a trademark of Advanced Micro Devices, Inc. Product/Application names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com October 2007 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Additional Features • Single chip Ethernet controller with IEEE 802.3u support • 32 bit/33MHz PCI bus for different host processor interfaces • Dynamic buffer memory scheme – Essential for applications such as Video over IP where image jitter is unacceptable • Micrel LinkMD® cable diagnostic capabilities to determine cable length and distance to fault, and to diagnose faulty cables • Wake-on-LAN technology – Incorporates Magic Packet™, network link state, and wake-up frame technology • HP Auto MDIX crossover with disable and enable option • Enhanced power management feature with powerdown feature Features • Fully compliant with the IEEE802.3u standard • Supports 10/100BASE-T/TX • Supports IEEE 802.3x full-duplex flow control and halfduplex backpressure collision flow control • Supports burst data transfers • 8KB internal memory for RX/TX FIFO buffers • Early TX/RX functions to minimize latency through the device • Serial EEPROM configuration • Single 25MHz reference clock for both PHY and MAC Network Features • • • • • • • Fully integrated to comply with IEEE802.3u standards 10BASE-T and 100BASE-TX physical layer support Auto-negotiation: 10/100Mbps full and half duplex Supports IEEE 802.1Q multiple VLAN tagging On-chip wave shaping – No external filters required Adaptive equalizer Baseline wander correction Applications • • • • Video Distribution Systems High-end Cable, Satellite, and IP set-top boxes Video over IP Voice over IP (VoIP) and Analog Telephone Adapters (ATA) Power Modes, Packaging, and Power Supplies • Single power supply (3.3V) with 5V tolerant I/O buffers • Enhanced power management feature with power down feature to ensure low power dissipation during device idle periods • Comprehensive LED indicator support for link, activity, full/half duplex, and 10/100 speed (4 LEDs) • Low power CMOS design • Commercial Temperature Range: 0oC to +70oC • Industrial Temperature Range: –40oC to +85oC (KSZ8841-PMQLI) • Available in 128-pin PQFP Markets • Fast Ethernet • Embedded Ethernet • Industrial Ethernet Ordering Information Part Number KSZ8841-PMQL KSZ8841-PMQLI Junction Temp. Range 0oC to 70oC –40oC to +85oC Package 128-Pin PQFP 128-Pin PQFP October 2007 2 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Revision History Revision 1.0 1.1 1.2 1.3 1.4 1.5 Date 09/29/05 01/13/06 06/12/06 02/16/07 06/01/07 10/02/07 Summary of Changes Data sheet created. Used detail package information. Corrected MRFCE field for MDRXC register. The NC Pin 13 was changed from Ipu to –. The PWRDN Pin 36 was changed from I to Ipu. Update support transformer and other. Add the package thermal information in the operating ratings. In VDDCO pin description, add 100ohm resistor for internal LDO application. October 2007 3 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Contents Pin Configuration .............................................................................................................................................................. 8 Pin Description .................................................................................................................................................................. 9 Functional Description ................................................................................................................................................... 14 PCI Bus Interface Unit .................................................................................................................................................. 14 PCI Bus Interface ................................................................................................................................................. 14 TXDMA Logic and TX Buffer Manager ................................................................................................................ 14 RXDMA Logic and RX Buffer Manager................................................................................................................ 14 Power Management...................................................................................................................................................... 14 Power down.......................................................................................................................................................... 14 Wake-on-LAN....................................................................................................................................................... 14 Link Change ......................................................................................................................................................... 15 Wake-up Packet ................................................................................................................................................... 15 Magic Packet........................................................................................................................................................ 15 Physical Layer Transceiver (PHY) ................................................................................................................................. 16 100BASE-TX Transmit.................................................................................................................................................. 16 100BASE-TX Receive................................................................................................................................................... 16 PLL Clock Synthesizer (Recovery) ............................................................................................................................... 16 Scrambler/De-scrambler (100BASE-TX Only).............................................................................................................. 16 10BASE-T Transmit ...................................................................................................................................................... 16 10BASE-T Receive ....................................................................................................................................................... 16 MDI/MDI-X Auto Crossover .......................................................................................................................................... 17 Straight Cable....................................................................................................................................................... 17 Crossover Cable................................................................................................................................................... 18 Auto Negotiation ........................................................................................................................................................... 18 LinkMD Cable Diagnostics ............................................................................................................................................. 20 Access........................................................................................................................................................................... 20 Usage............................................................................................................................................................................ 20 Media Access Control (MAC) and other........................................................................................................................ 20 Inter Packet Gap (IPG) ................................................................................................................................................. 20 Back-Off Algorithm........................................................................................................................................................ 20 Late Collision ................................................................................................................................................................ 20 Flow Control.................................................................................................................................................................. 20 Half-Duplex Backpressure ............................................................................................................................................ 21 Clock Generator............................................................................................................................................................ 21 EEPROM Interface ....................................................................................................................................................... 21 Loopback Support......................................................................................................................................................... 23 Host Communication ...................................................................................................................................................... 24 Host Communication Descriptor Lists and Data Buffers .............................................................................................. 24 Receive Descriptors (RDES0-RDES3) ......................................................................................................................... 24 Transmit Descriptors (TDES0-TDES3)......................................................................................................................... 26 PCI Configuration Registers .......................................................................................................................................... 28 Configuration ID Register (CFID Offset 00H) ............................................................................................................... 29 Command and Status Configuration Register (CFCS Offset 04H)............................................................................... 29 Configuration Revision Register (CFRV Offset 08H).................................................................................................... 31 Configuration Latency Timer Register (CFLT Offset 0CH)........................................................................................... 31 Configuration Base Memory Address Register (CBMA Offset 10H) ............................................................................ 31 Subsystem ID Register (CSID Offset 2CH) .................................................................................................................. 32 Capabilities Pointer Register (CCAP Offset 34H)......................................................................................................... 32 Configuration Interrupt Register (CFIT Offset 3CH) ..................................................................................................... 32 Capabilities ID Register (CCID Offset 50H).................................................................................................................. 33 Power-Management Control and Status Register (CPMC Offset 54H)........................................................................ 35 PCI Control & Status Registers ..................................................................................................................................... 36 MAC DMA Transmit Control Register (MDTXC Offset 0x0000) ................................................................................... 36 MAC DMA Receive Control Register (MDRXC Offset 0x0004).................................................................................... 37 October 2007 4 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL MAC DMA Transmit Start Command Register (MDTSC Offset 0x0008) ..................................................................... 38 MAC DMA Receive Start Command Register (MDRSC Offset 0x000C) ..................................................................... 39 Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)...................................................................... 39 Receive Descriptor List Base Address Register (RDLB Offset 0x0014) ...................................................................... 39 MAC Multicast Table 0 Register (MTR0 Offset 0x0020) .............................................................................................. 39 MAC Multicast Table 1 Register (MTR1 Offset 0x0024) .............................................................................................. 40 Interrupt Enable Register (INTEN Offset 0x0028) ........................................................................................................ 40 Interrupt Status Register (INTST Offset 0x002C) ......................................................................................................... 41 MAC Additional Station Address Low Register (MAAL0-15) ........................................................................................ 42 MAC Additional Station Address High Register (MAAH0-15)....................................................................................... 42 MAC/PHY and Control Registers ................................................................................................................................... 43 MAC Address Register Low (0x0200): MARL .............................................................................................................. 43 MAC Address Register Middle (0x0202): MARM ......................................................................................................... 44 MAC Address Register High (0x0204): MARH ............................................................................................................. 44 On-Chip Bus Control Register (Offset 0x0210): OBCR................................................................................................ 44 EEPROM Control Register (Offset 0x0212): EEPCR................................................................................................... 44 Memory BIST Info Register (Offset 0x0214): MBIR ..................................................................................................... 45 Global Reset Register (Offset 0x0216): GRR............................................................................................................... 45 Power Management Capabilities Register (Offset 0x0218): PMCR ............................................................................. 46 Wakeup Frame Control Register (Offset 0x021A): WFCR ........................................................................................... 47 Wakeup Frame 0 CRC0 Register (Offset 0x0220): WF0CRC0.................................................................................... 48 Wakeup Frame 0 CRC1 Register (Offset 0x0222): WF0CRC1.................................................................................... 48 Wakeup Frame 0 Byte Mask 0 Register (Offset 0x0224): WF0BM0 ............................................................................ 48 Wakeup Frame 0 Byte Mask 1 Register (Offset 0x0226): WF0BM1 ............................................................................ 48 Wakeup Frame 0 Byte Mask 2 Register (Offset 0x0228): WF0BM2 ............................................................................ 48 Wakeup Frame 0 Byte Mask 3 Register (Offset 0x022A): WF0BM3 ........................................................................... 49 Wakeup Frame 1 CRC0 Register (Offset 0x0230): WF1CRC0.................................................................................... 49 Wakeup Frame 1 CRC1 Register (Offset 0x0232): WF1CRC1.................................................................................... 49 Wakeup Frame 1 Byte Mask 0 Register (Offset 0x0234): WF1BM0 ............................................................................ 49 Wakeup Frame 1 Byte Mask 1 Register (Offset 0x0236): WF1BM1 ............................................................................ 49 Wakeup Frame 1 Byte Mask 2 Register (Offset 0x0238): WF1BM2 ............................................................................ 50 Wakeup Frame 1 Byte Mask 3 Register (Offset 0x023A): WF1BM3 ........................................................................... 50 Wakeup Frame 2 CRC0 Register (Offset 0x0240): WF2CRC0.................................................................................... 50 Wakeup Frame 2 CRC1 Register (Offset 0x0242): WF2CRC1.................................................................................... 50 Wakeup Frame 2 Byte Mask 0 Register (Offset 0x0244): WF2BM0 ............................................................................ 50 Wakeup Frame 2 Byte Mask 1 Register (Offset 0x0246): WF2BM1 ............................................................................ 51 Wakeup Frame 2 Byte Mask 2 Register (Offset 0x0248): WF2BM2 ............................................................................ 51 Wakeup Frame 2 Byte Mask 3 Register (Offset 0x024A): WF2BM3 ........................................................................... 51 Wakeup Frame 3 CRC0 Register (Offset 0x0250): WF3CRC0.................................................................................... 51 Wakeup Frame 3 CRC1 Register (Offset 0x0252): WF3CRC1.................................................................................... 51 Wakeup Frame 3 Byte Mask 0 Register (Offset 0x0254): WF3BM0 ............................................................................ 52 Wakeup Frame 3 Byte Mask 1 Register (Offset 0x0256): WF3BM1 ............................................................................ 52 Wakeup Frame 3 Byte Mask 2 Register (Offset 0x0258): WF3BM2 ............................................................................ 52 Wakeup Frame 3 Byte Mask 3 Register (Offset 0x025A): WF3BM3 ........................................................................... 52 Chip ID and Enable Register (Offset 0x0400): CIDER ................................................................................................. 52 Chip Global Control Register (Offset 0x040A): CGCR ................................................................................................. 53 Indirect Access Control Register (Offset 0x04A0): IACR ............................................................................................. 53 Indirect Access Data Register 1 (Offset 0x04A2): IADR1 ............................................................................................ 54 Indirect Access Data Register 2 (Offset 0x04A4): IADR2 ............................................................................................ 54 Indirect Access Data Register 3 (Offset 0x04A6): IADR3 ............................................................................................ 54 Indirect Access Data Register 4 (Offset 0x04A8): IADR4 ............................................................................................ 54 Indirect Access Data Register 5 (Offset 0x04AA): IADR5 ............................................................................................ 54 Reserved (Offset 0x04C0-0x04CF) .............................................................................................................................. 54 PHY 1 MII Register Basic Control Register (Offset 0x04D0): P1MBCR ...................................................................... 55 PHY 1 MII Register Basic Status Register (Offset 0x04D2): P1MBSR ........................................................................ 56 5 October 2007 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL PHY 1 PHYID Low Register (Offset 0x04D4): PHY1ILR.............................................................................................. 56 PHY 1 PHYID High Register (Offset 0x04D6): PHY1IHR ............................................................................................ 57 PHY 1 Auto-Negotiation Advertisement Register (Offset 0x04D8): P1ANAR .............................................................. 57 PHY 1 Auto-Negotiation Link Partner Ability Register (Offset 0x04DA): P1ANLPR..................................................... 57 PHY1 LinkMD Control/Status (Offset 0x04F0): P1VCT................................................................................................ 58 PHY1 Special Control/Status Register (Offset 0x04F2): P1PHYCTRL........................................................................ 58 Reserved (Offset 0x04F8 - 0x04FA)............................................................................................................................. 59 Port 1 PHY Special Control/Status, LinkMD (Offset 0x0510): P1SCSLMD ................................................................. 59 Port 1 Control Register 4 (Offset 0x0512): P1CR4....................................................................................................... 60 Port 1 Status Register (Offset 0x0514): P1SR ............................................................................................................. 61 Reserved (Offset 0x0516 – 0x0560)............................................................................................................................. 62 MIB (Management Information Base) Counters........................................................................................................... 63 Example: MIB Counter Read (read “Rx64Octets” counter at indirect address offset 0x0E) ........................................ 64 Additional MIB Information............................................................................................................................................ 64 Absolute Maximum Ratings(1) ........................................................................................................................................ 65 Operating Ratings(2) ........................................................................................................................................................ 65 Electrical Characteristics(4) ............................................................................................................................................ 65 Timing Diagrams ............................................................................................................................................................. 67 EEPROM Timing........................................................................................................................................................... 67 Auto Negotiation Timing................................................................................................................................................ 68 Reset Timing................................................................................................................................................................. 69 Selection of Isolation Transformers.............................................................................................................................. 70 Selection of Reference Crystal ...................................................................................................................................... 70 Package Information ....................................................................................................................................................... 71 Acronyms and Glossary................................................................................................................................................. 72 October 2007 6 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL List of Figures Figure 1. KSZ8841-PMQL Function Diagram .................................................................................................................... 1 Figure 2. KSZ8841-PMQL 128-Pin PQFP (Top View)....................................................................................................... 8 Figure 3. Typical Straight Cable Connection ................................................................................................................... 17 Figure 4. Typical Crossover Cable Connection ............................................................................................................... 18 Figure 5. Auto Negotiation and Parallel Operation .......................................................................................................... 19 Figure 6. Port 1 Near-End (Remote) Loopback Path....................................................................................................... 23 Figure 7. EEPROM Read Cycle Timing Diagram ............................................................................................................ 67 Figure 8. Auto-Negotiation Timing ................................................................................................................................... 68 Figure 9. Reset Timing ..................................................................................................................................................... 69 Figure 10. 128-Pin PQFP Package.................................................................................................................................. 71 List of Tables Table 1. MDI/MDI-X Pin Definitions ................................................................................................................................. 17 Table 2. KSZ8841-PMQL EEPROM Format.................................................................................................................... 21 Table 3. KSZ8841-PMQL ConfigParam in EEPROM Format.......................................................................................... 23 Table 4. Format of Port MIB Counters ............................................................................................................................. 63 Table 5. Port 1’s MIB Counters Indirect Memory Offsets................................................................................................. 64 Table 6. EEPROM Timing Parameters ............................................................................................................................ 67 Table 7. Auto Negotiation Parameters ............................................................................................................................. 68 Table 8. Reset Timing Parameters .................................................................................................................................. 69 Table 9. Transformer Selection Criteria ........................................................................................................................... 70 Table 10. Qualified Single Port Magnetics........................................................................................................................ 70 Table 11. Typical Reference Crystal Characteristics ........................................................................................................ 70 October 2007 7 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Pin Configuration PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 VDDIO VDDC DGND PAD31 CBE0N CBE1N CBE2N CBE3N NC NC NC NC SERRN VDDIO DGND PERRN GNTN REQN DEVSELN IDSEL STOPN TRDYN IRDYN FRAMEN PAR RSTN X2 X1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PAD20 PAD19 PAD18 PAD17 DGND VDDIO PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 PAD3 DGND DGND VDDIO PAD2 PAD1 PAD0 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 KSZ8841-PMQL 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 AGND VDDAP AGND ISET NC NC AGND VDDA NC NC AGND NC NC VDDARX VDDATX TXM1 TXP1 AGND RXM1 RXP1 NC VDDA AGND NC NC AGND October 2007 TESTEN SCANEN P1LED2 P1LED1 P1LED0 NC NC NC DGND VDDIO NC PCLK NC PMEN NC INTRN NC NC EECS NC NC NC DGND VDDCO NC EEEN P1LED3 EEDO EESK EEDI NC VDDIO VDDIO DGND DGND PWRDN AGND VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Figure 2. KSZ8841-PMQL 128-Pin PQFP (Top View) 8 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Pin Description Pin Number 1 2 3 4 5 Pin Name TEST_EN SCAN_EN P1LED2 P1LED1 P1LED0 Type I I Opu Opu Opu Pin Function Test Enable For normal operation, pull-down this pin to ground. Scan Test Scan Mux Enable For normal operation, pull-down this pin to ground. Port 1 LED indicators1 defined as follows: LEDs turn on when low. Chip Global Control Register: CGCR bit [15,9] [0,0] Default P1LED3 2 [0,1] — 100Link/Act 10Link/Act Full duplex — Link/Act Full duplex/Col Speed P1LED2 P1LED1 P1LED0 Reg. CGCR bit [15,9] [1,0] P1LED3 2 [1,1] — — — — Act Link Full duplex/Col Speed P1LED2 P1LED1 P1LED0 Notes: 1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink; Full Duplex = On (Full duplex); Off (Half duplex) Speed = On (100BASE-T); Off (10BASE-T) 2. P1LED3 is pin 27. 6 7 8 9 10 11 12 NC NC NC DGND VDDIO NC PCLK — — — Gnd P — Ipd No connect No connect No connect Digital ground 3.3V digital I/O VDD No connect PCI Bus Clock This Clock provides the timing for all PCI bus phases. The rising edge defines the start of each phase. The clock maximum frequency is 33MHz. 13 14 NC PMEN — Opu No connect Power Management Enable Asserted low. When asserted, this signal indicates that a Wake-on-LAN packet has been received in this Ethernet MAC chip. 15 16 NC INTRN — Opd No connect Interrupt Request October 2007 9 M9999-100407-1.5 Micrel, Inc. Pin Number Pin Name Type Pin Function KSZ8841-PMQL Active Low signal to host CPU to request an interrupt when any one of the interrupt conditions occurs in the registers. This pin should be pull-up externally. 17 18 19 20 21 22 23 24 NC NC EECS NC NC NC DGND VDDCO — — Opu — — — Gnd P No connect No connect EEPROM Chip Select This signal is used to select an external EEPROM device No connect No connect No connect Digital Ground 1.2V Core Voltage Output. (Internal 1.2V LDO power supply output) This pin provides 1.2V power supply to all 1.2V power pin, VDDC, VDDA, VDDAP. It is recommended the pin should be connected to 3.3V power rail by a 100ohm resistor for the internal LDO application. No connect EEPROM Enable EEPROM is enabled and connected when this pin is pull-up. EEPROM is disabled when this pin is pull-down or no connect. 27 28 29 P1LED3 EEDO EESK Opd Opd Opd Port 1 LED Indicator See the description in pins 3, 4, and 5. EEPROM Data Out This pin is connected to DI input of the serial EEPROM. EEPROM Serial Clock 4µs serial clock to load configuration data from the serial EEPROM. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 EEDI NC VDDIO VDDIO DGND DGND PWRDN AGND VDDA AGND NC NC AGND VDDA NC Ipd — P P Gnd Gnd Ipu Gnd P Gnd — — Gnd P — EEPROM Data In This pin is connected to DO output of the serial EEPROM. No connect 3.3V digital I/O VDD. 3.3V digital I/O VDD. Digital ground Digital ground Full-chip power-down input. Active Low. Analog ground 1.2V analog VDD Analog ground No connect No connect Analog ground 1.2V analog VDD No connect 25 26 NC EEEN — Ipd October 2007 10 M9999-100407-1.5 Micrel, Inc. Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Pin Name RXP1 RXM1 AGND TXP1 TXM1 VDDATX VDDARX NC NC AGND NC NC VDDA AGND NC NC ISET AGND VDDAP AGND X1 X2 Type I/O I/O Gnd I/O I/O P P — — Gnd — — P Gnd — — O Gnd P Gnd I O Pin Function Physical receive (MDI) or transmit (MDIX)signal (+ differential) Physical receive (MDI) or transmit (MDIX) signal (– differential) Analog ground Physical transmit (MDI) or receive (MDIX) signal (+ differential) Physical transmit (MDI) or receive (MDIX) signal (– differential) 3.3V analog VDD 3.3V analog VDD No connect No connect Analog ground No connect No connect 1.2 analog VDD Analog ground No connect No connect Set physical transmit output current Pull-down this pin with a 3.01K 1% resistor to ground. Analog ground 1.2V analog VDD for PLL Analog ground 25MHz crystal/oscillator clock connections KSZ8841-PMQL Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is no connected. Note: Clock is 50ppm for both crystal and oscillator. Hardware Reset, Active Low RSTN will cause the KSZ8841-PMQL to reset all of its functional blocks. RSTN must be asserted for a minimum duration of 10 ms. 67 RSTN Ipu 68 PAR I/O PCI Parity Even parity computed for PAD[31:0] and CBE[3:0]N, master drives PAR for address and write data phase, target drives PAR for read data phase. 69 FRAMEN I/O PCI Cycle Frame This signal is asserted low to indicate the beginning of the address phase of the bus transaction and de-asserted before the final transfer of the data phase of the transaction in a bus master mode. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. 70 IRDYN I/O PCI Initiator Ready As a bus master, this signal is asserted low to indicate valid data phases on PAD[31:0] during write data phases, indicates it is ready to accept data during read data phases. As a target, it’ll monitor this IRDYN signal that indicates the master has put the data on the bus. 71 TRDYN I/O PCI Target Ready As a bus target, this signal is asserted low to indicate valid data phases on PAD[31:0] during read data phases, indicates it is ready to accept data during write data phases. As a master, it will monitor this TRDYN signal that indicates the target is ready for data October 2007 11 M9999-100407-1.5 Micrel, Inc. Pin Number 72 Pin Name STOPN Type Pin Function during read/write operation. I/O PCI Stop KSZ8841-PMQL This signal is asserted low by the target device to request the master device to stop the current transaction. 73 IDSEL I/O PCI Initialization Device Select This signal is used to select the KSZ8841-PMQL during configuration read and write transactions. Active high. 74 DEVSELN I/O PCI Device Select This signal is asserted low when it is selected as a target during a bus transaction. As a bus master, the KSZ8841-PMQL samples this signal to insure that a PCI target recognizes the destination address for the data transfer. 75 76 REQN GNTN O I PCI Bus Request The KSZ8841-PMQL will assert this signal low to request PCI bus master operation. PCI Bus Grant This signal is asserted low to indicate to the KSZ8841-PMQL that it has been granted the PCI bus master operation. 77 PERRN I/O PCI Parity Error The KSZ8841-PMQL as a master or target will assert this signal low to indicate a parity error on any incoming data. As a bus master, it will monitor this signal on all write operations. 78 79 80 DGND VDDIO SERRN Gnd P O Digital ground 3.3V digital I/O VDD PCI System Error This system error signal is asserted low by the KSZ8841-PMQL. This signal is used to report address parity errors. 81 82 83 84 85 86 87 88 89 NC NC NC NC CBE3N CBE2N CBE1N CBE0N PAD31 — — — — I/O I/O I/O I/O I/O No connect No connect No connect No connect Command and Byte Enable These signals are multiplexed on the same PCI pins. During the address phase, these lines define the bus command. During the data phase, these lines are used as Byte Enables, The Byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. PCI Address / Data 31 Address and data are multiplexed on the all of the PAD pins. The PAD pins carry the physical address during the first clock cycle of a transaction, and carry data during the subsequent clock cycles. 90 91 92 93 94 95 96 DGND VDDC VDDIO PAD30 PAD29 PAD28 PAD27 Gnd P P I/O I/O I/O I/O Digital core ground 1.2V digital core VDD 3.3V digital I/O VDD PCI Address / Data 30 PCI Address / Data 29 PCI Address / Data 28 PCI Address / Data 27 October 2007 12 M9999-100407-1.5 Micrel, Inc. Pin Number 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Notes: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipd = Input with internal pull-down. Ipu = Input with internal pull-up. Opd = Output with internal pull-down. Opu = Output with internal pull-up. KSZ8841-PMQL Pin Name PAD26 PAD25 PAD24 PAD23 PAD22 PAD21 PAD20 PAD19 PAD18 PAD17 DGND VDDIO PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 PAD3 DGND DGND VDDIO PAD2 PAD1 PAD0 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Gnd P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Gnd Gnd P I/O I/O I/O Pin Function PCI Address / Data 26 PCI Address / Data 25 PCI Address / Data 24 PCI Address / Data 23 PCI Address / Data 22 PCI Address / Data 21 PCI Address / Data 20 PCI Address / Data 19 PCI Address / Data 18 PCI Address / Data 17 Digital ground 3.3V digital I/O VDD PCI Address / Data 16 PCI Address / Data 15 PCI Address / Data 14 PCI Address / Data 13 PCI Address / Data 12 PCI Address / Data 11 PCI Address / Data 10 PCI Address / Data 9 PCI Address / Data 8 PCI Address / Data 7 PCI Address / Data 6 PCI Address / Data 5 PCI Address / Data 4 PCI Address / Data 3 Digital ground Digital core ground 3.3V digital I/O VDD PCI Address / Data 2 PCI Address / Data 1 PCI Address / Data 0 October 2007 13 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Functional Description The KSZ8841-PMQL is a single chip Fast Ethernet MAC controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a PCI interface unit that controls the KSZ8841-PMQL via a 32 bit/33MHz PCI processor interface. The KSZ8841-PMQL is fully compliant to the IEEE802.3u standard. PCI Bus Interface Unit PCI Bus Interface The PCI Bus Interface implements PCI v2.2 bus protocols and configuration space. The KSZ8841-PMQL supports bus master reads and writes to CPU memory, and CPU access to on-chip register space. When the CPU reads and writes the configuration registers of the KSZ8841-PMQL, it is as a slave. So the KSZ8841-PMQL can be either a PCI bus master or slave. The PCI Bus Interface is also responsible for managing the DMA interfaces and the host processors access. Arbitration logic within the PCI Bus Interface unit accepts bus requests from the TXDMA logic and RXDMA logic. The PCI bus interface also manages interrupt generation for a host processor. TXDMA Logic and TX Buffer Manager The KSZ8841-PMQL supports a multi-frame, multi-fragment DMA gather process. Descriptors representing frames are built and linked in system memory by a host processor. The TXDMA logic is responsible for transferring the multifragment frame data from the host memory into the TX buffer. The KSZ8841-PMQL uses 4K bytes of transmit data buffer between the TXDMA logic and transmit MAC. When the TXDMA logic determines there is enough space available in the TX buffer, the TXDMA logic will move any pending frame data into the TX buffer. The management mechanism depends on the transmit descriptor list. RXDMA Logic and RX Buffer Manager The KSZ8841-PMQL supports a multi-frame, multi-fragment DMA scatter process. Descriptors representing frames are built and linked in system memory by the host processor. The RXDMA logic is responsible for transferring the frame data from the RX buffer to the host memory. The KSZ8841-PMQL uses 4K bytes of receive data buffer between the receive MAC and RXDMA logic. The management mechanism depends on the receive descriptor list. Power Management Power down The KSZ8841-PMQL features a port power-down mode. To save power, the user can power-down this port that is not in use by setting bit 11 in either P1CR4 or P1MBCR register for this port. To bring the port back up, reset bit 11 in these registers. In addition, there is a full chip power-down mode by pulled-down the PWRDN pin 36. When this pin is pulled-down, the entire chip powers down. Transitioning this pin from pull-down to pull-up results in a power up and chip reset. Wake-on-LAN Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is pre-programmed by the policy owner or other software with information on how to identify wake frames from other network traffic. A wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state (working). October 2007 14 M9999-100407-1.5 Micrel, Inc. A wake-up signal is caused by: 1. Detection of a change in the network link state 2. Receipt of a network wake-up frame 3. Receipt of a Magic Packet KSZ8841-PMQL Link Change Link status wake events are useful to indicate a change in the network’s availability, especially when this change may impact the level at which the system should re-enter the sleeping state. For example, a change from link off to link on may trigger the system to re-enter sleep at a higher level (D2 versus D3) so that wake frames can be detected. Conversely, a transition from link on to link off may trigger the system to re-enter sleep at a deeper level (D3 versus D2) since the network is not currently available. Note: References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined for PCI. For more information, refer to the PCI specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf. Wake-up Packet Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame. The KSZ8841-PMQL supports up to four users defined wake-up frames as below: 1. Wake-up frame 0 is defined in registers 0x0220-0x022A and is enabled by bit 0 in wakeup frame control register. 2. Wake-up frame 1 is defined in registers 0x0230-0x023A and is enabled by bit 1 in wakeup frame control register. 3. Wake-up frame 2 is defined in registers 0x0240-0x024A and is enabled by bit 2 in wakeup frame control register. 4. Wake-up frame 3 is defined in registers 0x0250-0x025A and is enabled by bit 3 in wakeup frame control register Magic Packet Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the LAN controller receives a Magic Packet frame, it will alert the system to wake up. Magic Packet is a standard feature integrated into the KSZ8841-PMQL. The chip implements multiple advanced powerdown modes including Magic Packet to conserve power and operate more efficiently. Once the KSZ8841-PMQL has been put into Magic Packet Enable mode (WFCR[7]=1), it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the chip this is a Magic Packet (MP) frame. A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address (SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address and CRC. The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as 6 bytes of FFh. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match the address of the machine to be awakened. EXAMPLE If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scanning for the data sequence (assuming an Ethernet frame): DESTINATION SOURCE MISC: FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 - MISC -CRC. There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node at the frame’s destination If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the controller (KSZ8841-PMQL) detects the data sequence, however, it then alerts the PC’s power management circuitry (asserted the PMEN pin) to wake up the system. October 2007 15 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Physical Layer Transceiver (PHY) 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the 25MHz 4-bit nibbles into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 1% 3.01KΩ resistor for the 1:1 transformer ratio sets the output current. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASETX driver. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC. PLL Clock Synthesizer (Recovery) The internal PLL clock synthesizer generates 125MHz, 62.5MHz, 41.66MHz, and 25MHz clocks by setting the on-chip bus speed control register OBCR for KSZ8841-PMQL system timing. These internal clocks are generated from an external 25MHz crystal or oscillator. Note: Default setting is 25MHz in OBCR register, recommends the software driver to set it to 125MHz for best performance. Scrambler/De-scrambler (100BASE-TX Only) The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter. 10BASE-T Transmit The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetic. They are internally wave-shaped and pre-emphasized into outputs with typical 2.4V amplitude. The harmonic contents are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering October 2007 16 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8841-PMQL decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. MDI/MDI-X Auto Crossover To eliminate the need for crossover cables between similar devices, the KSZ8841-PMQL supports HP-Auto MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the KSZ8841-PMQL device. This feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers. The IEEE 802.3u standard MDI and MDI-X definitions are: MDI RJ45 Pins 1 2 3 6 Signals TD+ TDRD+ RDMDI-X RJ45 Pins 1 2 3 6 Signals RD+ RDTD+ TD- Table 1. MDI/MDI-X Pin Definitions Straight Cable A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. The following diagram shows a typical straight cable connection between a network interface card (NIC) (MDI) and a switch (MDIX) or a hub (MDI-X). Figure 3. Typical Straight Cable Connection October 2007 17 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). Figure 4. Typical Crossover Cable Connection Auto Negotiation The KSZ8841-PMQL conforms to the auto negotiation protocol as described by the 802.3 committee. Auto negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto negotiation, the link partners advertise capabilities across the link to each other. If auto negotiation is not supported or the link partner to the KSZ8841-PMQL is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The link setup is shown in the following flow diagram (Figure 3). October 2007 18 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Start Auto Negotiation Force Link Setting NO Parallel Operation YES Bypass Auto Negotiation and Set Link Mode ttempt Auto Negotiation Listen for 100BASE-TX Idles Listen for 10BASE-T Link Pulses Join Flow Link Mode Set ? NO YES Link Mode Set Figure 5. Auto Negotiation and Parallel Operation October 2007 19 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL LinkMD Cable Diagnostics The KSZ8841-PMQL LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of +/–2m. Access LinkMD is initiated by accessing register P1VCT, the LinkMD Control/Status register, in conjunction with register P1CR4, the 100BASE-TX PHY Controller register. Usage LinkMD can be run at any time. To use LinkMD, disable HP Auto-MDIX by writing a ‘1’ to P1CR4[10] to enable manual control over the pair used to transmit the LinkMD pulse. The self-clearing cable diagnostic test enable bit, P1VCT[15], is set to ‘1’ to start the test on this pair. When bit P1VCT[15] returns to ‘0’, the test is complete. The test result is returned in bits P1VCT[14-13] and the distance is returned in bits P1VCT[8-0]. The cable diagnostic test results are as follows: 00 = Valid test, normal condition 01 = Valid test, open circuit in cable 10 = Valid test, short circuit in cable 11 = Invalid test, LinkMD failed If P1VCT[14-13]=11 case, this indicates an invalid test, occurs when the KSZ8841-PMQL is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8841-PMQL to determine if the detected signal is a reflection of the signal generated or a signal from another source. Cable distance (in meters) can approximately be determined by the following formula: Distance = P1VCT[8-0] x 0.4m This constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. Media Access Control (MAC) and other The KSZ8841-PMQL strictly abides by IEEE 802.3 standards to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the minimum 96-bits time for IPG is between the two consecutive packets. If the current packet is experiencing collisions, the minimum 96-bits time for IPG is from carrier sense to the next transmit packet. Back-Off Algorithm The KSZ8841-PMQL implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After 16 collisions, the packet is dropped. Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. Flow Control The KSZ8841-PMQL supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KSZ8841-PMQL receives a pause control frame, the KSZ8841-PMQL will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it is flow controlled), only flow control packets from the KSZ8841-PMQL are transmitted. October 2007 20 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL On the transmit side, the KSZ8841-PMQL has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources. The KSZ8841-PMQL issues a flow control frame (XON), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KSZ8841-PMQL sends out another flow control frame (XOFF) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. Half-Duplex Backpressure A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as above in full-duplex mode. If backpressure is required, the KSZ8841-PMQL sends preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8841-PMQL discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further colliding and maintaining carrier sense to prevent packet reception. The backpressure will take effect automatically in Auto-negotiation enable and half-duplex mode. Clock Generator The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to the 3.3V 25MHz oscillator (as described in the pin description). EEPROM Interface An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the node address and subsystem ID. As part of the initialization after system reset, the KSZ8841-PMQL reads the external EEPROM and places the data into certain host-accessible registers if the EEEN pin is pulled-up, the KSZ8841-PMQL performs an automatic read of the EEPROM word from 0x0 to 0x6 after the de-assertion of Reset. An EEPROM of 1KB(93C46) or 4KB(93C66) can be used based on application. The EEPROM read/write function can also be performed by software reading and writing to the EEPCR register. The KSZ8841-PMQL EEPROM format is given in Table 2. WORD 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7-0x3F MAC Address Byte 2 MAC Address Byte 4 MAC Address Byte 6 Subsystem ID Subsystem Vendor ID ConfigParam Not used by KSZ8841-PMQL (available for user to use) Table 2. KSZ8841-PMQL EEPROM Format 15 8 7 MAC Address Byte 1 MAC Address Byte 3 MAC Address Byte 5 0 Reserved October 2007 21 M9999-100407-1.5 Micrel, Inc. The ConfigParam in the EEPROM format is shown below. Bit 15 Name NEW_CAP Description New Capabilities KSZ8841-PMQL Indicates whether or not the KSZ8841-PMQL implements a list of new capabilities. When set, this bit indicates the presence of New capabilities. When reset, New capabilities are not implemented. The value of this bit is loaded to the New_cap bit in CFCS register. 14 NO_SRST No Soft Reset When this bit is set, indicates that KSZ8841-PMQL transitioning from D3_hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3_hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. When this bit is clear, KSZ8841-PMQL performs an internal reset upon transitioning from D3_hot to D0 via software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3_hot to the D0 state, full reinitialization sequence is needed to return the device to D0 Initialized. Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled. This bit is loaded to bit 3 of CPMC register 13 12 Reserved PME_D2 PME -Support D2 When this bit is set, the KSZ8841-PMQL asserts PME event when the KSZ8841PMQL is in D2 state and PME_EN is set. Otherwise, the KSZ8841-PMQL does not assert PME event when the KSZ8841-PMQL is in D2 state. This bit is loaded to bit 13 of PMCR register, and bit 29 of CCID register. 11 PME_D1 PME Support D1 When this bit is set, the K8841P asserts PME event when the K8841P is in D1 state and PME_EN is set. Otherwise, the KSZ8841-PMQL does not assert PME event when the KSZ8841-PMQL is in D1 state. This bit is loaded to bit 12 of PMCR register, and bit 28 of CCID register. 10 D2_SUP D2 support When this bit is set, the KSZ8841-PMQL supports D2 power state. This bit is loaded to bit 10 of PMCR register, and bit 26 of CCID register. 9 D1_SUP D1 support When this bit is set, the KSZ8841-PMQL supports D1 power state. This bit is loaded to bit 9 of PMCR register, and bit 25 of CCID register. 8-6 5 Reserved DSI Device Specific Initialization This bit indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. A “1” indicates that the function requires a device specific initialization sequence following transition to the D0 uninitialized state. This bit is loaded to bit 5 of PMCR register and bit 21 of CCID register. 4 Reserved October 2007 22 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Bit 3 Name PME_CK Description PME Clock When this bit is a “1”, it indicates that the function relies on the presence of the PCI clock for PME# operation. When this bit is a “0”, it indicates that no PCI clock is required for the function to generate PME#. This bit is loaded to bit 3 of PMCR register and bit 19 of CCID register. 2-0 PCI: PME_VER PCI: Power Management PCI Version. These bits are loaded to bits [2-0] of the PMCR register and bits [18-16] of the CCID register. Table 3. KSZ8841-PMQL ConfigParam in EEPROM Format Loopback Support The KSZ8841-PMQL provides loopback support for remote diagnostic failure. In loopback mode, the speed at the PHY port will be set to 100BASE-TX full-duplex mode. The KSZ8841-PMQL only supports Near-end (Remote) Loopback. Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8841-PMQL. The loopback path starts at the PHY ports receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY ports transmit outputs (TXPx/TXMx). Bit [1] of register P1PHYCTRL is used to enable near-end loopback for port 1. Alternatively, Bit [9] of register P1SCSLMD can also be used to enable near-end loopback. The port’s near-end loopback path is illustrated in the following Figure 4. RXP1 / RXM1 PHY Port 1 Near-end (remote) Loopback TXP1 / TXM1 PMD1/PMA1 PCS1 MAC1 8K RX/TX Buffer RX/TX DMA PCI Bus I/F Unit Figure 6. Port 1 Near-End (Remote) Loopback Path October 2007 23 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Host Communication The descriptor lists and data buffers, collectively called the host communication, manage the actions and status related to buffer management. Commands and signals that control the functional operation of the KSZ8841-PMQL are also described. The KSZ8841-PMQL and the driver communicate through the two data structures: Command and status registers (CSRs) and Descriptor Lists and Data Buffers. Note: All unused bits of the data structure in this section are reserved and should be written by the driver as zeros. Host Communication Descriptor Lists and Data Buffers The KSZ8841-PMQL transfers received data frames to the receive buffer in host memory and transmits data from the transmit buffers in host memory. Descriptors that reside in the host memory act as pointers to these buffers. There are two descriptor lists (one for receive and one for transmit) for the MAC DMA. The base address of each list is written in the TDLB register and in the RDLB register, respectively. A descriptor list is forward linked. The last descriptor may point back to the first entry to create a ring structure. Descriptors are chained by setting the next address to the next buffer in both receive and transmit descriptors. The descriptor lists reside in the host physical memory address space. Each pointer points to one buffer and the second pointer points to the next descriptor. This enables the greatest flexibility for the host to chain any data buffers with discontinuous memory location. This eliminates processor-intensive tasks such as memory copying from the host to memory. A data buffer contains either an entire frame or part of a frame, but it cannot exceed a single frame. Buffers contain only data; and buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers. Data chaining can be enabled or disabled. Data buffers reside in host physical memory space. Receive Descriptors (RDES0-RDES3) Receive descriptor and buffer addresses must be Word aligned. Each receive descriptor provides one frame buffer, one byte count field, and control and status bits. The following table shows the RDES0 register bit fields. Bit 31 Description OWN Own Bit When set, indicates that the descriptor is owned by the KSZ8841-PMQL. When reset, indicates that the descriptor is owned by the host. The KSZ8841-PMQL clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full. 30 FS First Descriptor When set, indicates that this descriptor contains the first buffer of a frame. If the buffer size of the first buffer is 0, the next buffer contains the beginning of the frame. 29 28 LS Last Descriptor When set, indicates that the buffer pointed by this descriptor is the last buffer of the frame. IPE IP Checksum Error When set, indicates that the received frame is an IP packet and its IP checksum field does not match. This bit is valid only when last descriptor is set. 27 TCPE TCP Checksum Error When set, indicates that the received frame is a TCP/IP packet and its TCP checksum field does not match. This bit is valid only when last descriptor is set. October 2007 24 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Bit 26 Description UDPE UDP Checksum Error When set, indicates that the received frame is an UDP/IP packet and its UDP checksum field does not match. This bit is valid only when last descriptor is set. 25 ES Error Summary Indicates the logical OR of the following RDES0 bits: CRC error Frame too long Runt frame This bit is valid only when last descriptor is set. 24 MF Multicast Frame When set, indicates that this frame has a multicast address. This bit is valid only when last descriptor is set. 23 - 20 SPN Switch Engine Source Port Number This field indicates the source port where the packet originated. If bit 20 is set, it indicates the packet was received from port 1. If bit 21 is set, it indicates the packet was received from port 2. This field is valid only when the last descriptor is set. (Bits 23 and 22 are not used, but reserved for backward compatibility and future expansion.) 19 RE Report on MII Error When set, indicates that a receive error in the physical layer was reported during the frame reception. 18 TL Frame Too Long When set, indicates that the frame length exceeds the maximum size of 1518 bytes. This bit is valid only when last descriptor is set. Note: Frame too long is only a frame length indication and does not cause any frame truncation. 17 RF Runt Frame When set, indicates that this frame was damaged by a collision or premature termination before the collision window has passed. Runt frames are passed on to the host only if the pass bad frame bit is set. 16 CE CRC Error When set, indicates that a CRC error occurred on the received frame. This bit is valid only when last descriptor is set. 15 FT Frame Type When set, indicates that the frame is an Ethernet-type frame (frame length field is greater than 1500 bytes). When clear, indicates that the frame is an IEEE 802.3 frame. This bit is not valid for runt frames. This bit is valid only when last descriptor is set. 14 - 11 10 - 0 Reserved FL Frame Length Indicates the length, in bytes, of the received frame, including the CRC. This field is valid only when last descriptor is set and descriptor error is reset. October 2007 25 M9999-100407-1.5 Micrel, Inc. The following table shows the RDES1 register bit fields. Bit 31 - 26 25 Description Reserved RER Receive End of Ring KSZ8841-PMQL When set, indicates that the descriptor list reached its final descriptor. The KSZ8841-PMQL returns to the base address of the list, thus creating a descriptor ring. 24 - 12 10 - 0 Reserved RBS Receive Buffer Size Indicates the size, in bytes, of the receive data buffer. If the field is 0, the KSZ8841-PMQL ignores this buffer and moves to the next descriptor. The buffer size must be a multiple of 4. The following table shows the RDES2 register bit fields. Bit 31 - 0 Description Buffer Address Indicates the physical memory address of the buffer. The buffer address must be Word aligned. The following table shows the RDES3 register bit fields. Bit 31 - 0 Description Next Descriptor Address Indicates the physical memory address of the next descriptor in the descriptor ring. The buffer address must be Word aligned. Transmit Descriptors (TDES0-TDES3) Transmit descriptors must be Word aligned. Each descriptor provides one frame buffer, one byte count field, and control and status bits. The following table shows the TDES0 register bit fields. Bit 31 Description OWN Own Bit When set, indicates that the descriptor is owned by the KSZ8841-PMQL. When cleared, indicates that the descriptor is owned by the host. The KSZ8841-PMQL clears this bit either when it completes the frame transmission or when the buffer allocated in the descriptor is empty. The ownership bit of the first descriptor of the frame should be set after all subsequent descriptors belonging to the same frame have been set. This avoids a possible race condition between the KSZ8841-PMQL fetching a descriptor and the driver setting an ownership bit. 30 - 0 Reserved The following table shows the TDES1 register bit fields. Bit 31 Description IC Interrupt on Completion When set, the KSZ8841-PMQL sets transmit interrupt after the present frame has been transmitted. It is valid only when last segment is set. 30 FS First Segment When set, indicates that the buffer contains the first segment of a frame. October 2007 26 M9999-100407-1.5 Micrel, Inc. Bit 29 28 Description LS Last Segment When set, indicates that the buffer contains the last segment of a frame. IPCKG IP Checksum Generate KSZ8841-PMQL When set, the KSZ8841-PMQL will generate correct IP checksum for outgoing frames that contains IP protocol header. The KSZ8841-PMQL supports only a standard IP header, i.e., IP with a 20 byte header. When this feature is used, ADD CRC bit in the transmit mode register should always be set. This bit is used as a per-packet control when the IP checksum generate bit in the transmit mode register is not set. This bit should be always set for multiple-segment packets. 27 TCPCKG TCP Checksum Generate When set, the KSZ8841-PMQL will generate correct TCP checksum for outgoing frames that contains IP and TCP protocol header. The KSZ8841-PMQL supports only a standard IP header, i.e., IP with a 20 byte header. When this feature is used, ADD CRC bit in the transmit mode register should always be set. This bit is used as a per-packet control when the TCP checksum generate bit in the transmit mode register is not set. This bit should be always set for multiple-segment packets. 26 UDPCKG UDP Checksum Generate When set, the KSZ8841-PMQL will generate correct UDP checksum for outgoing frames that contains an IP and UDP protocol header. The KSZ8841-PMQL supports only a standard IP header, i.e., IP with a 20 byte header. When this feature is used, ADD CRC bit in the transmit mode register should always be set. This bit is used as a per-packet control when the UDP checksum generate bit in the transmit mode register is not set. 25 TER Transmit End of Ring When set, indicates that the descriptor pointer has reached its final descriptor. The KSZ8841-PMQL returns to the base address of the list, forming a descriptor ring. 24 23 – 20 Reserved SPN Switch Engine Destination Port Map When set, this field indicates the destination port(s) where the packet will be forwarded to. If bit 20 is set, it indicates the packet was received from port 1. If bit 21 is set, it indicates the packet was received from port 2. Setting all ports to 1 will cause the controller engine to broadcast the packet. Setting all bits to 0 has no effect. The controller engine forwards the packet according to its internal controller lookup algorithm. This field is valid only when the last descriptor is set. (Bits 23 and 22 are not used, but reserved for backward compatibility and future expansion.) 19 - 11 10 - 0 Reserved TBS Transmit Buffer Size Indicates the size, in bytes, of the transmit data buffer. If this field is 0, the KSZ8841-PMQL ignores this buffer and moves to the next descriptor. October 2007 27 M9999-100407-1.5 Micrel, Inc. The following table shows the TDES2 register bit fields. Bit 31 - 0 Description Buffer Address Indicates the physical memory address of the buffer. There is no limitation on the transmit buffer address alignment. The following table shows the TDES3 register bit fields. Bit 31 - 0 Description Next Descriptor Address Indicates the physical memory address of the next descriptor in the descriptor ring. The buffer address must be Word aligned. KSZ8841-PMQL PCI Configuration Registers The KSZ8841-PMQL implements 12 configuration registers. These registers are described in the following subsections. The KSZ8841-PMQL enables a full software-driven initialization and configuration. This allows the software to identify and query the KSZ8841-PMQL. The KSZ8841-PMQL treats configuration space write operations to registers that are reserved as no-ops. That is, the access completes normally on the bus and the data is discarded. Read accesses, to reserved or unimplemented registers, complete normally and a data value of 0 is returned. Software reset has no effect on the configuration registers. Hardware reset sets the configuration registers to their default values. Configuration Register Identification Command and Status Revision Latency Timer Base Memory Address Reserved Subsystem ID Capabilities Pointer Reserved Interrupt Reserved Capability ID Power Management Control and Status Identifier CFID CFCS CFRV CFLT CBMA – CSID CCAP – CFIT – CCID CPMC I/O Address Offset 0x00 0x04 0x08 0x0C 0x10 0x14-28 0x2C 0x34 0x38 0x3C 0x40-4C 0x50 0x54 Default 0x884116C6 0x02*00000 0x02000010 0x00000000 0x00000000 0x00000000 0x******** 0x******** 0x00000000 0x28140100 0x00000000 0x***20001 0x00000000 October 2007 28 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Configuration ID Register (CFID Offset 00H) The CFID register identifies the KSZ8841-PMQL. The following table shows the CFID register bit fields. Bit 31 - 16 15 - 0 Default 0x8841 0x16C6 Description Device ID Vendor ID Specifies the manufacturer of the KSZ8841-PMQL. The following table shows the access rules of the register. Category Value after hardware reset Write access rules Description 0x884116C6 Write has no effect on the KSZ8841-PMQL. Command and Status Configuration Register (CFCS Offset 04H) The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]). The command register provides control of the KSZ8841-PMQL’s ability to generate and respond to PCI cycles. When 0 is written to this register, the KSZ8841-PMQL logically disconnects from the PCI bus for all accesses except configuration accesses. The status register records status information for the PCI bus-related events. The CFCS status bits are not cleared when they are read. Writing 1 to these bits clears them; writing 0 has no effect. The following table describes the CFCS register bit fields. Bit 31 Type Status Default 0 Description Detected Parity Error When set, indicates that the KSZ8841-PMQL detected a parity error, even if parity error handling is disabled in parity error response (CFCS[6]). 30 Status 0 Signal System Error When set, indicates that the KSZ8841-PMQL asserted the system error SERR_N pin. 29 Status 0 Received Master Abort When set, indicates that the KSZ8841-PMQL terminated a master transaction with master abort. 28 Status 0 Received Target Abort When set, indicates that the KSZ8841-PMQL master transaction was terminated due to a target abort. 27 Status 0 Target Abort This bit is set by KSZ8841-PMQL whenever it terminates with a Target Abort. The CSR registers are all 32-bit Little Endian format. For PCI register Read cycles, the KSZ8841-PMQL allows any different combination of CBEN. For PCI register bus cycles, only byte, word (16-bit), or Dword (32-bit) accesses are allowed. Any other combination is illegal and is target aborted. 26 - 25 Status 01 Device Select Timing Indicates the timing of the assertion of device select(DEVSEL_N). These bits are fixed at 01, which indicates a medium assertion of DEVSEL_N. October 2007 29 M9999-100407-1.5 Micrel, Inc. Bit 24 Type Status Default 0 Description Data Parity Report This bit is set when the following conditions are met: KSZ8841-PMQL The KSZ8841-PMQL asserts parity error PERR_N or it senses the assertion of PERR_N by another device. The KSZ8841-PMQL operates as a bus master for the operation that caused the error. Parity error response (CFCS[6]) is set. 23 - 22 21 20 Reserved Status Status 00 0 Reserved 66MHz Capable 0 = Not 66MHz capable New Capability Indicates whether or not the KSZ8841-PMQL implements a list of new capabilities. When set, this bit indicates the presence of New capabilities. When reset, New capabilities are not implemented. The value of this bit is loaded from the New_Cap bit in EEPROM. 19 - 9 8 Reserved Command 0x000 0 Reserved System Error Enable When set, the KSZ8841-PMQL asserts system error (SERR_N) when it detects a parity error on the address phase. 7 6 Reserved Command 0 0 Reserved Parity Error Response When set, the KSZ8841-PMQL asserts fatal bus error after it detects a parity error. When reset, any detected parity error is ignored and the KSZ8841-PMQL continues normal operation. Parity checking is disabled after hardware reset. 5-3 2 Reserved Command 000 0 Reserved Master Operation When set, the KSZ8841-PMQL is capable of acting as a bus master. When reset, the KSZ8841-PMQL capability to generate PCI accesses is disabled. For normal operation, this bit must be set. 1 Command 0 Memory Space Access When set, the KSZ8841-PMQL responds to memory space accesses. When reset, the KSZ8841-PMQL does not respond to memory space accesses. 0 Reserved 0 Reserved October 2007 30 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Configuration Revision Register (CFRV Offset 08H) The CFRV register contains the KSZ8841-PMQL revision number. The following table shows the CFRV register bit fields. Bit 31 - 24 23 - 16 15 - 8 7-4 Default 0x02 0x00 0x00 0x1 Description Base Class Indicates the network controller, and is equal to 0x2. Subclass Indicates the Fast/Gigabit Ethernet chip, and is equal to 0x00. Reserved Revision Number Indicates the KSZ8841-PMQL revision number, and is equal to 0x1. This number is incremented for subsequent revision. 3-0 0x0 Step Number Indicates the KSZ8841-PMQL step number, and is equal to 0x0 (chip revision A). This number is incremented for subsequent KSZ8841-PMQL steps within the current revision. Configuration Latency Timer Register (CFLT Offset 0CH) This register configures the cache line size field and the latency timer. The following table shows the CFLT register bit fields. Bit 31 - 16 15 - 8 Default 0x00 0x00 Description Reserved Configuration Latency Timer Specifies, in units of PCI bus clocks, the value of the latency timer of the KSZ8841-PMQL. When the KSZ8841-PMQL asserts FRAME_N, it enables its latency timer to count. If the KSZ8841-PMQL deserts FRAME_N prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the KSZ8841-PMQL initiates transaction termination as soon as its GNT_N is deserted. 7-0 0x00 Cache Line Size Specifies, in unit of 32-bit words(Dword), the system cache line size. Configuration Base Memory Address Register (CBMA Offset 10H) The CBMA register specifies the base memory address for accessing the KSZ8841-PMQL CSRs. This register must be initialized prior to accessing any CSR with memory access. The following table shows the CBMA register bit fields. Bit 31 - 11 Default 0 Description Configuration Base Memory Address Defines the base address assigned for mapping the KSZ8841-PMQL CSRs. 10 - 1 0 0 0 This field value is 0 when read. Memory Space Indicator Determines that the register maps into the Memory space. The value in this field is 0. This is a read-only field. October 2007 31 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Subsystem ID Register (CSID Offset 2CH) The CSID register is a read-only 32-bit register. The content of the CSID is loaded from the EEPROM after hardware reset. The loading period lasts at least 27,400 PCI cycles when the system is in 33MHz mode, and starts 50 cycles after hardware reset desertion. If the host accesses the CSID before its content is loaded from the EEPROM, the KSZ8841-PMQL responds with retry termination on the PCI bus. The following table shows the CSID register bit fields. Bit 31 - 16 15 - 0 Description Subsystem ID Indicates a 16-bit field containing the subsystem ID. Subsystem Vendor ID Indicates a 16-bit field containing the subsystem vendor ID. The following table shows the access rules of the register. Category Value after hardware reset Write access rules Description Read from EEPROM. Write has no effect on the KSZ8841-PMQL. Capabilities Pointer Register (CCAP Offset 34H) The CCAP register points to the base address of the power management register block in the configuration address space. This pointer is valid only if the new capability bit in CFCS is set. The following table shows the CCAP register bit fields. Bit 31 - 8 7-0 Default 0x000000 -Description Reserved Capabilities Pointer Points to the location of the power management register block in the PCI configuration space. The value of this field is determined by the New Capabilities bit 15 in the EEPROM. If this bit is set, the value of this field is 0x50, which stands for Support Power Management. Otherwise, this field is read as 0x00. Configuration Interrupt Register (CFIT Offset 3CH) The CFIT register is divided into two sections: the interrupt line and the interrupt pin. CFIT configures both the system’s interrupt and the KSZ8841-PMQL interrupt pin connection. The following table shows the CFIT register bit fields. Bit 31 - 24 Default 0x28 Description MAX_LAT This field indicates how often the device needs to gain access to the PCI bus. Time unit is equal to 0.25 us, assuming a PCI clock frequency of 33 MHz. The value after a hardware reset is 0x28 (10 us). 23 - 16 0x14 MIN_GNT This field indicates the burst period length that the device needs. Time unit is equal to 0.25us, assuming a PCI clock frequency of 33 MHz. The value after a hardware reset is 0x14 (5 us). 15 - 8 0x01 Interrupt Pin Indicates which interrupt pin that the KSZ8841-PMQL uses. The KSZ8841PMQL uses INTA# and the read value is 0x01. 7-0 0x00 Interrupt Line October 2007 32 M9999-100407-1.5 Micrel, Inc. Bit Default Description KSZ8841-PMQL Provides interrupt line routing information. The basic input/output system (BIOS) writes the routing information into to this field when it initialized and configures the system. The value in this field indicates which input of the system interrupt controller is connected to the K8841P’s interrupt pin. The driver can use this information to determine priority and vector information. Values in this field are system architecture specific. The following table shows the access rules of the register. Category Value after hardware reset Description 0x281401XX Capabilities ID Register (CCID Offset 50H) The CCID register is a read-only register that provides information on the KSZ8841-PMQL power management capabilities. The following table shows the CCID register bit fields. The CCID register bits [31-16] are mirrored with PMCR register bits [15-0]. Bit 31 Default 0 Description PME Support D3 (cold) If this bit is set, the KSZ8841-PMQL asserts PME in D3(cold) power state. Otherwise, the KSZ8841-PMQL does not assert PME in D3(cold). The value of this bit is loaded from the PME_D3_cold bit in the EEPROM. 30 1 PME Support D3 (hot) The value of this bit is 1, indicating that the KSZ8841-PMQL may assert PME in D3(hot) power state. 29 0 PME Support D2 If this bit is set, the KSZ8841-PMQL asserts PME in D2 power state. Otherwise, the KSZ8841-PMQL does not assert PME in D2 state. The value of this bit is loaded from the PME_D2 bit in the EEPROM. 28 0 PME Support D1 If this bit is set, the KSZ8841-PMQL asserts PME in D1 power state. Otherwise, the KSZ8841-PMQL does not assert PME in D1 state. The value of this bit loaded from the PME_D1 bit in the EEPROM. 27 0 PME Support D01 The value of this bit is 0, indicating that the KSZ8841-PMQL does not assert PME in D0 power state. 26 0 D2 Support If this bit is set, it indicates that the KSZ8841-PMQL support D2 power state. The value of this bit is loaded from the D2_SUP bit in the EEPROM. References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined for PCI. For more information, refer to the PCI specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf. 1 October 2007 33 M9999-100407-1.5 Micrel, Inc. Bit 25 Default 0 Description D1 Support KSZ8841-PMQL If this bit is set, it indicates that the KSZ8841-PMQL support D1 power state. The value of this bit loaded from the D1_SUP bit in the EEPROM. 24 - 22 000 Auxiliary Current This 3-bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. If PME# generation from D3_cold is not supported by the function, this field must return a value of 000 when read. 21 0 Device Specific Initialization Indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. Note that this bit is not used by some operating systems. Microsoft Windows and Windows NT, for instance, do not use this bit to determine whether to use D3. Instead, they use the driver’s capabilities to determine this. A “1” indicates that the function requires a device specific initialization sequence following transition to the D0 uninitialization state. The value of this bit is loaded from the PME_DSI bit in the EEPROM. 20 19 0 0 Reserved Should be set to 0. PME Clock When this bit is a “1”, it indicates that the function relies on the presence of the PCI clock for PME# operation. When this bit is a “0”, it indicates that no PCI clock is required for the function to generate PME#. The value of this bit is loaded from the PME_CK bit in the EEPROM. 18 - 16 0 Power Management PCI Version The value of this bit is loaded from the PME_VER[2:0] bits in the EEPROM. 15 - 8 0x00 Next Item Pointer Points to the location of the next block of the capabilities list in the PCI Configuration Space. The value of this field is 0x00, indicating that this is the last item of the Capability linked list. 7-0 0x01 Capabilities ID PCI Power Management Registers ID. The value of this field is 01h, indicating that this is the power-management register block. The following table shows the access rules of the register. Category Value after hardware reset Write access rules Description 0x40000001 & EEPROM Write has no effect on the KSZ8841-PMQL October 2007 34 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Power-Management Control and Status Register (CPMC Offset 54H) The CMPC register is a power-management control and status register. This register can control and sate power management events. The following table shows the CMPC register bit fields. Bit 31 - 16 15 Default 0x0000 0 Description Reserved PME_Status This bit indicates that the KSZ8841-PMQL has detected a powermanagement event. If bit PME_Enable is set, the KSZ8841-PMQL also asserts the PME_N pin. This bit is cleared on power-up reset or by write 1. It is not modified by either hardware or software reset. When this bit is cleared, the KSZ8841-PMQL deserts the PME_N pin. 14 - 9 8 0x00 0 Reserved PME_Enable If this bit is set, the KSZ8841-PMQL can assert the PME_N pin. Otherwise, assertion of the PME_N pin is disabled. This bit is cleared on power-up reset only and is not modified by either hardware or software reset. 7-4 3 0x0 0 Reserved No Soft Reset If this bit is set (“1”), the KSZ8841-PMQL does not perform an internal reset when transitioning from D3_hot to D0 because of PowerState commands. Configuration context is preserved. Upon transition from D3_hot to the D0 Initialized state, no additional operating system intervention is required to preserve configuration context beyond writing the PowerState bits. If this bit is cleared (“0”), the KSZ8841-PMQL does perform an internal reset when transitioning from D3_hot to D0 via software control of the PowerState bits. Configuration context is lost when performing the soft reset. Upon transition from D3_hot to the D0 state, full reinitialization sequence is needed to return the device to D0 Initialized. Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled. 2 1-0 0 00 Reserved Power State This field is used to set the current power state of the KSZ8841-PMQL and to determine its power state. The definitions of the field values are: 0: D0 1: D1 2: D2 3: D3(hot) This field gets a value of 0 after power up. October 2007 35 M9999-100407-1.5 Micrel, Inc. The following table shows the access rules of the register. Category bit 15 bit 8 bit 3 bit 1 – 0 Description Read/Write 1 Clear (RW1C) Read/Write (RW) Read Only (RO) Read Write (RW) KSZ8841-PMQL PCI Control & Status Registers The PCI CSR registers are all 32 bit in Little Endian format. For PCI register Read cycle, the KSZ8841-PMQL allows any different combination of CBEN. For PCI register bus cycles, only byte, word(16-bit), or Dword(32-bit) accesses are allowed. Any other combinations are illegal, and will be target aborted. All other registers not included below are reserved. MAC DMA Transmit Control Register (MDTXC Offset 0x0000) The MAC DMA transmit control register establishes the transmit operating modes and commands for the port. This register should be one of the last CSRs to be written as part of the transmit initialization. The following table shows the register bit fields. Bit 31-30 29 - 24 Default 0x00 Read/ Write RO RW Reserved MTBS DMA Transmit Burst Size This field indicates the maximum number of words to be transferred in one DMA transaction. If reset, the MAC DMA burst size is limited only by the amount of data stored in the transmit buffer before issuing a bus request. The MTBS can be programmed with permissible values 0,1, 2, 4, 8, 16, or 32. After reset, the MTBS default is 0, i.e. unlimited. 23 - 19 18 0x00 0 RO RW Reserved MTUCG MAC Transmit UDP Checksum Generate When set, the KSZ8841-PMQL will generate correct UDP checksum for outgoing UDP/IP frames at port. When this bit is set, ADD CRC should also turn on. 17 0 RW MTTCG MAC Transmit TCP Checksum Generate When set, the KSZ8841-PMQL will generate correct TCP checksum for outgoing TCP/IP frames at port. When this bit is set, ADD CRC should also turn on. 16 0 RW MTICG MAC Transmit IP Checksum Generate When set, the KSZ8841-PMQL will generate correct IP checksum for outgoing IP frames at port. When this bit is set, ADD CRC should also turn on. 15 - 10 9 0x00 0 RO RW Reserved MTFCE MAC Transmit Flow Control Enable When this bit is set and the KSZ8841-PMQL is in Full Duplex mode, flow control is enabled and the KSZ8841-PMQL will transmit a PAUSE frame when the Receive Buffer capacity has reached a level that may cause the buffer to overflow. When this bit is set and the KSZ8841-PMQL is in Half Duplex mode, backDescription October 2007 36 M9999-100407-1.5 Micrel, Inc. Bit Default Read/ Write Description KSZ8841-PMQL pressure flow control is enabled. When this bit is cleared, no transmit flow control is enabled. 8-3 2 0x0 0 RO RW Reserved MTEP MAC DMA Transmit Enable Padding When set, the KSZ8841-PMQL automatically adds a padding field to a packet shorter than 64 bytes. Note: Setting this bit automatically enables Add CRC feature. 1 0 RW MTAC MAC DMA Transmit Add CRC When set, the KSZ8841-PMQL appends the CRC to the end of the transmission frame. 0 0 RW MTE MAC DMA TX Enable When the bit is set, the MDMA TX block is enabled and placed in a running state. When reset, the transmission process is placed in the stopped state after completing the transmission of the current frame. The stop transmission command is effective only when the transmission process is in the running state. MAC DMA Receive Control Register (MDRXC Offset 0x0004) The MAC DMA receive control register establishes the receive operating modes and commands for the port. This register should be one of the last CSRs to be written as part of the receive initialization. The following table shows the register bit fields. Bit 31 - 30 29 - 24 Default 00 0x00 Read/ Write RO RW Reserved MRBS DMA Receive Burst Size This field indicates the maximum number of words to be transferred in one DMA transaction. If reset, the MAC DMA burst size is limited only by the amount of data stored in the receive buffer before issuing a bus request. The MRBS can be programmed with permissible values 0,1, 2, 4, 8, 16, or 32. After reset, the MRBS default is 0, i.e. unlimited. 23 - 20 19 0x0 0 RO RW Reserved IP Header Alignment Enable 1 = Enable alignment of IP header to dWord address. Layer 2 header will not be dWord aligned anymore. Please look at RX descriptor 0 for the Layer 2 header address shift. 0 = IP Header alignment disabled. 18 0 RW MRUCC MAC Receive UDP Checksum Check When set, the KSZ8841-PMQL will check for correct UDP checksum for incoming UDP/IP frames at port. Packets received with incorrect UDP checksum will be discarded. 17 0 RW MRTCG MAC Receive TCP Checksum Check When set, the KSZ8841-PMQL will check for correct TCP checksum for incoming TCP/IP frames at port. Packets received with incorrect TCP checksum will be discarded. 16 0 RW MRICG MAC Receive IP Checksum Check When set, the KSZ8841-PMQL will check for correct IP checksum for Description October 2007 37 M9999-100407-1.5 Micrel, Inc. Bit Default Read/ Write Description KSZ8841-PMQL incoming IP frames at port. Packets received with incorrect IP checksum will be discarded. 15 - 10 9 0x00 0 RO RW Reserved MRFCE MAC Receive Flow Control Enable When this bit is set and the KSZ8841-PMQL is in Full Duplex mode, flow control is enabled and the KSZ8841-PMQL will acknowledge a PAUSE frame from MAC of the controller, the outgoing packets will be pending in the transmit buffer until the PAUSE control timer expires. This field has no meaning in half-duplex mode and should be programmed to 0. When this bit is cleared, no flow control is enabled. 8-7 6 5 4 00 0 0 0 RO RW RW RW Reserved MRB MAC Receive Broadcast When set, the MAC receive all broadcast frames. MRM MAC Receive Multicast When set, the MAC receive all multicast frames (including broadcast). MRU MAC Receive Unicast When set, the MAC receive unicast frames that match the 48-bit Station Address of the MAC. 3 0 RW MRE MAC DMA Receive Error Frame When set, the KSZ8841-PMQL will pass the errors frames received to the host. Error frames include runt frames, oversized frames, CRC errors. 2 0 RW MRA MAC DMA Receive All When set, the KSZ8841-PMQL receives all incoming frames, regardless of its destination address. 1 0 RW DMA Receive Multicast Hash-Table Enable Setting this bit enables the RX function to receive multicast frames that pass the CRC Hash filtering mechanism. 0 0 RW MRE MAC DMA RX Enable When the bit is set, the DMA RX block is enabled and placed in a running state. When reset, the receive process is placed in the stopped state after completing the reception of the current frame. The stop transmission command is effective only when the reception process is in the running state. MAC DMA Transmit Start Command Register (MDTSC Offset 0x0008) This register is written by the CPU when packets in the data buffer need to be transmitted. The following table shows the register bit fields. Bit 31 - 0 Default 0x00000000 Read/ Write WO WTSC Transmit Start Command When written with any value, the Transmit DMA checks for frames to be transmitted. If no descriptor is available, the transmit process returns to suspended state. If descriptiors are available, the transmit process starts or resumes. This bit is self-clearing. Description October 2007 38 M9999-100407-1.5 Micrel, Inc. MAC DMA Receive Start Command Register (MDRSC Offset 0x000C) This register is written by the CPU when there are frame data in receive buffer to be processed. The following table shows the register bit fields. Bit 31 - 0 Default \ 0x00000000 Read/ Write WO WRSC Receive Start Command Description KSZ8841-PMQL When written with any value, the Receive DMA checks for descriptors to be acquired. If no descriptor is available, the receive process returns to suspended state and wait for the next receive restart command. If descriptors are available, the receive process resumes. This bit is selfclearing. Transmit Descriptor List Base Address Register (TDLB Offset 0x0010) This register is used for Transmit descriptor list base address register. The register is used to point to the start of the appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state. When stopped, the register must be written before the respective START command is given. Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not wordaligned. The following table shows the register bit fields. Bit 31 - 0 Default 0x00000000 Read/ Write RW WSTL Start of Transmit List Note: Write can only occur when the transmit process stopped. Description Receive Descriptor List Base Address Register (RDLB Offset 0x0014) This register is used for Receive descriptor list base address register. The register is used to point to the start of the appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state. When stopped, the register must be written before the respective START command is given. Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not wordaligned. The following table shows the register bit fields. Bit 31 - 0 Default 0x00000000 Read/ Write RW WSRL Start of Receive List Note: Write can only occur when the transmit process stopped. Description MAC Multicast Table 0 Register (MTR0 Offset 0x0020) The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the register. Bit 31-0 Default 0x00000000 Read/ Write RW MTR0 Multicast Table 0 When appropriate bit is set, the packet received with DA matches the CRC hashing function is received without being filtered. Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR then all multicast addresses are received regardless of the multicast table value. Description October 2007 39 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL MAC Multicast Table 1 Register (MTR1 Offset 0x0024) The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the register. Bit 31-0 Default 0x00000000 Read/ Write RW MTR0 Multicast Table 1 When appropriate bit is set, the packet received with DA matches the CRC hashing function is received without being filtered. Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR then all multicast addresses are received regardless of the multicast table value. Description Interrupt Enable Register (INTEN Offset 0x0028) This register enables the interrupts from the internal or external sources. The following table shows the register bit fields. Bit 31 Default 0 Read/ Write RW DMLCIE DMA MAC Link Changed Interrupt Enable When this bit is set, the DMA MAC Link Changed Interrupt is enabled. When this bit is reset, the DMA MAC Link Changed Interrupt is disabled. 30 0 RW DMTIE DMA MAC Transmit Interrupt Enable When this bit is set, the DMA MAC Transmit Interrupt is enabled. When this bit is reset, the DMA MAC Transmit Interrupt is disabled. 29 0 RW DMRIE DMA MAC Receive Interrupt Enable When this bit is set, the DMA MAC Receive Interrupt is enabled. When this bit is reset, the DMA MAC Receive Interrupt is disabled. 28 0 RW DMTBUIE DMA MAC Transmit Buffer Unavailable Interrupt Enable When this bit is set, the DMA MAC Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the DMA MAC Transmit Buffer Unavailable Interrupt is disabled. 27 0 RW DMRBUIE DMA MAC Receive Buffer Unavailable Interrupt Enable When this bit is set, the DMA MAC Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the DMA MAC Receive Buffer Unavailable Interrupt is disabled. 26 0 RW DMTPSIE DMA MAC Transmit Process Stopped Interrupt Enable When this bit is set, the DMA MAC Transmit Process Stopped Interrupt is enabled. When this bit is reset, the DMA MAC Transmit Process Stopped Interrupt is disabled. Description October 2007 40 M9999-100407-1.5 Micrel, Inc. Bit 25 Default 0 Read/ Write RW Description KSZ8841-PMQL DMRPSIE DMA MAC Receive Process Stopped Interrupt Enable When this bit is set, the DMA MAC Receive Process Stopped Interrupt is enabled. When this bit is reset, the DMA MAC Receive Process Stopped Interrupt is disabled. 24 - 0 - RO Reserved Interrupt Status Register (INTST Offset 0x002C) This register contains all the status bits for the ARM CPU. When corresponding enable bit is set, it cause the CPU to be interrupted. This register is usually read by the driver during interrupt service routine or polling. The register bits are not cleared when read. Each field can be masked. The following table shows the register bit fields. Bit 31 Default 0 Read/ Write RW DMLCS DMA MAC Link Changed Status When this bit is set, it indicates that the DMA MAC link status has changed from link up to link down or from link down to link up. This edge-triggered interrupt status is cleared by writing 1 to this bit. 30 0 RW DMTS DMA MAC Transmit Status When this bit is set, it indicates that the DMA MAC has transmitted at least a frame on the DMA port and the MAC is ready for new frames from the host. This edge-triggered interrupt status is cleared by writing 1 to this bit. 29 0 RW DMRS DMA MAC Receive Status When this bit is set, it indicates that the DMA MAC has received a frame from the DMA port and it is ready for the host to process This edge-triggered interrupt status is cleared by writing 1 to this bit. 28 0 RW DMTBUS DMA MAC Transmit Buffer Unavailable Status When this bit is set, it indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired by the KSZ8841PMQL. The transmission process is suspended. To resume processing transmit descriptors, the host should change the ownership bit of the descriptor and then issue a transmit start command. This edge-triggered interrupt status is cleared by writing 1 to this bit. 27 0 RW DMRBUS DMA MAC Receive Buffer Unavailable Status When this bit is set, it indicates that the descriptor list is owned by the host and cannot be acquired by the KSZ8841-PMQL. The receiving process is suspended. To resume processing receive descriptors, the host should change the ownership of the descriptor and may issue a receive start command. If no receive start command is issued, the receiving process resumes when the next recognized incoming frame is received. After the first assertion, this bit is not asserted for any subsequent not owned receive descriptors fetches. This bit is asserted only when the previous receive descriptor was owned by the KSZ8841PMQL. This edge-triggered interrupt status is cleared by writing 1 to this bit. 26 0 RW DMTPSS DMA MAC Transmit Process Stopped Status Description October 2007 41 M9999-100407-1.5 Micrel, Inc. Bit Default Read/ Write Description KSZ8841-PMQL Asserted when the DMA MAC transmit process enters the stopped state. This edge-triggered interrupt status is cleared by writing 1 to this bit. 25 0 RW DMRPSS DMA MAC Receive Process Stopped Status Asserted when the DMA MAC receive process enters the stopped state. This edge-triggered interrupt status is cleared by writing 1 to this bit. 24 - 0 RO Reserved MAC Additional Station Address Low Register (MAAL0-15) The KSZ8841-PMQLsupports 16 additional MAC addresses for MAC address filtering. This MAC address is used to define one of the 16 destination addresses that the KSZ8841-PMQL will respond to when receiving frames on the port. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received left to right, and the bits within each byte are received right to left (LSB to MSB). The actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. The following table shows the register bit fields. Bit 31 - 0 Default -Read/ Write RW MAAL0 MAC Additional Station Address 0 Low 4 bytes The least significant word of the additional MAC 0 station address. Description MAC Additional Station Address High Register (MAAH0-15) The KSZ8841-PMQL supports 16 additional MAC addresses for MAC address filtering. This MAC address is used to define one of the 16 destination addresses that the KSZ8841-PMQL will respond to when receiving frames on the port. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received left to right, and the bits within each byte are received right to left (LSB to MSB). The actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. The following table shows the register bit fields. Bit 31 Default 0 Read/ Write RW MAA0E MAC Additional Station Address 0 Enable When set, the additional MAC address is enabled for received frames. When reset, the additional MAC address is disabled. 30 - 16 15 - 0 0x0 -RO RW Reserved MAAH0 MAC Additional Station Address 0 High 2 bytes The most significant word of the additional MAC 0 station address. Description The following table shows the register map for all 16 additional MAC address registers. Register ADD MAC Low 0 ADD MAC High 0 ADD MAC Low 1 ADD MAC High 1 ADD MAC Low 2 IDENTIFIER MAAL0 MAAH0 MAAL1 MAAH1 MAAL2 OFFSET 0x0080 0x0084 0x0088 0x008C 0x0090 October 2007 42 M9999-100407-1.5 Micrel, Inc. Register ADD MAC High 2 ADD MAC Low 3 ADD MAC High 3 ADD MAC Low 4 ADD MAC High 4 ADD MAC Low 5 ADD MAC High 5 ADD MAC Low 6 ADD MAC High 6 ADD MAC Low 7 ADD MAC High 7 ADD MAC Low 8 ADD MAC High 8 ADD MAC Low 9 ADD MAC High 9 ADD MAC Low 10 ADD MAC High 10 ADD MAC Low 11 ADD MAC High 11 ADD MAC Low 12 ADD MAC High 12 ADD MAC Low 13 ADD MAC High 13 ADD MAC Low 14 ADD MAC High 14 ADD MAC Low 15 ADD MAC High 15 IDENTIFIER MAAH2 MAAL3 MAAH3 MAAL4 MAAH4 MAAL5 MAAH5 MAAL6 MAAH6 MAAL7 MAAH7 MAAL8 MAAH8 MAAL9 MAAH9 MAAL10 MAAH10 MAAL11 MAAH11 MAAL12 MAAH12 MAAL13 MAAH13 MAAL14 MAAH14 MAAL15 MAAH15 OFFSET 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC KSZ8841-PMQL MAC/PHY and Control Registers MAC Address Register Low (0x0200): MARL This register along with other 2 MAC address registers are loaded starting at word location 0x10 of the EEPROM upon hardware reset. The register can be modified by software driver, but will not modify the original MAC address value in the EEPROM. These six bytes of MAC address in external EEPROM are loaded to these three registers as mapping below: MARL[15:0] = EEPROM 0x1(MAC Byte 2 and 1) MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3) MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5) The MAC address is used to define the individual destination address the KSZ8841-PMQL responds to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101. October 2007 43 M9999-100407-1.5 Micrel, Inc. These three registers value for MAC address 01:23:45:67:89:AB will be held as below: MARL[15:0] = 0x89AB MARM[15:0] = 0x4567 MARH[15:0] = 0x0123 The following table shows the register bit fields for low word of MAC address. Bit 15-0 Default R/W RW Description MARL MAC Address Low The least significant word of the MAC address KSZ8841-PMQL MAC Address Register Middle (0x0202): MARM The following table shows the register bit fields for middle word of MAC address. Bit 15-0 Default R/W RW Description MARM MAC Address Middle The middle word of the MAC address MAC Address Register High (0x0204): MARH The following table shows the register bit fields for high word of MAC address. Bit 15-0 Default R/W RW Description MARH MAC Address High The Most significant word of the MAC address On-Chip Bus Control Register (Offset 0x0210): OBCR This register controls the on-chip bus speed for the KSZ8841-PMQL operations. It’s used for power management when the external host CPU is running a slow frequency. The default of the on-chip bus speed is 25MHz. When the external host CPU is running at a higher clock rate, it’s recommended the on-chip bus is adjusted accordingly for the best performance. Bit 15-2 1-0 Default 0x3 R/W RO RW Description Reserved OBSC On-Chip Bus Speed Control 00: 125 MHz 01: 62.5 MHz 10: 41.66 MHz 11: 25 MHz EEPROM Control Register (Offset 0x0212): EEPCR KSZ8841-PMQL supports both with and without EEPROM system design. To support external EEPROM, tie the EEPROM Enable (EEEN) pin to high; otherwise, tie it to Low (or no connect). Also, KSZ8841-PMQL allows software to access (read and write) EEPROM directly. That is, the EEPROM access timing can be fully controlled by software if EEPROM Software Access bit is set. Bit 15-5 4 Default 0 0 R/W RO RW Description Reserved EESA EEPROM Software Access 1 = Enable software to access EEPROM through bit 14 to bit 11. 0 = Disable software to access EEPROM. October 2007 44 M9999-100407-1.5 Micrel, Inc. Bit 3 Default 00 R/W RO Description EECB EEPROM Status Bits KSZ8841-PMQL Bit 3: Data receive from EEPROM. This bit directly reflects the value of the EEDI pin. 2 00 RW EECB EEPROM Control Bits Bit 2: Data In to EEPROM. This bit directly controls the device’s the EEDO pin. 1 0 00 00 RW RW EECB EEPROM Control Bits Bit 1: Serial Clock. This bit directly controls the device’s the EESK pin. EECB EEPROM Control Bits Bit 0: Chip Select. This bit directly controls the device’s the EECS pin. Memory BIST Info Register (Offset 0x0214): MBIR The following table shows the register bit fields. Bit 15-13 12 Default 0x0 R/W RO RO Description Reserved TXMBF TX Memory Bits Finish When set, it indicates the Memory Built In Self Test has completed for the TX Memory. 11 10-5 4 RO RO RO TXMBFA TX Memory Bits Fail When set, it indicates the Memory Built In Self Test has failed. Reserved RXMBF RX Memory Bits Finish When set, it indicates the Memory Built In Self Test has completed for the RX Memory. 3 2-0 RO RO RXMBFA RX Memory Bits Fail When set, it indicates the Memory Built In Self Test has failed. Reserved Global Reset Register (Offset 0x0216): GRR This register holds control information programmed by the CPU to control the global soft reset function. Bit 15-1 0 Default 0x00 0 R/W RO RW Description Reserved Global Soft Reset 1 = Software reset active 0 = Software reset inactive Soft reset will affect all of the registers except PCI configuration registers. October 2007 45 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Power Management Capabilities Register (Offset 0x0218): PMCR This register is a read-only register that provides information on the KSZ8841-PMQL power management capabilities. These bits are automatically downloaded from the Configparam word of EEPROM, if pin EEEN is pulled high (enable EEPROM). The PMCR register bits [15-0] are mirrored to CCID register bits [31-16]. Bit 15 Default 0 R/W RO Description PME Support D3 (cold) This bit is 0 only; the KSZ8841-PMQL does not support PME in D3(cold) power state. 14 1 RO PME Support D3 (hot) This bit is 1 only, it is indicating that the KSZ8841-PMQL can assert PME event (PMEN pin 14) in D3(hot) power state. 13 0 RO PME Support D2 If this bit is set, the KSZ8841-PMQL asserts PME event (PMEN pin 14) when the KSZ8841PMQL is in D2 power state and PME_EN (see bit8 in PMCS register) is set. Otherwise, the KSZ8841PMQL does not assert PME event (PMEN pin 14) when the KSZ8841PMQL is in D2 power state. The value of this bit is loaded from the PME_D2 bit in the EEPROM 0x6 word. 12 0 RO PME Support D1 If this bit is set, the KSZ8841-PMQL asserts PME event (PMEN pin 14) when the KSZ8841-PMQL is in D1 power state and PME_EN (see bit8 in PMCS register) is set. Otherwise, the KSZ8841M does not assert PME event (PMEN pin 14) when the KSZ8841M is in D1 power state. The value of this bit loaded from the PME_D1 bit in the EEPROM 0x6 word. 11 0 RO PME Support D0 This bit is 0 only, it indicates that the KSZ8841-PMQL does not assert PME event (PMEN pin 14) in D0 power state. 10 0 RO D2 Support If this bit is set, it indicates that the KSZ8841-PMQL support D2 power state. The value of this bit is loaded from the D2_SUP bit in the EEPROM 0x6 word. (This bit is 0 only if without EEPROM). 9 0 RO D1 Support If this bit is set, it indicates that the KSZ8841-PMQL support D1 power state. The value of this bit loaded from the D1_SUP bit in the EEPROM 0x6 word. (This bit is 0 only if without EEPROM). 8-6 000 RO Auxiliary Current This 3-bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. If PME# generation from D3_cold is not supported by the function, this field must return a value of 000 when read. 5 0 RO Device Specific Initialization Indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. Note that this bit is not used by some operating systems. Microsoft Windows and Windows NT, for instance, do not use this bit to determine whether to use D3. Instead, they use the driver’s capabilities to determine this. October 2007 46 M9999-100407-1.5 Micrel, Inc. Bit Default R/W Description KSZ8841-PMQL A “1” indicates that the function requires a device specific initialization sequence following transition to the D0 uninitialization state. The value of this bit is loaded from the PME_DSI bit in the EEPROM 0X6 word. 4 3 0 0 RO RO Reserved PME Clock When this bit is a “1”, it indicates that the function relies on the presence of the PCI clock for PME# operation. When this bit is a “0”, it indicates that no PCI clock is required for the function to generate PME#. The value of this bit is loaded from the PME_CK bit in the EEPROM 0x6 word. 2-0 0 RO Power Management PCI Version The value of this bit is loaded from the PME_VER[2:0] bits in the EEPROM 0x6 word. Wakeup Frame Control Register (Offset 0x021A): WFCR This register holds control information programmed by the CPU to control the transmit module function. Bit 15 - 8 7 Default 0x00 0 R/W RO RW Description Reserved MPRXE Magic Packet RX Enable When set, it enables the magic packet pattern detection. When reset, the magic packet pattern detection is disabled. 6-4 3 0x0 0 RO RW Reserved WF3E Wake up Frame 3 Enable When set, it enables the wake up frame 3 pattern detection. When reset, the wake up frame pattern detection is disabled. 2 0 RW WF2E Wake up Frame 2 Enable When set, it enables the wake up frame 2 pattern detection. When reset, the wake up frame pattern detection is disabled. 1 0 RW WF1E Wake up Frame 1 Enable When set, it enables the wake up frame 1 pattern detection. When reset, the wake up frame pattern detection is disabled. 0 0 RW WF0E Wake up Frame 0 Enable When set, it enables the wake up frame 0 pattern detection. When reset, the wake up frame pattern detection is disabled. October 2007 47 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Wakeup Frame 0 CRC0 Register (Offset 0x0220): WF0CRC0 This register contains the expected CRC values of the Wake up frame 0 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF0CRC0 Wake up Frame 0 CRC (lower 16 bits) The expected CRC value of a wake up frame 0 pattern. Wakeup Frame 0 CRC1 Register (Offset 0x0222): WF0CRC1 This register contains the expected CRC values of the Wake up frame 0 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF0CRC1 Wake up Frame 0 CRC (upper 16 bits) The expected CRC value of a wake up frame 0 pattern. Wakeup Frame 0 Byte Mask 0 Register (Offset 0x0224): WF0BM0 This register contains the first 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the first byte of the Wake up frame 0; setting bit 15 selects the 16th byte of the Wake up frame 0. Bit 15 - 0 Default -R/W RW Description WF0BM0 Wake up Frame 0 Byte Mask 0 The first 16 bytes mask of a wake up frame 0 pattern. Wakeup Frame 0 Byte Mask 1 Register (Offset 0x0226): WF0BM1 This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 0; setting bit 15 selects the 32nd byte of the Wake up frame 0. Bit 15 - 0 Default -R/W RW Description WF0BM1 Wake up Frame 0 Byte Mask 1 The next 16 bytes mask covering bytes 17 to 32 of a wake up frame 0 pattern. Wakeup Frame 0 Byte Mask 2 Register (Offset 0x0228): WF0BM2 This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 0; setting bit 15 selects the 48th byte of the Wake up frame 0. Bit 15 - 0 Default -R/W RW Description WF0BM2 Wake up Frame 0 Byte Mask 2 The next 16 bytes mask covering bytes 33 to 48 of a wake up frame 0 pattern. October 2007 48 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Wakeup Frame 0 Byte Mask 3 Register (Offset 0x022A): WF0BM3 This register contains the last 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 0; setting bit 15 selects the 64th byte of the Wake up frame 0. Bit 15 - 0 Default -R/W RW Description WF0BM2 Wake up Frame 0 Byte Mask 3 The last 16 bytes mask covering bytes 49 to 64 of a wake up frame 0 pattern. Wakeup Frame 1 CRC0 Register (Offset 0x0230): WF1CRC0 This register contains the expected CRC values of the Wake up frame 1 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF1CRC0 Wake up Frame 1 CRC (lower 16 bits) The expected CRC value of a wake up frame 1 pattern. Wakeup Frame 1 CRC1 Register (Offset 0x0232): WF1CRC1 This register contains the expected CRC values of the Wake up frame 1 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF1CRC1 Wake up Frame 1 CRC (upper 16 bits) The expected CRC value of a wake up frame 1 pattern. Wakeup Frame 1 Byte Mask 0 Register (Offset 0x0234): WF1BM0 This register contains the first 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the first byte of the Wake up frame 1; setting bit 15 selects the 16th byte of the Wake up frame 1. Bit 15 - 0 Default -R/W RW Description WF1BM0 Wake up Frame 1 Byte Mask 0 The first 16 bytes mask of a wake up frame 1 pattern. Wakeup Frame 1 Byte Mask 1 Register (Offset 0x0236): WF1BM1 This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 1; setting bit 15 selects the 32nd byte of the Wake up frame 1. Bit 15 - 0 Default -R/W RW Description WF1BM1 Wake up Frame 1 Byte Mask 1 The next 16 bytes mask covering bytes 17 to 32 of a wake up frame 1 pattern. October 2007 49 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Wakeup Frame 1 Byte Mask 2 Register (Offset 0x0238): WF1BM2 This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 1; setting bit 15 selects the 48th byte of the Wake up frame 1. Bit 15 - 0 Default -R/W RW Description WF1BM2 Wake up Frame 1 Byte Mask 2 The next 16 byte mask covering bytes 33 to 48 of a wake up frame1 pattern. Wakeup Frame 1 Byte Mask 3 Register (Offset 0x023A): WF1BM3 This register contains the last 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 1; setting bit 15 selects the 64th byte of the Wake up frame 1. Bit 15 - 0 Default -R/W RW Description WF1BM2 Wake up Frame 1 Byte Mask 3 The last 16 bytes mask covering bytes 49 to 64 of a wake up frame 1 pattern. Wakeup Frame 2 CRC0 Register (Offset 0x0240): WF2CRC0 This register contains the expected CRC values of the Wake up frame 2 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF2CRC0 Wake up Frame 2 CRC (lower 16 bits) The expected CRC value of a wake up frame 2 pattern. Wakeup Frame 2 CRC1 Register (Offset 0x0242): WF2CRC1 This register contains the expected CRC values of the Wake up frame 2 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF2CRC1 Wake up Frame 2 CRC (upper 16 bits) The expected CRC value of a wake up frame 2 pattern. Wakeup Frame 2 Byte Mask 0 Register (Offset 0x0244): WF2BM0 This register contains the first 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the first byte of the Wake up frame 2; setting bit 15 selects the 16th byte of the Wake up frame 2. Bit 15 - 0 Default -R/W RW Description WF2BM0 Wake up Frame 2 Byte Mask 0 The first 16 byte mask of a wake up frame 2 pattern. October 2007 50 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Wakeup Frame 2 Byte Mask 1 Register (Offset 0x0246): WF2BM1 This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 2; setting bit 15 selects the 32nd byte of the Wake up frame 2. Bit 15 - 0 Default -R/W RW Description WF2BM1 Wake up Frame 2 Byte Mask 1 The next 16 bytes mask covering bytes 17 to 32 of a wake up frame 2 pattern. Wakeup Frame 2 Byte Mask 2 Register (Offset 0x0248): WF2BM2 This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 2; setting bit 15 selects the 48th byte of the Wake up frame 2. Bit 15 - 0 Default -R/W RW Description WF2BM2 Wake up Frame 2 Byte Mask 2 The next 16 bytes mask covering bytes 33 to 48 of a wake up frame 2 pattern. Wakeup Frame 2 Byte Mask 3 Register (Offset 0x024A): WF2BM3 This register contains the last 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 2; setting bit 15 selects the 64th byte of the Wake up frame 2. Bit 15 - 0 Default -R/W RW Description WF2BM2 Wake up Frame 2 Byte Mask 3 The last 16 bytes mask covering bytes 49 to 64 of a wake up frame 2 pattern. Wakeup Frame 3 CRC0 Register (Offset 0x0250): WF3CRC0 This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF3CRC0 Wake up Frame 3 CRC (lower 16 bits) The expected CRC value of a wake up frame 3 pattern. Wakeup Frame 3 CRC1 Register (Offset 0x0252): WF3CRC1 This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. Bit 15 - 0 Default -R/W RW Description WF3CRC1 Wake up Frame 3 CRC (upper 16 bits) The expected CRC value of a wake up frame 3 pattern. October 2007 51 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Wakeup Frame 3 Byte Mask 0 Register (Offset 0x0254): WF3BM0 This register contains the first 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the first byte of the Wake up frame 3; setting bit 15 selects the 16th byte of the Wake up frame 3. Bit 15 - 0 Default -R/W RW Description WF3BM0 Wake up Frame 3 Byte Mask 0 The first 16bytes mask of a wake up frame 3 pattern. Wakeup Frame 3 Byte Mask 1 Register (Offset 0x0256): WF3BM1 This register contains the next 16bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 17th byte of the Wake up frame 3; setting bit 15 selects the 32nd byte of the Wake up frame 3. Bit 15 - 0 Default -R/W RW Description WF3BM1 Wake up Frame 3 Byte Mask 1 The next 16bytes mask covering bytes 17 to 32 of a wake up frame 3 pattern. Wakeup Frame 3 Byte Mask 2 Register (Offset 0x0258): WF3BM2 This register contains the next 16bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 33rd byte of the Wake up frame 3; setting bit 15 selects the 48th byte of the Wake up frame 3. Bit 15 - 0 Default -R/W RW Description WF3BM2 Wake up Frame 3 Byte Mask 2 The next 16bytes mask covering bytes 33 to 48 of a wake up frame 3 pattern. Wakeup Frame 3 Byte Mask 3 Register (Offset 0x025A): WF3BM3 This register contains the last 16bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte of the Wake up frame 3; setting bit 15 selects the 64th byte of the Wake up frame 3. Bit 15 - 0 Default -R/W RW Description WF3BM2 Wake up Frame 3 Byte Mask 3 The last 16 bytes mask covering bytes 49 to 64 of a wake up frame 3 pattern. Chip ID and Enable Register (Offset 0x0400): CIDER This register contains the chip ID, and the chip enables control. Bit 15-8 7-4 3-1 0 Default 0x88 0x05 000 R/W RO RO RO RW Description Family ID Chip family ID Chip ID 0x05 is assigned to KSZ8841-PMQL Revision ID Start Controller 1 = Start the chip operation 0 = Stop the chip operation October 2007 52 M9999-100407-1.5 Micrel, Inc. Chip Global Control Register (Offset 0x040A): CGCR This register contains the global control for the chip function. Bit 15 14-10 9 Default 0 Reserved 0 R/W RW RW RW Description LEDSEL1 See description for bit 9. Reserved LEDSEL0 KSZ8841-PMQL The two register bits LEDSEL1 and LEDSEL0, are used to select the LED mode. The LED Indicators, are defined as below: [LEDSEL1, LEDSEL0] [0, 0] P1LED3 P1LED2 P1LED1 P1LED0 -----LINK/ACT FULL_DPX/COL SPEED [0, 1] -----100LINK/ACT 10LINK/ACT FULL_DPX [LEDSEL1, LEDSEL0] [1, 0] P1LED3 P1LED2 P1LED1 P1LED0 8-0 0 RW Reserved ACT LINK FULL_DPX/COL SPEED [1, 1] --------------------- Indirect Access Control Register (Offset 0x04A0): IACR This register contains the indirect control for the MIB counter. Write IACR will actually trigger a command. Read or write access is determined by this register bit 12. Bit 15-13 12 Default 000 0 R/W RW RW Description Reserved Read High. Write Low 1 = Read cycle 0 = Write cycle 11-10 9-0 00 0x000 RW RW Table select 11 = MIB counter selected Indirect address Bit 9-0 of indirect address Note: (1) write IACR will actually trigger a command. Read or write access is determined by Register bit 12. October 2007 53 M9999-100407-1.5 Micrel, Inc. Indirect Access Data Register 1 (Offset 0x04A2): IADR1 This register contains the indirect data for the chip function. Bit 15-8 7 Default 0x00 0 R/W RO RO Description Reserved CPU Read Status Only for dynamic and statistics counter reads. 1 = Read is still in progress 0 = Read has completed 6-3 2-0 0x0 000 RO RO Reserved Reserved KSZ8841-PMQL Indirect Access Data Register 2 (Offset 0x04A4): IADR2 This register contains the indirect data for the chip function. Bit 15-0 Default 0x0000 R/W RW Description Indirect data Bit 47-32 of indirect data Indirect Access Data Register 3 (Offset 0x04A6): IADR3 This register contains the indirect data for the chip function. Bit 15-0 Default 0x0000 R/W RW Description Reserved Indirect Access Data Register 4 (Offset 0x04A8): IADR4 This register contains the indirect data for the chip function. Bit 15-0 Default 0x0000 R/W RW Description Indirect data Bit 15-0 of indirect data Indirect Access Data Register 5 (Offset 0x04AA): IADR5 This register contains the indirect data for the chip function. Bit 15-0 Default 0x0000 R/W RW Description Indirect data Bit 31-16 of indirect data Reserved (Offset 0x04C0-0x04CF) October 2007 54 M9999-100407-1.5 Micrel, Inc. PHY 1 MII Register Basic Control Register (Offset 0x04D0): P1MBCR This register contains the MII register control for the chip function. Bit 15 14 13 Default 0 0 0 R/W RO RW RW Description Soft reset NOT SUPPORTED Reserved. Force 100 1 = Force 100 Mbps if AN is disabled (bit12) 0 = Force 10 Mbps if AN is disabled (bit12) 12 1 RW AN enable 1 = Auto-negotiation enabled 0 = Auto-negotiation disabled 11 0 RW Power down 1 = Power down 0 = Normal operation 10 9 0 0 RO RW Isolate NOT SUPPORTED Restart AN 1 = Restart auto-negotiation 0 = Normal operation 8 0 RW Force full duplex 1 = Force full duplex if AN is disabled (bit12) 0 = Force half duplex if AN is disabled (bit12) 7 6 5 0 0 0 RO RO R/W Reserved Reserved HP_mdix 1 = HP Auto MDIX mode 0 = Micrel Auto MDIX mode 4 0 RW Force MDIX 1 = Force MDIX 0 = Normal operation 3 0 RW Disable MDIX 1 = Disable auto MDIX 0 = Normal operation 2 0 RW Disable far end fault 1 = Disable far end fault detection 0 = Normal operation 1 0 RW Disable transmit 1 = Disable transmit 0 = Normal operation 0 0 RW Disable LED 1 = Disable LED 0 = Normal operation P1CR4, bit 15 P1CR4, bit 14 P1CR4, bit 12 P1CR4, bit 10 P1CR4, bit 9 P1SR, bit 15 P1CR4, bit 5 P1CR4, bit 13 P1CR4, bit 11 P1CR4, bit 7 P1CR4, bit 6 KSZ8841-PMQL Is the Same as October 2007 55 M9999-100407-1.5 Micrel, Inc. PHY 1 MII Register Basic Status Register (Offset 0x04D2): P1MBSR This register contains the MII register control for the chip function. Bit 15 Default 0 R/W RO Description T4 capable 1 = 100 Base-T4 capable 0 = Not 100 BaseT4 capable 14 1 RO 100 Full capable 1 = 100BaseTX full duplex capable 0 = Not 100BaseTX full duplex capable 13 1 RO 100 Half capable 1 = 100BaseTX half duplex capable 0 = Not 100BaseTX half duplex capable 12 1 RO 10 Full capable 1 = 10BaseT full duplex capable 0 = Not 10BaseT full duplex capable 11 1 RO 10 Half capable 1 = 10BaseT half duplex capable 0 = Not 10BaseT half duplex capable 10-7 6 5 0 0 0 RO RO RO Reserved Preamble suppressed NOT SUPPORTED AN complete 1 = Auto-negotiation complete 0 = Auto-negotiation not completed 4 0 RO Far end fault 1 = Far end fault detected 0 = No far end fault detected 3 1 RO AN capable 1 = Auto-negotiation capable 0 = Not auto-negotiation capable 2 0 RO Link status 1 = Link is up 0 = Link is down 1 0 0 0 RO RO Reserved Extended capable 1 = Extended register capable 0 = Not extended register capable P1SR, bit 5 P1CR4, bit 7 P1SR, bit 8 P1SR, bit 6 Always 1 Always 1 Always 1 Always 1 KSZ8841-PMQL Is the Same as PHY 1 PHYID Low Register (Offset 0x04D4): PHY1ILR This register contains the PHY ID (low) for the chip function. Bit 15-0 Default 0x1430 R/W RO Description PHYID low Low order PHYID bits October 2007 56 M9999-100407-1.5 Micrel, Inc. PHY 1 PHYID High Register (Offset 0x04D6): PHY1IHR This register contains the PHY ID (high) for the chip function. Bit 15-0 Default 0x0022 R/W RO Description PHYID high High order PHYID bits KSZ8841-PMQL PHY 1 Auto-Negotiation Advertisement Register (Offset 0x04D8): P1ANAR This register contains the auto-negotiation advertisement for the chip function. Bit 15 14 13 12-11 10 Default 0 0 0 0 1 R/W RO RO RO RO RW Description Next page NOT SUPPORTED Reserved Remote fault NOT SUPPORTED Reserved Pause (follow control capability) 1 = Advertise pause ability 0 = Do not advertise pause ability 9 8 0 1 RW RW Reserved Adv 100 Full 1 = Advertise 100 full duplex ability 0 = Do not advertise 100 full duplex ability 7 1 RW Adv 100 Half 1 = Advertise 100 half duplex ability 0 = Do not advertise 100 half duplex ability 6 1 RW Adv 10 Full 1 = Advertise 10 full duplex ability 0 = Do not advertise 10 full duplex ability 5 1 RW Adv 10 Half 1 = Advertise 10 half duplex ability 0 = Do not advertise 10 half duplex ability 4-0 0_0001 RO Selector field 802.3 P1CR4, bit 0 P1CR4, bit 1 P1CR4, bit 2 P1CR4, bit 3 P1CR4, bit 4 Is the Same as PHY 1 Auto-Negotiation Link Partner Ability Register (Offset 0x04DA): P1ANLPR This register contains the auto-negotiation link partner ability for the chip function. Bit 15 14 13 12-11 Default 0 0 0 0 R/W RO RO RO RO Description Next page NOT SUPPORTED LP ACK NOT SUPPORTED Remote fault NOT SUPPORTED Reserved Is the Same as October 2007 57 M9999-100407-1.5 Micrel, Inc. Bit 10 9 8 7 6 5 4-0 Default 0 0 0 0 0 0 0_0000 R/W RO RO RO RO RO RO RO Description Pause Link partner pause capability Reserved Adv 100 Full Link partner 100 full capability Adv 100 Half Link partner 100 half capability Adv 10 Full Link partner 10 full capability Adv 10 Half Link partner 10 half capability Reserved P1SR, bit 0 P1SR, bit 1 P1SR, bit 2 P1SR, bit 3 KSZ8841-PMQL Is the Same as P1SR, bit 4 PHY1 LinkMD Control/Status (Offset 0x04F0): P1VCT This register contains the LinkMD control and status of PHY 1: Bit 15 Default 0 R/W RW SC (self-clear) Description Vct_enable 1 = The cable diagnostic test is enabled. It’ll be self-cleared after VCT test is done 0 = It indicates the cable diagnostic test is completed and the status information is valid for read 14 - 13 0 RO Vct_result [00] = Normal condition [01] = Open condition has been detected in cable [10] = Short condition has been detected in cable [11] = Cable diagnostic test is failed 12 11 - 9 8-0 0 0 RO RO RO Vct 10M short 1 = Less than 10 meter short Reserved Vct_fault_count Distance to the fault. The distance is approximately 0.4m X vct_fault_count P1SCSLMD, bits 8-0 P1SCSLMD, bit 15 P1SCSLMD, bit 14-13 Is the Same as P1SCSLMD, bit 12 PHY1 Special Control/Status Register (Offset 0x04F2): P1PHYCTRL This register contains the control and status information of PHY1: Bit 15 - 6 5 Default 0 0 R/W RO RO Description Reserved Polarity reverse (polrvs) 1 = Polarity is reversed 0 = Polarity is not reversed P1SR, bit 13 Is the Same as October 2007 58 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Bit 4 Default 0 R/W RO Description MDIX Status (mdix_st) 1 = MDIX 0 = MDI Is the Same as P1SR, bit 7 3 0 RW Force Link (force_lnk) 1 = Force link pass 0 = Normal Operation P1SCSLMD, bit 11 2 1 RW Power Saving (pwrsave) 1 = Disable 0 = Enable power saving P1SCSLMD, bit 10 1 0 RW Remote loopback (rlb) 1 = Loop back at PMD/PMA of port’s PHY (RXP1/RXM1 -> TXP1/TXM1) 0 = Normal operation. P1SCSLMD, bit 9 0 0 RW Reserved Reserved (Offset 0x04F8 - 0x04FA) Bit 15-0 Default 0x0000 R/W RO Description Reserved Port 1 PHY Special Control/Status, LinkMD (Offset 0x0510): P1SCSLMD This register contains the port LinkMD control register for the chip function. Bit 15 14-13 Default 0 0 R/W RO RO Description Vct 10M short Less than 10 meter short Vct result [00] = Normal condition [01] = Open condition has been detected in cable [10] = Short condition has been detected in cable [11] = Cable diagnostic test is failed 12 0 RW SC (self clear) Vct enable 1 = The cable diagnostic test is enabled. It’ll be self-cleared after VCT test is done 0 = It indicates the cable diagnostic test is completed and the status information is valid for read Force Link 1 = Force link pass 0 = Normal Operation 10 1 RW Power Saving 1 = Disable 0 = Enable power saving P1PHYCTRL, bit 2 P1PHYCTRL, bit 3 P1VCT, bit 15 P1VCT, bits 14 - 13 Is the Same as P1VCT, bit 12 11 0 RW October 2007 59 M9999-100407-1.5 Micrel, Inc. Bit 9 Default 0 R/W RW Description Remote loopback 1 = Loop back at PMD/PMA of port’s PHY (RXP1/RXM1 -> TXP1/TXM1) 0 = Normal operation. 8-0 0x000 RO VCT fault count Distance to the fault. The distance is approximately 0.4m X vct_fault_count KSZ8841-PMQL Is the Same as P1PHYCTRL, bit 1 P1VCT, bits 8-0 Port 1 Control Register 4 (Offset 0x0512): P1CR4 This register contains the global per port control for the chip function. Bit 15 Default 0 R/W RW Description LED off 1 = Turn off all port’s LEDs (LED1_3, LED1_2, LED1_1, LED1_0. These pins will be driven high if this bit is set to one 0 = Normal operation 14 0 RW Txids 1 = Disable port’s transmitter 0 = Normal operation 13 0 RW Restart AN 1 = Restart auto-negotiation 0 = Normal operation 12 0 RW Disable Far end fault 1 = Disable far end fault detection & pattern transmission. 0 = Enable far end fault detection & pattern transmission. 11 0 RW Power down 1 = Power down 0 = Normal operation 10 0 RW Disable auto MDI/MDIX 1 = Disable auto MDI/MDIX function 0 = Enable auto MDI/MDIX function 9 0 RW Force MDIX 1 = If auto MDI/MDIX is disabled, force PHY into MDIX mode 0 = Do not force PHY into MDIX mode 8 7 0 1 RW Reserved Auto Negotiation Enable 1 = Auto negotiation is enable 0 = Disable auto negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 6 0 RW Force Speed 1 = Force 100BT if AN is disabled (bit 7) P1MBCR, bit 13 P1MBCR, bit 14 P1MBCR, bit 12 P1MBCR, bit 4 P1MBCR, bit 3 P1MBCR, bit 11 P1MBCR, bit 2 P1MBCR, bit 9 P1MBCR, bit 1 Is the Same as P1MBCR, bit 0 October 2007 60 M9999-100407-1.5 Micrel, Inc. Bit 5 Default 0 R/W RW Description 0 = Force 10BT if AN is disabled (bit 7) Force duplex 1 = Force full duplex if (1) AN is disabled or (2) AN is enabled but failed. 0 = Force half duplex if (1) AN is disabled or (2) AN is enabled but failed. 4 1 RW Advertised flow control capability 1 = Advertise flow control (pause) capability 0 = Suppress flow control (pause) capability from transmission to link partner 3 1 RW Advertised 100BT Full duplex capability 1 = Advertise 100BT Full duplex capability 0 = Suppress 100BT Full duplex capability from transmission to link partner 2 1 RW Advertised 100BT half duplex capability 1 = Advertise 100BT Half duplex capability 0 = Suppress 100BT Half duplex capability from transmission to link partner 1 1 RW Advertised 10BT Full duplex capability 1 = Advertise 10BT Full duplex capability 0 = Suppress 10BT Full duplex capability from transmission to link partner 0 1 RW Advertised 10BT half duplex capability 1 = Advertise 10BT Half duplex capability 0 = Suppress 10BT Half duplex capability from transmission to link partner P1ANAR, bit 0 P1ANAR, bit 1 P1ANAR, bit 2 P1ANAR, bit 3 P1ANAR, bit 4 KSZ8841-PMQL Is the Same as P1MBCR, bit 9 Port 1 Status Register (Offset 0x0514): P1SR This register contains the global per port status for the chip function. Bit 15 Default 0 R/W RW Description HP_mdix 1 = HP Auto MDIX mode 0 = Micrel Auto MDIX mode 14 13 0 0 RO RO Reserved Polarity reverse 1 = Polarity is reversed 0 = Polarity is not reversed 12 0 RO Receive flow control enable 1 = Receive flow control feature is active 0 = Receive flow control feature is inactive 11 0 RO Transmit flow control enable 1 = Transmit flow control feature is active 0 = Transmit flow control feature is inactive 10 0 RO Operation Speed 1 = Link speed is 100Mbps P1PHYCTRL, bit 5 Is the Same as P1MBCR, bit 5 October 2007 61 M9999-100407-1.5 Micrel, Inc. Bit 9 Default 0 R/W RO Description 0 = Link speed is 10Mbps Operation duplex 1 = Link duplex is full 0 = Link duplex is half 8 0 RO Far end fault 1 = Far end fault status detected 0 = No Far end fault status detected 7 0 RO MDIX status 1 = MDIX 0 = MDI 6 0 RO AN done 1 = AN done 0 = AN not done 5 0 RO Link good 1 = Link good 0 = Link not good 4 0 RO Partner flow control capability 1 = Link partner flow control (pause) capable 0 = Link partner not flow control (pause) capable 3 0 RO Partner 100BT full duplex capability 1 = Link partner 100BT full duplex capable 0 = Link partner not 100BT full duplex capable 2 0 RO Partner 100BT half duplex capability 1 = Link partner 100BT half duplex capable 0 = Link partner not 100BT half duplex capable 1 0 RO Partner 10BT full duplex capability 1 = Link partner 10BT full duplex capable 0 = Link partner not 10BT full duplex capable 0 0 RO Partner 10BT half duplex capability 1 = Link partner 10BT half duplex capable 0 = Link partner not 10BT half duplex capable P1MBSR, bit 2 P1MBSR, bit 5 P1MBSR, bit 4 KSZ8841-PMQL Is the Same as P1PHYCTRL, bit 4 P1ANLPR, bit 10 P1ANLPR, bit 8 P1ANLPR, bit 7 P1ANLPR, bit 6 P1ANLPR, bit 5 Reserved (Offset 0x0516 – 0x0560) Bit 15 - 0 Default 0x0000 R/W RO Description Reserved October 2007 62 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL MIB (Management Information Base) Counters The KSZ8841-PMQL provides 32 MIB counters to monitor the port activity for network management. The MIB counters are formatted as shown in Table 4. Bit 31 30 29-0 Name Overflow Count valid Counter values R/W RO RO RO Description 1 = Counter overflow. 0 = No counter overflow. 1 = Counter value is valid. 0 = 0 counter value is not valid. Counter value 0 0 Default 0 Table 4. Format of Port MIB Counters The port MIB counters are read using indirect memory access. The base address offsets is 0x00 and address ranges is 0x00-0x1F as shown in Table 5. The Port MIB counters read/write functions use Access Control register IACR (0x04A0) bit 12. The base address offset and address range for port 1 is 0x00 and range is (0x00-0x1F) that can be changed in register IACR (0x04A0) bits[9:0]. The data of MIB counters are from the Indirect Access data register IADR4 (0x04A8) and IADR5 (0x04AA) based on Table 4. Offset 0x0 (base address) 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA RxUndersizePkt RxFragments RxOversize RxJabbers RxSymbolError RxCRCError RxAlignmentError RxControl8808Pkts RxPausePkts Counter Name RxByte Description Rx octet count including bad packets. Reserved. Do not write to this register. Rx undersize packets w/ good CRC. Rx fragment packets w/ bad CRC, symbol errors or alignment errors. Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes). Rx packets longer than 1522 bytes w/ either CRC errors, alignment errors, or symbol errors (depends on max packet size setting). Rx packets w/ invalid data symbol and legal packet size. Rx packets within (64,1522) bytes w/ an integral number of bytes and a bad CRC (upper limit depends on max packet size setting). Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC (upper limit depends on max packet size setting). Number of MAC control frames received by a port with 88-08h in EtherType field. Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC. Rx good broadcast packets (not including error broadcast packets or valid multicast packets). Rx good multicast packets (not including MAC control frames, error multicast packets or valid broadcast packets). Rx good unicast packets. Total Rx packets (bad packets included) that were 64 octets in length. Total Rx packets (bad packets included) that are between 65 and 127 octets in length. Total Rx packets (bad packets included) that are between 128 and 255 octets in length. Total Rx packets (bad packets included) that are between 256 and 511 0xB 0xC 0xD 0xE 0xF 0x10 0x11 RxBroadcast RxMulticast RxUnicast Rx64Octets Rx65to127Octets Rx128to255Octets Rx256to511Octets October 2007 63 M9999-100407-1.5 Micrel, Inc. Offset 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A TxLateCollision TxPausePkts TxBroadcastPkts TxMulticastPkts TxUnicastPkts Counter Name Rx512to1023Octets Rx1024to1522Octets TxByte Description octets in length. KSZ8841-PMQL Total Rx packets (bad packets included) that are between 512 and 1023 octets in length. Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). Tx good octet count, including PAUSE packets. Reserved. Do not write to this register. The number of times a collision is detected later than 512 bit-times into the Tx of a packet. Number of PAUSE frames transmitted by a port. Tx good broadcast packets (not including error broadcast or valid multicast packets). Tx good multicast packets (not including error multicast packets or valid broadcast packets). Tx good unicast packets. Table 5. Port 1’s MIB Counters Indirect Memory Offsets Example: MIB Counter Read (read “Rx64Octets” counter at indirect address offset 0x0E) Write to reg. IACR with 0x1C0E (set indirect address and trigger a read MIB counters operation) Then: Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow // If bit 30 = 0, restart (reread) from this register Read reg. IADR4 (MIB counter value 15-0) Additional MIB Information In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read. October 2007 64 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Absolute Maximum Ratings(1) Supply Voltage (VDDATX, VDDARX, VDDIO) ........................... –0.5V to +4.0V Input Voltage (all inputs). ............................. –0.5V to +5.0V Output Voltage (all outputs) ......................... –0.5V to +4.0V Lead Temperature (soldering, 10sec.) ....................... 270°C Storage Temperature (Ts) .........................–55°C to +150°C Operating Ratings(2) Supply Voltage (VDDATX, VDDARX, VDDIO)...................... +3.1V to +3.5V Ambient Temperature (TA) ....................... 0°C to +70°C Junction Temperature (TJ) .................................. 125°C Package Thermal Resistance(3) PQFP (θJA) No Air Flow........................ 42.91°C/W PQFP (θJC) No Air Flow .......................... 19.6°C/W Electrical Characteristics(4) Symbol Parameter Condition Min Typ Max Units Supply Current 100BASE-TX Operation (All Ports @ 100% Utilization) IDDXIO 100BASE-TX (Analog Core + Digital Core + Transceiver + Digital I/O) 100BASE-TX (Analog Core + Digital Core + Transceiver + Digital I/O) Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage Output Tri-state Leakage Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Output Jitter 10Base-T Receive VSQ VP Squelch Threshold Peak Differential Output Voltage Jitter Added 5MHz square wave 100Ω termination on the differential output. 100Ω termination on the differential output. 400 2.4 1.8 ±3.5 mV V ns 10Base-T Transmit (measured differentially after 1:1 transformer) VDDATX = 3.3V only Peak to peak 0.5 0.7 1.4 100Ω termination on the differential output. 100Ω termination on the differential output. 3 0 0.95 VIN = GND ~ VDDIO IOH = –8mA IOL = 8mA –10 2.4 0.4 10 1.05 2 5 0.5 ±0.5 5 VDDATX, VDDARX, VDDIO = 3.3V 100 mA 10BASE-TX Operation (All Ports @ 100% Utilization) IDDXIO VDDATX, VDDARX, VDDIO = 3.3V 85 mA TTL Inputs VIH VIL IIN VOH VOL IOZ VO VIMB tr, tf 2.0 0.8 10 V V µA V V µA V % ns ns ns % V ns TTL Outputs 100Base-TX Transmit (measured differentially after 1:1 transformer) VDDATX = 3.3V only October 2007 65 M9999-100407-1.5 Micrel, Inc. Notes: KSZ8841-PMQL 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level. 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD) 3. No (HS) heat spreader in this package. The thermal junction to ambient (θJA) and the thermal junction to case (θJC) are under air velocity 0m/s. 4. Specification for packaged product only. A single port’s transformer consumes an additional 45mA at 3.3V for 100BASE-T and 70mA at 3.3V for 10BASE-T. October 2007 66 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Timing Diagrams For PCI Timing, please refer to PCI specification version 2.2. EEPROM Timing EECS *1 EESK 1 EEDO 11 0 An A0 ts th D15 D14 D13 D1 D0 EEDI Hight-Z *1 Start bit Figure 7. EEPROM Read Cycle Timing Diagram Timing Parameter tcyc ts th Description Clock cycle Setup time Hold time Min 20 20 Typ 4000 Max Unit ns ns ns Table 6. EEPROM Timing Parameters October 2007 67 M9999-100407-1.5 Micrel, Inc. Auto Negotiation Timing KSZ8841-PMQL FLP Burst FLP Burst TX+/TXtFLPW tBTB Clock Pulse TX+/TXtPW tCTD Data Pulse tPW Clock Pulse Data Pulse tCTC Figure 8. Auto-Negotiation Timing Timing Parameter tBTB tFLPW tPW tCTD tCTC Description FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to data pulse Clock pulse to clock pulse Number of Clock/Data pulses per burst Min 8 Typ 16 2 100 Max 24 Unit ms ms ns 55.5 111 17 64 128 69.5 139 33 µs µs Table 7. Auto Negotiation Parameters October 2007 68 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8841-PMQL supply voltages (3.3V). The reset timing requirement is summarized in the Figure 7 and Table 8. Supply Voltage tsr RST_N Figure 9. Reset Timing Symbol tsr Parameter Stable supply voltages to reset High Min 10 Max Unit ms Table 8. Reset Timing Parameters October 2007 69 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Selection of Isolation Transformers A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit inductance (min) Leakage inductance (max) Inter-winding capacitance (max) D.C. resistance (max) Insertion loss (max) HIPOT (min) Value 1 CT : 1 CT 350µH 0.4µH 12pF 0.9Ω 1.0dB 1500Vrms Table 9. Transformer Selection Criteria 0MHz – 65MHz 100mV, 100kHz, 8mA 1MHz (min) Test Condition The following transformer vender provide compatible transformers for Micrel’s device: Magnetic Manufacturer Pulse Pulse (low cost) Transpower Bel Fuse Delta LanKom TDK (Mag Jack) Part Number H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S TLA-6T718 Auto MDI-X Yes Yes Yes Yes Yes Yes Yes Number of Port 1 1 1 1 1 1 1 Table 10. Qualified Single Port Magnetics Selection of Reference Crystal Characteristics Frequency Frequency tolerance (max) Load capacitance (max) Series resistance Value 25 ±50 20 25 Table 11. Typical Reference Crystal Characteristics Units MHz ppm pF Ω October 2007 70 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Package Information Figure 10. 128-Pin PQFP Package October 2007 71 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL Acronyms and Glossary BPDU CMOS Bridge Protocol Data Unit Complementary Metal Oxide Semiconductor A packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination. A common semiconductor manufacturing technique in which positive and negative types of transistors are combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. A common technique for detecting data transmission errors. CRC for CRC Cyclic Redundancy Check Ethernet is 32 bits long. Cut-Through Switch A switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. A cut-through switch simply reads in the first bit of an incoming packet and forwards the packet. Cut-through switches do not store the packet. Destination Address Direct Memory Access The address to send packets. A design in which memory on a chip is controlled independently of the CPU. A design in which memory on a chip can be erased by exposing it to an electrical charge. A bus architecture designed for PCs using 80x86 processors, or an Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32 bits wide and support multiprocessing. A naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. In computer technology, computer devices are susceptible to EMI because electromagnetic fields are a byproduct of passing electricity through a wire. Data lines that have not been properly shielded are susceptible to data corruption by EMI. See CRC. Specifies the frame identifier. Alternately is the filter identifier. The protocol defined by RFC 1112 for IP multicast transmissions. A time delay between successive data packets mandated by the network standard for protocol reasons. In Ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. IPG is used to correct timing differences between a transmitter and receiver. During the IPG, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity. The disruption of transmitted code caused by adjacent pulses DA DMA EEPROM Electronically Erasable Programmable Readonly Memory Extended Industry Standard Architecture Electro-Magnetic Interference EISA EMI FCS FID IGMP IPG Frame Check Sequence Frame or Filter ID Internet Group Management Protocol Inter-Packet Gap ISI Inter-Symbol Interference Industry Standard Architecture affecting or interfering with each other. ISA Jumbo Packet A bus architecture used in the IBM PC/XT and PC/AT. A packet larger than the standard Ethernet packet (1500 bytes). Large packet sizes allow for more efficient use of bandwidth, lower overhead, October 2007 72 M9999-100407-1.5 Micrel, Inc. less processing, etc. MDI Medium Dependent Interface KSZ8841-PMQL An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' An Ethernet port connection that allows networked end stations (i.e., PCs or workstations) to connect to each other using a null-modem, or crossover, cable. For 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. When connecting two computers together, a cable that crosses the TX and RX is required to do this. With auto MDI-X, the PHY senses the correct TX and RX roles, eliminating any cable confusion. The MIB comprises the management portion of network devices. This can include things like monitoring traffic levels and faults (statistical), and can also change operating parameters in network nodes (static forwarding addresses). The MII accesses PHY registers as defined in the IEEE 802.3 specification. An expansion board inserted into a computer to allow it to be connected to a network. Most NICs are designed for a particular type of network, protocol, and media, although some can serve multiple networks. The Port VLAN ID value is used as a VLAN reference. An electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. A PLL ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency. An occurrence that affects the directing of power to different components of a system. Manages packet traffic between MAC/PHY interface and the system host. The QMU has built-in packet memories for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). The address from which information has been sent. TDR is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. They send a signal down the conductor and measure the time it takes for the signal -- or part of the signal -- to return. Commonly a cable containing 4 twisted pairs of wires. The wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. MDI-X Medium Dependent Interface Crossover MIB Management Information Base MII NIC Media Independent Interface Network Interface Card NPVID PLL Non Port VLAN ID Phase-Locked Loop PME QMU Power Management Event Queue Management Unit SA TDR Source Address Time Domain Reflectometry UTP Unshielded Twisted Pair VLAN Virtual Local Area Network October 2007 73 M9999-100407-1.5 Micrel, Inc. KSZ8841-PMQL MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. October 2007 74 M9999-100407-1.5