SP5669KGMP1S

SP5669 2.7GHz I2C Bus Controlled Synthesiser Preliminary Information DS4852 Issue 2.1 May 1999 Features q q q q q q q q q q Ordering Information SP5669/KG/MP1S (Tubes) SP5669/KG/MP1T (Tape and reel) Complete 2.7GHz single chip system Compatible with UK DTT offset requirements Optimised for low phase noise Selectable divide by two prescaler Selectable reference division ratio Selectable reference/comparison frequency output Selectable charge pump current Four selectable I2C bus address 5–level ADC Pin compatible with the SP5658 3–wire bus controlled synthesiser and SP5659 I2C bus synthesiser and SP5659 I2C bus synthesiser ESD protection; (Normal ESD handling procedures should be observed) The comparison frequency is obtained either from an on–chip crystal controlled oscillator, or from an external source. The oscillator frequency Fref or the comparison frequency Fcomp may be switched to the REF/COMP output. This feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see Fig. 8). The synthesiser is controlled via an I 2 C bus, and responds to one of four programmable addresses which are selected by applying a specific voltage to the ‘address’ input. This feature enables two or more synthesisers to be used in a system. The device contains four switching ports P0–P3 and a 5–level ADC. The output of the ADC can be read via the I2 C bus. The device also contains a varactor line disable and chargepump disable facility. Applications q q Complete 2.7GHz single chip system Optimised for low phase noise Description The SP5669 is a single chip frequency synthesiser designed for tuning systems up to 2.7GHz and offers step size compatible with DTT offset requirements. The RF preamplifier drives a divide by two prescaler which can be disabled for applications up to 2GHz, allowing direct interfacing with the programmable divider so enabling a step size equal to the comparison frequency. For applications up to 2.7GHz the divide by two is enabled, giving a step size of twice the comparison frequency. SP5669 CHARGE PUMP CRYSTAL REF/COMP ADDRESS SDA SCL PORT P3 PORT P2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DRIVE Vee RF INPUT RF INPUT Vcc ADC PORT P0 PORT P1 MP16 Figure. 1 Pin connections - top view 3 REF/COMP Fcomp 13 BIT COUNT Fpd PHASE COMP Fref OSC 2 CRYSTAL 13 RF INPUTS PRE AMP 14 PROGRAMMABLE DIVIDER 2/1 16/17 REFERENCE DIVIDER (see Fig. 3) LOCK DETECT 4 BIT COUNT CHARGE PUMP 1 16 CHARGE PUMP DRIVE C1, C0 PE 1 BIT LATCH 17 BIT LATCH DIVIDE RATIO 2 BIT LATCH 4 BIT LATCH 5 BIT LATCH and MODE CONTROL LOGIC (see Fig. 5) ADDRESS SDA SCL 4 5 6 POR POWER ON DETECT ADC 11 3 BIT ADC 7 PORT P3 8 PORT P2 9 10 I 2C TRANSCEIVER FL FPD /2 MODE CONTROL DISABLE 15 V EE 12 V CC 4 BIT LATCH AND PORT INTERFACE P0 TEST CONTROL PORT P1 PORT P0 Figure. 2 Block diagram 2 SP5669 ELECTRICAL CHARACTERISTICS T amb = –20°C to +80°C, V CC = +4.5V to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristics Supply current, I CC RF input voltage 13, 14100 13,14 50 RF input impedance RF input capacitance SDA, SCL Input High voltage Input Low voltage Input High current Input Low Current LeakageCurrent Input hysteresis SDA Output voltage Charge pump output current Charge pump output leakage Charge pump drive output current Drive output saturation voltage when disabled External reference input frequency External reference input ampltude Crystal frequency Crystal oscillator drive level Recommended crystal series resistance 13, 14 13, 14 5, 6 3 0 50 2 5.5 1.5 10 –10 10 0.8 5 1 1 ±3 0.4 Pin Min 12 58 13, 14 73 40 Value Typ 68 Max 85 Units mA Conditions V CC = 5V prescaler enabled, PE = 1 mAV CC = 5V prescaler disabled, PE = 0 300 mV rms 300MHz to 2.7GHz Prescaled enabled, PE = 1, See Fig. 7b. 300 mV rms 80MHz Prescaler enabled, PE=1, See Fig. 7b. 300 mV rms Ω pF V V µA µA µA V V 80MHz to 2.0GHz Prescaler disabled, PE = 0, See Fig. 7a. Refer to Fig. 13 Refer to Fig. 13 Input voltage = V CC Input voltage = VEE VCC = VEE I sink = 3mA See Fig. 6, V pin = 2V V pin1 = 2V ± 10 nA 16 16 2 2 4 1 350 2 200 16 35 mV 20 500 MHz mV p–p mAV pin16 = 0.7V MHzAC coupled sinewave mV p–pAC coupled sinewave 2 2 10 200 Ω Applies to 4MHz crystal only. ‘Parallel resonant’ crystal. Figure quoted is under all conditions including start up. Includes temperature and process tolerances. AC coupled output. Output enabled,RE=1. See Note 1. Crystal oscillator negative resistance REF/COMP output Voltage 3 2 400 Ω 350 mV p–p 3 SP5669 Electrical Chacteristics (cont.) T amb = –20°C to 80 °C, V CC =+ 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristics Pin Min Comparison frequency Equivalent phase noise at phase detector Value Typ Units Max 2 –148 MHz dBC/Hz 6kHz loop BW, phase comparator freq 250kHz. Figure measured @ 1kHz offset, SSB (within loop band width). Prescaler disabled, PE = 0 Prescaler enabled, PE = 1 See Fig. 3 Conditions RF division ratio Reference division ratio Output ports P0, P1, P2, P3 10 Sink current Leakage current ADC input voltage ADC input current Address input current High Address input current Low 240 480 7,8,9, 131071 262142 10 10 11 11 4 4 ±10 1 –0.5 mA µA µA mA mA V port = 0.7V V port = 13.2V See Table 4, Fig 4 VCC ≥ V input ≥ VEE Input voltage =V CC Input voltage =VEE Note 1: If the REF/COMP output is not used, the output should be left open circuit or connected to V CC , and disabled by setting RE=0. Absolute Maximum Ratings All voltages are referred to VEE at 0V. Characteristics Supply Voltage, V CC RF input voltage RF input DC offset Port voltage Total port current ADC input DC offset REF/COMP output DC offset Charge pump DC offset Drive DC offset Crystal oscillator DC offset Address DC offset SDA and SCL DC offset Storage temperature Junction temperature MP16 thermal resistance chip to ambient chip to case Power consumption at V CC =5.5V ESD protection All 4 Pin 12 13,14 13,14 7–10 7–10 7–10 11 3 1 16 2 4 5, 6 Min 0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –55 Value Max 7 2.5 V CC +0.3 14 6 50 V CC +0.3 V CC +0.3 V CC +0.3 V CC +0.3 V CC +0.3 V CC +0.3 6V +150 +150 111 41 468 Units V V p–p V V V mA V V V V V V V °C °C °C/W °C/W mW kV All ports off, prescaler enabled Mil Std 883 TM 3015 AC coupled as per application Port in off state Port in on state Conditions 4 SP5669 Functional Description The SP5669 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The block diagram is shown in Fig. 2. The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces with the 17–bit fully programmable divider via a divide–by–two prescaler. For applications up to 2GHz RF input, the prescaler may be disabled so eliminating the degradation in phase noise due to prescaler action. The divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4–bits, and the M counter is 13–bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on–board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 15 ratios as detailed in Fig. 3. The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. By invoking the device test modes as described in Fig. 5, the varactor drive output can be disabled so switching the external transistor ’off’ and allowing an external voltage to be written to the varactor line for tuner alignment purposes. Similarly, the charge pump may be also disabled to a high impedance state. The programmable divider output Fpd/2 can be switched to port P0 by programming the device into test mode. The test modes are described in Fig. 5 high Programming The SP5669 is controlled by an I 2 C data bus. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesiser can either accept data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 1 and 2 in Fig. 4 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C bus system. Table 3 in Fig.4 shows how the address is selected by applying a voltage to the ’address’ input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. Write Mode With reference to Table 1, bytes 2 and 3 contain frequency information bits 2 14 –2 0 inclusive. Auxillary frequency bits 2 16 –2 15 are in byte 4. For most frequencies only bytes 2 and 3 will be required. The remainder of byte 4 and byte 5 control the prescaler enable, reference divider ratio (see Fig. 3), charge pump, REF/COMP output (see Fig. 5), output ports and test modes (see Fig. 5). After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic ’0’ indicating byte 2 and a logic ’1’ indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without readdressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous data is retained. 5 SP5669 To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 17 bits of frequency data have been received, or after the generation of a STOP condition. Repeatedly sending bytes 2 and 3 only will not change the frequency. A frequency change occurs when one of the following data sequences is sent to an addressed device; Additional Programmable Features Prescaler enable The divide by two prescaler is enabled by setting bit PE within byte 4 to a logic ’1’. A logic ’0’ disables the prescaler, directly passing the RF input frequency to the 17–bit programmable counter. Bit PE is a static select only. Charge pump current The charge pump current can be programmed by bits C1 and C0 within data byte 5, as defined in Fig. 6. Test mode The test modes are invoked by setting bits RE=0 and RTS=1 within the programming data, and are selected by bits TS2, TS1 and TS0 as shown in Fig. 5. When TS2, TS1 and TS0 are received, the device retains previously received P2, P1 and P0 data. Reference/Comparison frequency output The reference frequency F ref can be switched to the REF/COMP output, pin 3, by setting bit RE=1 and RTS=0 within byte 5. The comparison frequency F comp can be switched to the REF/COMP output, pin 3, by setting bit RE=1 and RTS=1 within byte 5. For RE set to logic ’0’, the output is disabled and set to a high state. RE and RTS default to logic ’1’ during device power up, thus enabling the comparison frequency F comp at the REF/COMP output. Comparison frequency with a 4MHz external reference 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.625kHz 666.67kHz 333.33kHz 166.67kHz 83.33kHz 41.67kHz 20.83kHz 10.42kHz Bytes 2, 3, 4, 5 Bytes 4, 5, 2, 3 or when a STOP condition follows valid data bytes as follows; Bytes 2, 3, 4, STOP Bytes 4, 5, 2 STOP Bytes 2, 3, STOP Bytes 2, STOP Bytes 4, STOP It should be noted that the device must be initially addressed with both frequency AND control byte data, since the control byte contains reference divider information which must be provided before a chosen frequency can be synthesised. This implies that after initial turn on, bytes 2, 3, 4 must be sent followed by a STOP condition as a minimum requirement. Alternatively bytes 2, 3, 4, 5 must be sent if port information is also required. Read Mode When the device is in read mode, the status byte read fromthe device takes the form shown in Table 2, Fig. 4. Bit 1 (POR) is the power–on reset indicator, and this is set to a logic ’1’ if the VCC supply to the device has dropped below 3V (at 25°C), e.g. when the device is initially turned ON. The POR is reset to ’0’ when the read sequence is terminated by a STOP command. When POR is set high (at low V CC), the programmed information is lost and the output ports are all set to high impedance. Bit 2 (FL) indicates whether the device is phase locked, a logic ’1’ is present if the device is locked, and a logic ’0’ if the device is unlocked. Bits 6,7 and 8 (A2, A1, A0) combine to give the output of the ADC. The ADC can be used to feed AFC information to the microprocessor via the I 2 C bus. R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 Not Allowed 6 12 24 48 96 192 384 Figure. 3 Reference division ratios 6 SP5669 ADDRESS PROGRAMMABLE DIVIDER PROGRAMMABLE DIVIDER CONTROL DATA CONTROL DATA MSB 1 0 27 1 C1 1 2 14 26 216 C0 0 2 13 25 215 RE 0 2 12 24 PE RTS 0 2 11 23 R3 P3 MA1 210 MA0 29 LSB 0 28 A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 22 21 20 R2 R1 R0 P2/TS2 P1/TS1 P0/TS0 Table 1 Write data format (MSB is transmitted first) ADDRESS STATUS BYTE MSB 1 POR 1 FL 0 X 0 X 0 X MA1 A2 MA0 A1 LSB 1 A0 A A Byte 1 Byte 2 Table 2 Read data format (MSB is transmitted first) A MA1, MA0 2 16 –2 0 PE R3,R2,R1,R0 C1, C0 RE RTS RTS TS2, TS1, TS0 P0 P3, P2, P1 POR FL A2, A1, A0 X : : : : : : : : : : : : : : : : Acknowledge bit Variable address bits (see Table 3) Programmable division ratio control bits Prescaler enable Reference division ratio select (see Fig. 3) Charge pump current select (see Fig.6) Reference oscillator output enable REF/COMP output select when RE=1 (see Fig.5) Test mode enable when RE=0 (see Fig.5) Test mode control bits (valid when RE=0, RTS=1, see Fig. 5) P0 port output state (always valid except when RE=0, RTS=1) P3, P2 and P1 port output states Power On Reset indicator Phase Lock Flag ADC data (see Table 4) Don’t care A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 Voltage on ADC input 0.6V CC toV CC 0.45V CC to 0.6VCC 0.3V CC to 0.45VCC 0.15V CC to 0.3VCC 0 to 0.15VCC MA1 MA0 Address input voltage level 0 0 0 – 0.1VCC 0 1 Open circuit 1 0 0.4V CC – 0.6VCC # 1 1 0.9V CC – VCC # Programmed by connecting a 15kΩ resistor between pin 4 and VCC Table 3 Address selection Table 4 ADC levels Figure. 4 Data formats 7 SP5669 RE 0 0 0 0 0 0 1 1 X=don’t care Figure. 5 REF/COMP output mode and Test modes RTS 0 1 1 1 1 1 0 1 TS2 X X X X X 1 X X TS1 X 0 0 1 1 X X X TS0 X 0 1 0 1 X X X REF/COMP OUTPUT MODE Disabled to high state Disabled to high state Disabled to high state Disabled to high state Disabled to high state Disabled to high state F ref switched F comp switched Test mode description Normal operation Charge pump sink. Status byte FL = logic ‘1’ Charge pump source. Status byte FL = logic ‘0’ Charge pump disabled. Status byte FL=logic ‘0’ Port P0 = F pd /2 Varactor Drive Output disabled Normal operation Normal operation C1 byte 5, bit 1 0 0 1 1 C0 byte 5, bit 2 0 1 0 1 min ±90 ±195 ±416 ±900 Current in µA typ ±120 ±260 ±555 ±1200 max ±150 ±325 ±694 ±1500 Figure 6. Charge pump current 300 VIN (mV RMS INTO 50 ) 100 50 10 300 VIN (mV RMS INTO 50 ) OPERATING WINDOW 100 50 10 OPERATING WINDOW 80 100 1000 2000 3000 3500 80 300 1000 2000 3000 3500 2700 FREQUENCY (MHz) FREQUENCY (MHz) Figure. 7a Typical input sensitivity (prescaler disabled, PE=0) Figure. 7b Typical input sensitivity (prescaler enabled, PE=1) 8 SP5669 Double Conversion Tuner Systems The high 2.7GHz maximum operating frequency and excellent noise characteristics of the SP5669 enables the construction of double conversion high IF tuners. A typical system shown in Fig.8 will use the SP5669 as the first LO control for full band upconversion to an IF of greater than 1GHz. The wide range of reference division ratios allows the SP5669 to be used both for the up converter LO with a high phase comparator frequency (hence low phase noise) and the down converter which utilises the device in a lower comparison frequency mode (which offers a fine step size). 50–900MHz 1.6GHz 38.9MHz 1650–2700MHz Reference Clock First LO SP5659 SP5669 Second LO SP5659 SP5669 Figure. 8 Example of double conversion from VHF/UHF frequencies to TV IF +30V 4MHz 18pF 68pF 15nF 13k3 BCW31 Optional application utilising on–board crystal controlled oscillator 1 2 3 16 15 14 +5V +12V 22k 16k 47k 2n2 REF 10n ADDRESS SDA SCL P3 P2 1n 1n OSCILLATOR OUTPUT 10n TUNER CONTROL MICRO 4 5 6 7 8 SP5669 SP5659 13 12 11 10 9 ADC P0 P1 Figure. 9 Typical appliction Application Notes A generic set of application notes AN168 for designing with synthesisers such as the SP5659 has been written. This covers aspects such as loop filter design and decoupling. This application note is also featured in the Media Data Book, or refer to the Mitel Semicondor Internet Site http://www.gpsemi.com. A generic test/demo board has been produced which can be used for the SP5669. A circuit diagram and list of components for the board is shown in Figs. 10 and 11. The board can be used for the following purposes: (A) Measuring RF sensitivity performance. (B) Indicating port function. (C) Synthesising a voltage controlled oscillator. (D) Testing of external reference 9 SP5669 P2 +30V +5V C8 EXTERNAL REFERENCE SKT2 C6 10nF* *(NOT FITTED) C3 68pF R7 22K R8 R6 13K3 1 2 16 15 14 13 12 11 10 9 +12V C9 C7/C8/C9 = 100nF C7 R9 47K C12 2n2F RF INPUT C5 1nF C10 1nF SKT1 VAR GND C2 15nF 16K T1 2N3904 C4 1nF X1 4MHz C1 P1 DISABLE / REF ENABLE DATA / SDA CLOCK / SCL C13 100pF C14 100pF 18pF 3 4 5 6 7 8 R1 4K7 R2 4K7 R3 4K7 R4 4K7 D1 D2 D3 D4 C11 1nF R5 4K7 D5 LOCK NOTE : The circuit diagram shown is designed for use with a number of synthesisers. 1 The LED connected to pin 1. is redundant when a SP5669 is used in this board. SP5659 Figure. 10 Test board Figure. 11 Test board (layout) 10 SP5669 Loop Bandwidth The majority of applications for which the SP5669 is intended require a loop filter bandwidth of between 2kHz and10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped. There are two ways of achieving a higher phase comparator sampling frequency:– A) Reduce the division ratio between the reference source and the phase comparator B) use a higher reference source frequency. Approach B) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. Driving Two Devicesfrom A Common Reference As mentioned earlier in the Datasheet, the SP5669 has a REF/COMP output which allows two synthesisers to be driven from a common reference. To do this, the ‘‘Master” should be programmed by setting RE = 1 and RTS = 0. The driven device should be programmed for normal operation i.e. RE = 0, and RTS = 0. The two devices should be connected as shown below. Reference Source The SP5669 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase noise within the loop bandwidth is: phase comparator LO frequency noise floor + 20 log 10 phase comparator frequency ( ) Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO to phase comparator division ratio is a minimum. 11 SP5669 4MHz 18pF 1 2 3 16 15 14 1nF 1 2 3 4 5 6 7 8 16 15 14 SP5669 SP5659 4 5 6 7 8 13 12 11 10 9 SP5669 SP5659 +j2 13 12 11 10 9 Fig. 12 Driving two devices from a common reference +j1 +j0.5 +j0.2 +j5 0 0.2 0.5 1 2 5 X –j0.2 X X –j5 S11:Z0 = 50 NORMALISED TO 50 –j0.5 –j1 X –j2 FREQUENCY MARKERS AT 100MHz, 500MHz, 1GHz AND 2.7GHz Figure. 13 typical RF input impedance 12 SP5669 VREF VCC 500 500 CHARGE PUMP RF INPUTS 200 OS (Output disable) 100 DRIVE OUTPUT RF inputs V CC Loop amplifier PORT SCL/SDA/ADC 3k ACK SDA ONLY SDA and SCL and ADC Output Ports VCC VCC 30k ADDRESS CRYSTAL VCC REF/COMP 3k enable/ disable 10K Reference oscillator Address input REF/COMP output Figure. 14 Input/Output interface circuits 13 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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