SP5748KGMP1T

SP5748 2.4GHz Very Low Phase Noise PLL Advance Information DS4875 - 1.3 November 1998 The SP5748 is a single chip frequency synthesiser designed for tuning systems up to 2.4 GHz and is optimized for low phase noise with comparison frequencies up to 4 MHz. It is designed to be downwards software compatible with the SP5658. The RF programmable divider contains a front end dual modulus 16/17 functioning over the full operating range and allows for coarse tuning in the upconverter application and fine tuning in the downconverter. Comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. a buffered reference frequency output is also available to drive a second SP5748. The device also contains 2 switching ports. CHARGE PUMP CRYSTAL CAP CRYSTAL ENABLE DATA CLOCK PORT P1/OC 14 SPOT REF. DRIVE VEE RF INPUT RF INPUT VCC REF PORT P0/OP MP14 Figure1 Pin connections - top view APPLICATIONS FEATURES q Complete 2.4 GHz single chip system (for faster device refer to to SP5768) q Optimised for low phase noise, with comparison frequencies up to 4 MHz q No RF prescaler q Selectable reference division ratio q Reference frequency output q Selectable charge pump current q Integrated loop amplifier q Two switching ports q Low power replacement for SP5658 and 5668 q Downwards software compatible with SP5658 q ESD protection, (Normal ESD handling procedures should be observed) q TV, VCR and Cable tuning systems q Communications systems ORDERING INFORMATION SP5748/KG/MP1S (Tubes) SP5748/KG/MP1T (Tape and Reel) SP5748 Advance Information REF 13 BIT COUNT RF INPUT 16/17 4 BIT COUNT REFERENCE DIVIDER CRYSTAL PUMP DRIVE 17 BIT LATCH 6 BIT LATCH DATA CLOCK ENABLE DATA INTERFACE 3 BIT LATCH & PORT/ TEST MODE INTERFACE PORT P0/OP PORT P1/OC Figure 2 SP5748 block diagram ELECTRICAL CHARACTERISTICS These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40°C to 80°C, VCC = +4·5V to +5·5V Characteristic Pin Min Supply current 10 80 30 Value Typ 13 2400 300 Units Max mA MHz mV rms See Figure 3 Conditions RF input frequency range 11,12 RF input voltage RF input impedance Data, clock & enable input high voltage input low voltage input current hysterysis 11,12 11,12 5,6,4 3 0 -10 0.8 Vcc 0.7 10 V V µA V PP All input conditions 2 SP5748 Advance Information ELECTRICAL CHARACTERISTICS (continued) These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40°C to 80°C, VCC =+ 4·5V to +5·5V Characteristic Pin Min Clock rate Bus timing data set up data hold enable set up enable hold clock to enable Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal 1 6 5,6,4 300 600 300 600 300 Value Typ Units Max 500 kHz See Figure4 ns ns ns ns ns See Figure 5, Vpin1 = 2V +-3 +-10 nA Vpin1=2V Conditions 1 14 0.5 mA Vpin 14=0.7V 2,3 2 10 20 200 MHz Ω o ppm/ C See Figure 6 for application 4 MHz parallel resonant crystal. series resistance Oscillator temperature stability Oscillator supply voltage stability External reference input frequency External reference drive level Buffered reference frequency output * output amplitude output impedance 9 0.35 TBC 2 2 TBC TBC ppm/V 20 MHz Sinewave coupled through TBA nF blocking capacitor Sinewave coupled through TBA nF blocking capacitor AC coupled 2 0.2 0.5 Vpp Vpp Ω 2-20MHz 3 SP5748 Advance Information ELECTRICAL CHARACTERISTICS These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40°C to 80°C, VCC = +4·5V to +5·5V Characteristic Pin Min Value Typ Max Units Conditions Comparison frequency Equivalent phase noise at phase detector -148 4 MHz dBc/Hz @10 kHz, SSB, with 2 MHz comparison from 4 MHz crystal reference RF division ratio Reference division ratio Output ports P0-P1# sink current leakage current 7, 8 240 131071 see figure (7) 2 10 µA mA Vport = 0.7V Vport = Vcc * Reference output disabled by connecting to Vcc if not required ’ Output ports high impedance on power up, with data, clock and enable at logic 0 4 SP5748 Advance Information ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V Characteristic Supply voltage, Vcc RF input voltage RF input DC offset Port voltage Charge pump DC offset Varactor drive DC offset Crystal DC offset Buffered ref output Data, clock & enable DC offset Storage temperature Junction temperature MP14 thermal resistance, chip to ambient chip to case Power consumption at Vcc=5.5V ESD protection Pin 10 11,12 11,12 7,8 1 14 2,3 9 5,6,4 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 Min -0.3 Typ Max 7 2.5 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 +125 +150 81 27 TBC 2 Units V Vp-p V V V V V V V °C °C °C/W °C/W mW kV All ports off Mil-std 883B latest revision method 3015 cat.1. Differential across pins 11 and 12 Conditions Functional description The SP5748 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. The package and pin allocation is shown in Figure 1 and the block diagram in Figure 2. The SP5748 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. The programming word contains 26 bits, two of which are used for port selection, 17 to set the programmable divider ratio, four bits to select the reference division ratio, bits RD & R0-R2, see Figure 7, two bits to set charge pump current, bit C0 and C1, see Figure 5, and the remaining bit to access test modes, bit T0, see Figure 8. The programming format is shown in Figure 4. The clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the 17 bit fully programmable counter, which is of MN+A architecture. The M counter is 13 bit and the A counter 4 The output of the programmable counter is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as descried in Figure 7. The output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump current setting is described in Figure 5, A buffered crystal reference frequency suitable for driving further synthesisers is available from pin 9. If not required this output can be disabled by connecting to Vcc The programmable divider output divided by 2, Fpd/2 and comparison frequency, Fcomp can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Figure 8. 5 SP5748 Advance Information +j1 +j0.5 +j2 +j0.2 +j5 0 1 -j0.2 S11 : Zo = 50Ω Normalised to 50Ω -j0.5 -j1 4 3 2 -j5 Frequency Markers at 500MHz, 1GHz, 1.5GHz and 2.4GHz -j2 Figure 3 RF input impedance CLOCK ENABLE DATA 225 P1 224 P0 223 T0 222 C1 221 C0 220 R2 219 R1 218 R0 217 RD 216 20 MSB LSB Frequency data TIMING DIAGRAM TBC 2^16 to 2^0 R2,R1,R0 RD P1,P0 C1,C0 T0 : : : : : : Programmable divider ratio control bits Reference divider control bits Reference divider mode select Port control bits Charge pump current select Test mode enable Figure 4 Data format C1 0 0 1 1 C0 0 1 0 1 Current (in mA) 0.2 0.9 .1 .45 Figure 5 Charge pump current 6 SP5748 Advance Information 2 SP5748 3 Figure 6 Crystal oscillator application RD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Figure 7 Reference division ratio R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RATIO 2 4 8 16 32 64 128 256 3 5 10 20 40 80 160 320 P1 X 0 0 1 1 X = don't care P0 X 0 1 0 1 T0 0 1 1 1 1 FUNCTIONAL DESCRIPTION Normal operation Charge pump sink Charge pump source Charge pump disable Port P1 = Fcomp, P0 = Fpd/1 Figure 8 Test modes 7 SP5748 Advance Information 300 VIN (mV RMS INTO 50Ω) OPERATING WINDOW 30 10 80 1000 2400 FREQUENCY (MHz) Figure 9 Typical input sensitivity 50 - 900MHz 1.6GHz 38.9MHz 1650-2700MHz 1650 -2400MHz 2 3 SP5748 VCO 3 10 10nF Figure 10 Example of double conversion from VHF/UHF frequencies to TV IF SP5748 VCO 18pF 2 39pF 3 4MHz +30V 68pF 15nF 13k3 BCW31 22k +5V +12V 16k 47k 2n2 Optional application utilising on–board crystal controlled oscillator 1 2 14 13 REFERENCE CONTROL MICRO ENABLE DATA CLOCK P1 1n 1n OSCILLATOR OUTPUT 10n P0 TUNER 4 5 6 7 SP5748 3 12 11 10 9 8 Figure 11 Typical application SP5748 8 SP5748 Advance Information APPLICATION NOTES A generic set of application notes AN168 for designing withsynthesisers such as the SP5748 has been written. This covers aspects such as loop filter design and decoupling. Thisapplication note is also featured in the Media Data Book, or refer to the Mitel Semiconductor Internet Site http://www.Mitelsemi.com. A generic test/ demo board has been produced which can be used for the SP5748. A circuit diagram is shown in Figure 12. The board can be used for the following purposes: (A) Measuring RF sensitivity performance. (B) Indicating port function. (C) Synthesising the voltage controlled oscillator. (D) Testing of external reference. (E) Measurement of phase noise performance. REFERENCE SOURCE The SP5748 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase noise within the loop bandwidth is: phase comparator LO frequency noise floor + 20 log 10 phase comparator frequency ( ) Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO to phase comparator division ratio is a minimum. There are two ways of achieving a higher phase comparator sampling frequency:– A) Reduce the division ratio between the reference source and the phase comparator B) use a higher reference source frequency. Approach B) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. LOOP BANDWIDTH The majority of applications for which the SP5748 is intended require a loop filter bandwidth of between 2kHz and10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped. 9 W 18pF 39pF 1 2 CP Drive Output VEE C5 1nF 12 11 C4 10 9 VCC 8 R11 16R 1nF R13 16R R12 16R 13 XTAL CAP XTAL ENA RF Input VCC REF OUT P0 DATA CLK P1 RF Input 14 T1 BCW31 2 3 4 5 6 C14 4n7F C18 IC1 SP5748 1K 0R 1 2 8V RF INPUT RF1 C20 1nF C19 100pF 1 +8V 8 C6 1 R6 POT2 1 LK2 LK 2 X1 4MHz 10nF VT RF OUT Clock GND Enable Data 6 5 4 3 3 WIRE BUS R1 S1 1 2 4 3 4K7 R4 4K7 SW DIP-2 C17 10nF 7 LED1 C21 2 HLMPK-150 1 LK1 LK 1nF R14 68R C12 C13 C15 100pF 100pF 100pF HLMPK-150 LED2 8V C11 1nF J4 1 2 RF3 COMP O/P PORT OUTPUTS Figure 12 Evaluation Board 2 10 C7 C10 C16 100nF 100pF 4u7F VCC J1 +5V +22V +8V 1 2 3 4 5 C9 100nF R8 22K C8 4u7F 8V POWER CONNECTOR SP5748 Advance Information R7 13K3 C3 LK2 TO BE FITTED FOR NORMAL OPERATION NF C2 2n2F R9 R10 C1 POS-2000 TUNING RANGE = 1370MHz - 2000MHz J2 VARACTOR RF2 EXT REF POS_2000 GND 7 J5 POS_2000 SP5748 Advance Information Top view Bottom view Figure 13 11 SP5748 Advance Information VREF VCC 500 500 CHARGE PUMP RF INPUTS 200 DRIVE RF inputs Loop amplifier VCC PORT 25K BIAS Disable, Enable, Data and Clock inputs Output Ports VCC VCC CRYSTAL REF CRYSTAL CAP 1.2mA Reference oscillator Reference output Figure 14 Input/Output interface cicruits 12 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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