VP7615

VP7615 Colour Digital Video Camera Decoder IC Advance Information Supersedes February 1997 edition, DS4602 - 2.4 DS4602 - 3.1 August 1997 The VP7615 iCamHost™ Processor chip can decode the signals from a variety of iVision™ compatible digital video cameras (such as Silicon Vision’s iCam™) and process them for use in a host computer system. Digital cameras can offer real cost and performance gains in applications which require a digital video input, and iVision technology realises both these benefits. In a typical analog camera the digitised output from the CCD imager is normally encoded into an analog composite video signal which then has to be redigitised at the input to the host system. By employing the iVision approach the output from the camera is maintained as a digital signal, but in a format which allows for a low cost 9wire connection to the host. Eliminating the unnecessary conversion to an analog signal and back again not only saves cost, but also avoids any possible degradation of image quality. Other benefits include direct control of the camera from the host and the ability to power the camera from the host system so saving the cost of a separate power supply. The VP7615 supports two software selectable CamPort™ interface ports, either of which can receive the digital video from an iVision™ compatible digital video camera. The output is a standard colour digital video signal, similar to standard composite analog-digital decoder chips such as the Philips SAA7110 and SAA7111. All iCamHost™ operating modes are controlled by the host PC via an I2C interface. Hardware I/O controls include output enable and I2C address offset. NOTE: iCamTM, CamPort™ and iCamHost™ are trademarks of Silicon Vision, Inc., Fremont, CA FEATURES I Accommodates different camera configurations based on a variety of CCD imager resolutions I Requires only a small, low-cost 9 pin mini-DIN to connect to camera I Receives the image signal from the camera in digital form at a frame rate determined by the host I Decodes all necessary synchronisation and clock signals from the digital data stream I Programmable gamma correction curve in RGB colourspace I Programmable colour-separation matrix I Collects image status data within user-defined rectangular gated zone of CCD sensor I Programmable horizontal and vertical aperture correction I Pin-strap selectable output format in 16 bit YUV 4:2:2 or 8 bit CCIR 656 YUV 4:2:2 I Test pattern generator for SMPTE colourbars I Bypass mode to output unprocessed 8 bit CCD pixel samples in the luminance channel I Dual iCamPort™ camera input ports, software selectable I Completely iVision™ Compatible I Eight general purpose I/O pins for board level configuration control and/or status I Programmable polarity for HSYNC, VSYNC, HACT & VACT control outputs I Chip pinout is backwards compatible with VP7610 ORDERING INFORMATION VP7615 CG FP1N VP7615 3 ADDRESS OFFSET I2C CLK,DATA CAMPORT A CAMPORT B 5 SERIAL BUS CONTROLLER 2 5 DEMUX & SYNC RECOVERY CLK1X, CLK2X CTRL RAM CONTROL CMYG PIXEL SEPARATOR TWO HORIZONTAL LINE DELAY FIFO RAM CTRL COLOUR MATRIX CONVERTER RGB APERTURE CORRECTION CTRL TO SERIAL BUS CONTROLLER MODULE GAMMA CORRECTION CTRL COLOURSPACE CONVERSION CHROMINANCE & LUMINANCE METRICS Y UV CTRL CHRO MINANCE SUB-SAMPLING AND FILTERING CTRL OUTPUT ENA BLE O UTPUT FORMATTER CTRL BFLAG, FIELD 8 BIT CCIR656/ VSYNC,HSYNC, 16 BIT CCIR601 VACT, HACT Fig.1 Functional Block Diagram 2 VP7615 THEORY OF OPERATION General Overview The VP7615 iCamHost™ is a fully synchronous real-time pipeline pixel processor for converting digitized CCD photosite samples into co-sited, colour calibrated, gamma corrected and aperture corrected digital video in an industryconventional format similar to analog video decoders. The VP7615 supports the full iVision™ Command Set for control of camera head functions such as frame rate, resolution, exposure and colour depth via the CamPort™ Interface. 2 Access to all registers and functions is provided by an I C state machine. Demux and sync recovery The incoming CCD photosite bytes come in a single nibble at a time in a “big-endian” fashion from one of two CamPort™s. These nibbles are clocked in via a separate pixel clock signal. The formatting signals such as start of active video, end of active video, and start of new frame are all encoded into the nibble stream. The output is an 8 bit byte of CCD sample for each pixel clock, as well as separate horizontal and vertical sync signals. RAM control & 2H line delay FIFO RAM Since the iCamHost™ assumes an interlaced scanning CCD with a CMYG colour mosaic format, the colour content is derived from different locations around where the output video pixel is desired. Specifically, the first line from the CCD contains “red-like” colour content, alternating with the following line containing “blue-like” colour content. The third line is real-time, and the first opportunity to output properly cosited luminance and chrominance as though the colour pixels were superimposed upon themselves, all on the second line. Pixel separator Since the colourspace converter requires the 3 most recent lines of CCD data, this block handles the shuffling of either the 2 red and 1 blue line, or 2 blue and 1 red line of data. Colour matrix converter The input to this converter is derived from the relative sums and differences of the above 3 lines of sample data, and processes them through a programmable 3x3 matrix multiplier. The output is colour-separated and calibrated RGB samples. Gamma corrector Since CRT monitors have a non-linear RGB intensity response to input signal, gamma correction must be performed in RGB space as well to prevent cross-coupling errors between luminance and chrominance. This block is a programmable 16 line-segment curve generator to provide not only gamma correction, but any arbitrary contiguous curve of positive slope, with end points at any level to adjust contrast and range. Colourspace converter Since the output of the processor is to be YUV and not RGB, a fixed-coefficient 3x3 matrix converter is used. Chrominance sub-sampling & filtering Spatial sub-sampling and filtering is performed since the output sampling format must be reduced from 4:4:4 to 4:2:2 because most video systems do not require more chrominance data for video camera input. Output formatter Devices taking digital video input such as capture, graphics and compression chips usually require the YUV to be formatted either in CCIR601 16 bit mode (YU then YV) or CCIR656 8 bit mode(U then Y then V then Y). The output mode (8 vs 16 bit) CCIR601 is pin-strap selectable. Additional control register bits may be used to swap the luma and chroma data or to swap the order of U and V data to support the video input requirements of a variety of bus master or graphics chip video interfaces without external glue logic. The polarity of VSYNC, HSYNC, VACT and HACT is also programmable. An output enable input signal may be used when “bussing” the output with other video decoders. Other useful signals such as field and colour flags are also provided. Timing diagrams illustrating the function of the video outputs at different time scales are given in figures 5 to 8. Aperture corrector Since both the luminance and chrominance are derived from spatially spread pixels and the ideal output would be as though all the pixels were superimposed upon one another, a programmable vertical and horizontal aperture correction can be applied to either “soften” or “sharpen” the image. Scene-sensing luminance and chrominance metrics There are no hard-wired closed-loop control circuits in the processor. To achieve great flexibility in control over the behavior of the camera head and processor system, a userdefined region of interest is programmed which provides statistical information about the field of video only within that region. Peak luminance, total luminance, total red chrominance and total blue chrominance are provided and updated after each field. Serial bus control To provide read-write control over the registers within the processor, a standard I2C state-machine is provided. Its address may be offset by 3 bits to preclude address conflicts. 3 VP7615 PERFORMANCE PARAMETER CCD Resolution Field Rate Video Sample Rate Video Sample Quantisation Control Signals Configuration Inputs Gamma Correction Output Format Output Colourspace Output Signals Power Consumption MAXIMUM VALUE OR SPECIFICATION Up to 768 pixels per line Up to 60 fields per second 30 MHz. max. input clock rate, 15MHz. max. output clock rate 8 bit samples in 2 nibbles of 4 bits each Standard I2C protocol I2C address offset, output enable Programmable via 16 arbitrary connected line segments CCIR601 compliant 4:2:2 digital video, pixels per line=CCD pixels YCrCb luminance & chrominance 16 bit digital video, H & V sync, 1X & 2X clock, field ID, chroma ID 950mW STATUS REGISTERS FUNCTION Gated Luminance Sum Gated Luminance Peak Gate Red Chrominance Sum Gated Blue Chrominance Sum SIZE 32 bits 8 bits 32 bits 32 bits DESCRIPTION Sum of luminance values within gated zone Value of peak luminance pixel(s) within gated zone Sum of red chrominance values within gated zone Sum of blue chrominance values within gated zone CONTROL REGISTERS FUNCTION Colour Calibration Matrix Gating Zone Start Pixel Gating Zone End Pixel Gamma Correction Horiz. Aperture Correction Vert. Aperture Correction Processor bypass CamPortTM select Test pattern generator SIZE 78 bit 16 bits 16 bits 128 bit 4 bits 4 bits 2 bits 1 bit 1 bits DESCRIPTION 9x9 bit signed coefficients converting CMYG to RGB 8 bits for column # and for row #, in 4 pixel increments 8 bits for column # and for row #, in 4 pixel increments Locus of 16 points of 8 bits each forms many curves 00H = 0%, 40H = +100%, 70H = +175%, F0H= -175% 00H = 0%, 40H = + 50%, 70H = + 87%, F0H= - 87% 0=normal, 1=pass raw 8 bit samples to Y output pins 0=port A, 1=port B 0=live video, 1=colourbars 4 VP7615 SIGNALS & PINOUT Pin # 60 54 55 56 59 88 84 85 86 87 91 I/O In* In* In* In* In* In* In* In* In* In* Out Name CPCKA CPDA3 CPDA2 CPDA1 CPDA0 CPCKB CPDB3 CPDB2 CPDB1 CPDB0 CPSEL Description Clock - This input receives the clock from the CamPort™ camera on port A. CamPort™ Data Bit 3 - This bus receives the data from the CamPort™ camera on port A. CamPort™ Data Bit 2 - Port A CamPort™ Data Bit 1 - Port A CamPort™ Data Bit 0 - Port A CamPort™ B Clock - This input receives the clock from the CamPort™ camera on port B. CamPort™ B Data Bit 3 - This bus receives the data from the CamPort™ camera on port B. CamPort™ B Data Bit 2 CamPort™ B Data Bit 1 CamPort™ B Data Bit 0 CamPort™ Select Status - When this output is low, the data from CamPort™ A is being used, when this output is high, the data from CamPort™ B is being used. This pin is controlled by Bit 3 of the Configuration Register (sub-address = 0x00). Reset Not - When this Schmidtt trigger input is low, the chip is placed into a known state. When this input is high, the chip can operate. Luminance Out bit 7 - When CCSEL is low this bus carries the luminance data. When CCSEL is high this bus carries multiplexed luminance and chrominance data Luminance Out bit 6 Luminance Out bit 5 Luminance Out bit 4 Luminance Out bit 3 Luminance Out bit 2 Luminance Out bit 1 Luminance Out bit 0 Chrominance Out bit 7 - When CCSEL is low this bus carries the chrominance data. When CCSEL is high this bus carries a constant value of 0x80 (128). Chrominance Out bit 6 Chrominance Out bit 5 Chrominance Out bit 4 Chrominance Out bit 3 Chrominance Out bit 2 Chrominance Out bit 1 Chrominance Out bit 0 Clock Out 2X - This clock runs at twice the pixel rate Clock Out 1X - This clock runs at the pixel rate. Output Enable - When this input is low, the signals YY[7..0], UV[7..0], HSYNC, VSYNC, CLK2, CLK1, HACT, VACT, FIELD and BFLAG are driven. When this input is high, these signals are high-impedance. 44 11 10 9 6 5 4 3 2 23 22 21 20 17 16 15 14 24 27 34 In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In RSTN YY7 YY6 YY5 YY4 YY3 YY2 YY1 YY0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 CLK2 CLK1 OUTEN * CamPort inputs are TTL levels. All other inputs are CMOS. See Static Electrical Characteristics table. 5 VP7615 12 Out VSYNC Vertical Sync - This signal goes active for 3 horizontal lines to mark the beginning of each field. In Odd fields, it starts and ends when HSYNC and HACT are low. In Even fields, it starts and ends when HSYNC and HACT are active. This signal’s polarity is programmable, but defaults to active low on reset. Horizontal Sync - This signal goes active and returns inactive in the horizontal blanking interval to mark the beginning of each line. This signal’s polarity is programmable, but defaults to active low on reset. Horizontal Active - This signal is active when there is valid video data on the luminance and chrominance busses. Data is valid only when this signal and VACT are active. HACT can be programmed to only go active on active lines (HACT = HACT AND VACT), but defaults at reset to active on all lines. This signal’s polarity is also programmable, but defaults to active high on reset. Vertical Active - This signal is active when there is valid video data on the luminance and chrominance busses. Data is valid only when this signal and HACT are active. VACT can be programmed to only go active on active lines during active pixels (VACT = HACT AND VACT), but defaults at reset to active for entire lines only. This signal’s polarity is also programmable, but defaults to active high on reset. Field Flag - This signal indicates the field. When it is low, the field is odd. When it is high, the field is even. Blue Flag - This signal indicates when Blue chrominance data is on the chrominance bus. CCIR 656 Select - When this input is high, the YY[7..0] bus carries multiplexed luminance and chrominance data in conformance with CCIR 656. When this signal is low, the YY[7..0] bus carries only luminance data. Register Clock - This input clocks the control circuitry in the chip and must be running in order to access the registers via the I2C bus. The frequency on this input should be between 10 and 33 MHz. Inverter In - This CMOS Schmidt trigger input controls the INVO output. This inverter can be used to form an RC oscillator to drive the input RCLK. It is typically connected through a resistor to INVO and through a capacitor to GND. This oscillator has a period roughly equal to the time constant R*C. Inverter Out - This signal outputs the opposite level from that applied to INVI. If this inverter is used to form an RC oscillator, this pin would be connected to RCLK. Oscillator Crystal Input - The crystal oscillator is another way to produce a clock for the input RCLK. A crystal is connected between this input and OSXO. Oscillator Crystal Output - A crystal is connected between this output and OSXI. Oscillator Output - If the crystal oscillator is used to produce the register clock, this CMOS output drives the RCLK input. I2C Address Select Bit 3 - The IAD[3..1] inputs select the I2C address that the chip will respond to. The address is 0x60 + 8 * IAD3 + 4 * IAD2 + 2 * IAD1. I2C Address Select Bit 2 I2C Address Select Bit 1 Serial Data In - This input is connected to the I2C Data line. It may be connected through a filter to reduce noise susceptibility. Serial Data Out - This open-drain output connects directly to the I2C Data line. Serial Data Monitor - This output is low when the SDAO output is driving low. This output is high when the SDAO output is high impedance. Serial Clock In - This input is connected to the I2C Clock line. It may be connected through a filter to reduce noise susceptibility. 13 Out HSYNC 28 Out HACT 29 Out VACT 30 31 35 Out Out In FIELD BFLAG CCSEL 36 In RCLK 38 In INVI 37 42 41 39 45 43 40 48 47 46 49 Out In Out Out In In In In Out Out In INVO OSXI OSXO OSCO IAD3 IAD2 IAD1 SDAI SDAO SDMN SCLI 6 VP7615 89 Out SCLOA Serial Clock Out Port A - This output drives the level on the SCLI input when the CamPort™ A is selected. When the CamPort™ B is selected this output is driven high. This is not an open-drain output. Serial Clock Out Port B - This output drives the level on the SCLI input when the CamPort™ B is selected. When the CamPort™ A is selected this output is driven high. This is not an open-drain output. General Purpose I/O Bit 7 - This bus represents eight general purpose I/O pins. Each bit may programmed to be an input or an ouput; on reset, all GPIO pins default to high impedance (tri-state) inputs. General Purpose I/O Bit 6 General Purpose I/O Bit 5 General Purpose I/O Bit 4 General Purpose I/O Bit 3 General Purpose I/O Bit 2 General Purpose I/O Bit 1 General Purpose I/O Bit 0 Test Pin - This pin should be tied low. Test Pin - This pin should be tied low. Test Pin - This pin should be tied low. Test Pin - This pin should be tied low. Test Pin - This pin should be tied low. Test Output Enable - This pin should be tied high. Test Outputs - These pins should be unconnected. 90 Out SCLOB 99 Out GPIO7 98 97 96 95 94 93 92 52 53 61 62 63 71 Out Out Out Out Out Out Out In In In In In In GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 TST0 TST1 TST2 TST3 TST4 TSTOE TOUT 64, 65, 66, Out 67, 70, 72, 73, 74, 77, 78, 79, 80, 81, 1, 7, 19, 25, 32, 51, 57, 69, 75, 82, 8, 18, 26, 33, 50, 58, 68, 76, 83, 100 In GND Power In VDD Power 7 VP7615 REGISTER DESCRIPTIONS The VP7615 iCamHost™ processor station address is strap-configurable to any even location between 0x60 and 0x6E inclusive. Since most iCam cameras currently built use the Station Address 0x68, it is recommended that the iCamHost™ be strapped to a different address. The register addresses shown below are the sub-addresses written to the iCamHost™ immediately after the Station Address. The 7 LSBs of the sub-address must match the specified address. The MSB of the sub-address controls the auto-increment feature of the iCamHost™. If the MSB of the sub-address is a ‘1’, (sub-addresses 0x80 through 0xFF), the sub-address register in the iCamHost™ is incremented to the next address immediately after the data register is read or written. If the MSB of the sub-address is a ‘0’, (sub-addresses 0x00 through 0x7F), the sub-address register in the iCamHost™ remains constant regardless of any reads or writes to the data register. All registers default to 0x00 following chip reset unless otherwise noted. Address 0x00 Configuration Control Register Read/Write 7 0 6 0 Bits 7 - 4 Bit 3 5 0 4 0 3 Cfg3 2 Cfg2 1 Cfg1 0 Cfg0 Always read as ‘0’ Cfg3 - Camera Input Port Enable ‘1’ CamPort™ ‘B’ is source ‘0’ CamPort™ ‘A’ is source Cfg2 - Colour Bar Enable ‘1’ Colour Bar Test Pattern Output ‘0’ Normal Video Output Cfg1 - RGB to YUV Converter Bypass ‘1’ Green + BnR Pattern Output ‘0’ Normal YUV Output Cfg0 - Separator Bypass ‘1’ Sum = CCD Data, Diff = 0 ‘0’ Normal Separator Output Bit 2 Bit 1 Bit 0 Address 0x01 RESERVED Address 0x02 Peak Luma Filter Control Register Read/Write 7 0 6 0 Bits 7 - 3 Bits 2 - 0 5 0 4 0 3 0 2 PLF2 1 PLF1 0 PLF0 Always read as ‘0’ Peak Luma Filter Control ‘000’ - PLF K = 1, No Luma Filter ‘001’ - PLF K = 1/2, Fast Luma Filter ‘010’ - PLF K = 1/4, Med Fast Luma Filter ‘011’ - PLF K = 1/8, Med Slow Luma Filter ‘1XX’ - PLF K = 1/16, Slow Luma Filter Address 0x03 RESERVED Address 0x04 Horizontal Start Register Read/Write 7 HStrt7 6 HStrt6 5 HStrt5 4 HStrt4 3 2 1 0 HStrt3 HStrt2 HStrt1 HStrt0 Bits 7 - 0 Horizontal Start Register Four times the value of this register is the Horizontal starting pixel for the Metrics window. 8 VP7615 Address 0x05 Horizontal Stop Register Read/Write 7 6 5 4 3 2 1 0 HStop7 HStop6 HStop5 HStop4 HStop3 HStop2 HStop1 HStop0 Bits 7 - 0 Horizontal Stop Register Four times the value of this register is the Horizontal ending pixel for the Metrics window. Read/Write Address 0x06 Vertical Start Register 7 VStrt7 6 VStrt6 5 VStrt5 4 VStrt4 3 VStrt3 2 VStrt2 1 VStrt1 0 VStrt0 Bits 7 - 0 Vertical Start Register Four times the value of this register is the Vertical starting line (in the frame) for the Metrics window (two times in the field). Read/Write Address 0x07 Vertical Stop Register 7 6 5 4 3 2 1 0 VStop7 VStop6 VStop5 VStop4 VStop3 VStop2 VStop1 VStop0 Bits 7 - 0 Vertical Stop Register Four times the value of this register is the Vertical ending line (in the frame) for the Metrics window (two times in the field). Read/Write Address 0x08 Horizontal Aperture Control Register 7 HApt7 6 HApt6 5 HApt5 4 HApt4 3 0 2 0 1 0 0 0 Bits 7 Horizontal Aperture Sign Bit ‘1’ Correction is negative (blurring) ‘0’ Correction is positive (sharpening) Horizontal Aperture Control Value ‘000’ - No Aperture Correction | ‘111’ - Maximum Aperture Correction Always read as ‘0’ Read/Write Bits 6 - 4 Bits 3 - 0 Address 0x09 Vertical Aperture Control Register 7 VApt7 6 VApt6 5 VApt5 4 VApt4 3 0 2 0 1 0 0 0 Bits 7 Vertical Aperture Sign Bit ‘1’ Correction is negative (blurring) ‘0’ Correction is positive (sharpening) Vertical Aperture Control Value ‘000’ - No Aperture Correction | ‘111’ - Maximum Aperture Correction Always read as ‘0’ Bits 6 - 4 Bits 3 - 0 9 VP7615 Address 0x0A GPIO Output Control Register Read/Write 7 6 5 4 3 2 1 0 GPOE7 GPOE6 GPOE5 GPOE4 GPOE3 GPOE2 GPOE1 GPOE0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPIO7 Output Enable GPIO6 Output Enable GPIO5 Output Enable GPIO4 Output Enable GPIO3 Output Enable GPIO2 Output Enable GPIO1 Output Enable GPIO0 Output Enable ‘0’ = Corresponding GPIO pin is tristated/not driven. ‘1’ = Corresponding GPIO pin is driven to level of corresponding bit in GPIO Output Register. Write Only Address 0x0B GPIO Output Register 7 GPO7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 GPO6 5 GPO5 4 GPO4 3 GPO3 2 GPO2 1 GPO1 0 GPO0 GPIO7 Output Level GPIO6 Output Level GPIO5 Output Level GPIO4 Output Level GPIO3 Output Level GPIO2 Output Level GPIO1 Output Level GPIO0 Output Level ‘0’ = If corresponding GPIO Output Enable bit is ‘1’, then drive the appropriate GPIO pin to ‘0’ ‘1’ = If corresponding GPIO Output Enable bit is ‘1’, then drive the appropriate GPIO pin to ‘1’ ‘X’ = If the corresponding GPIO Output Enable bit it ‘0’, then tri-state the appropriate GPIO pin. Read Only Address 0x0B GPIO Input Register 7 GPI7 6 GPI6 5 GPI5 4 GPI4 3 GPI3 2 GPI2 1 GPI1 0 GPI0 Bits 7 - 0 GPIO Input Register This register represents the level on the corresponding GPIO pins. 10 VP7615 Address 0x0C Output Sense Control Register Read/Write 7 6 5 VAG 4 HAG 3 VAS 2 HAS 1 VSS 0 HSS SWPYUV SWPUV Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SWPYUV - YY and UV Swap ‘0’ = Normal: YY and UV are in proper positions CCIR601 output mode: YY data on YY bus; UV data on UV bus CCIR656 output mode: UYVY ‘1’ = Swapped: YY and UV in each other’s positions CCIR601 output mode: UV data on YY bus; YY data on UV bus CCIR656 output mode: YUYV . SWPUV - UV Swap ‘0’ = Normal: U and V are in position for CCIR601/656: U before V ‘1’ = Swapped: U and V are swapped in time: V before U VAG - VACT Gate ‘1’ = Gated: VACT active gated by HACT ‘0’ = Normal: VACT active during Active Lines HAG - HACT Gate ‘1’ = Gated: HACT active gated by VACT ‘0’ = Normal: HACT active during Active Pixels VAS - VACT Sense ‘1’ = Active High: VACT = 1 during Active Lines ‘0’ = Active Low: VACT = 0 during Active Lines HAS - HACT Sense ‘1’ = Active High: HACT = 1 during Active Pixels ‘0’ = Active Low: HACT = 0 during Active Pixels VSS - VSYNC Sense ‘1’ = Active High: VSYNC = 1 during Vertical Sync ‘0’ = Active Low: VSYNC = 0 during Vertical Sync HSS - HSYNC Sense ‘1’ = Active High: HSYNC = 1 during Horizontal Sync ‘0’ = Active Low: HSYNC = 0 during Horizontal Sync This register defaults on chip reset to 0x0C. Address 0x0D VACT Control Register Read/Write 7 VAFIX Bit 7 6 0 5 4 3 2 1 0 VFCnt5 VFCnt4 VFCnt3 VFCnt2 VFCnt1 VFCnt0 VAFIX - VACT Control This bit provides backward compatibility for certain iCam cameras. ‘0’ = Disabled: VACT controlled by camera timing ‘1’ = Enabled: VACT is inactive during a fixed number of lines during Vertical Blanking. This only effects the end, and not the beginning, of Vertical Blanking. Always read as ‘0’ VFCnt5 - VFCnt0 This field modifies the end of Vertical Blanking if VAFIX is ‘1’ by setting the number of lines that VACT will be inactive during Vertical Blanking. Bit 6 Bits 5 - 0 This register defaults on chip reset to 0x3F. 11 VP7615 Address 0x0E Hardware Version Register Read Only 7 HVer7 6 HVer6 5 HVer5 4 HVer4 3 HVer3 2 HVer2 1 HVer1 0 HVer0 Bits 7 - 0 Hardware Version Register 0x10 - VP7600 0x11 - VP7610 0x12 - VP7615 Read Only Address 0x0F Timing Status Register 7 FCnt5 6 FCnt4 5 FCnt3 4 FCnt2 3 FCnt1 2 FCnt0 1 Fld 0 VBlk Bits 7 - 2 Field Count A number between 0 and 63 which increments at the beginning of every Vertical Blanking Interval Field Bit ‘1’ Even Field - Digital Field 2 ‘0’ Odd Field - Digital Field 1 Vertical Blanking ‘1’ Vertical Blanking Interval ‘0’ Vertical Active Interval Bit 1 Bit 0 12 VP7615 Address 0x10 Lower Byte Red Chroma Register Read Only This register contains Bits 07 - 00 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x11 Lower Middle Byte Red Chroma Register Read Only This register contains Bits 15 - 08 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x12 Upper Middle Byte Red Chroma Register Read Only This register contains Bits 23 - 16 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x13 Upper Byte Red Chroma Register Read Only This register contains Bits 31 - 24 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x14 Lower Byte Blue Chroma Register Read Only This register contains Bits 07 - 00 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x15 Lower Middle Byte Blue Chroma Register Read Only This register contains Bits 15 - 08 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x16 Upper Middle Byte Blue Chroma Register Read Only This register contains Bits 23 - 16 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x17 Upper Byte Blue Chroma Register Read Only This register contains Bits 31 - 24 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x18 Lower Byte Luminance Register This register contains Bits 07 - 00 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x19 Lower Middle Byte Luminance Register This register contains Bits 15 - 08 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1A Upper Middle Byte Luminance Register This register contains Bits 23 - 16 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1B Upper Byte Luminance Register This register contains Bits 31 - 24 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1C Peak Luminance Register This register contains the peak value of the filtered Luminance of the pixels within the Metrics window. Read Only Read Only Read Only Read Only Read Only Address 0x20 Sum to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the Sum signal. Address 0x21 AmB to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the AmB signal. Address 0x22 CmD to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the CmD signal. 13 VP7615 Address 0x23 Red Coefficients Sign Register Read/Write 7 0 Bit 1 Bit 0 6 0 5 0 4 0 3 0 2 0 1 0 RCmD RAmB Sign for CmD to Red Coefficient Sign for AmB to Red Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Address 0x24 Sum to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the Sum signal. Address 0x25 AmB to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the AmB signal. Address 0x26 CmD to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the CmD signal. Address 0x27 Green Coefficients Sign Register Read/Write 7 0 Bit 1 Bit 0 6 0 5 0 4 0 3 0 2 0 1 0 GCmD GAmB Sign for CmD to Green Coefficient Sign for AmB to Green Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Address 0x28 Sum to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the Sum signal. Address 0x29 AmB to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the AmB signal. Address 0x2A CmD to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the CmD signal. Address 0x2B Blue Coefficients Sign Register Read/Write 7 0 Bit 1 Bit 0 6 0 5 0 4 0 3 0 2 0 1 0 BCmD BAmB Sign for CmD to Blue Coefficient Sign for AmB to Blue Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive 14 VP7615 Addresses 0x30 - 0x3F Gamma Values Write Register Write The 16 values that are written to these registers determine the breakpoints in the Gamma correction circuit. The lower four bits of the address are ignored on writes, and the data values are pushed on to an internal shift register. The writes should start with the lowest value and end with the highest value. The last 16 values written generate the Gamma curve, so all 16 values must be written. It is recommended that all 16 writes occur to address 0x30 with auto-increment disabled. All sixteen Gamma registers default on chip reset to 0x00. Addresses 0x30 - 0x3F Gamma Values Read Register Read The breakpoints in the Gamma correction circuit are read from these registers. 15 VP7615 Signal Timing The clock source for the VP7615 is the clock input of the selected CamPort. Since there are two CamPort inputs, the selected clock is brought out as an output, namely CLK2. Since the frequency of this clock is twice the pixel rate, another output, CLK1, is provided which runs at the pixel rate. It is anticipated that the VP7615 user would use one or both of these clocks to clock the data and timing outputs into another device. In order to assure hold times into any device, the clock outputs CLK1 and CLK2 were inverted inside the VP7615 so that the data and timing outputs would change near the falling edge of these clocks, and would be stable at their rising edges. The timing specifications characterize the delay from the falling edges of CLK1 and CLK2 to the edges of the data and timing outputs. It is left to the system designer to calculate the available setup and hold times based on these timing specifications, the period of CLK1 and CLK2 and their duty cycles. OUTEN CLK1, CLK2 VSYNC, HSYNC, VACT, HACT BFLAG, FIELD YY[7:0], UV[7:0] CPCKA or CPCKB tdis High Impedance toen CLK1 tcqCPX tcpCK1f VSYNC, HSYNC VACT, HACT BFLAG, FIELD YY[7:0] UV[7:0] CCSEL = Low CPCKA or CPCKB tpdCK2 tpdCK2 tcqCPX CLK2 CLK1 VSYNC, HSYNC VACT, HACT BFLAG, FIELD tcpCK2f tcpCK2f YY[7:0] CCSEL = High LUMA CHROMA LUMA CHROMA Fig.2 Video Interface Timing Diagram 16 VP7615 SCL tpdSCL tpdSCL CPSEL tpdSCL SCLOA tpdSCL SCLOB tWRSTN RSTN tRCK RCLK CPSEL SDMN tcqRCLK tcqRCLK High Impedance SDAO Fig.3 I2C Timing Diagram INVI tpdINV tpdINV INVO thiCPX tCPX CPCKA or CPCKB fCPX = 1/tCPX dcCPX = thiCPX/tCPX CPDA or CPDB thCPDX tsuCPDX Fig.4 Clock Timing Diagram 17 VP7615 CLK2 CLK1 HACT BFLAG 16 BIT OUTPUT MODE (CCSEL = 0): YY(7:0) 10 Y0 Y1 Y2 Y3 UV(7:0) 80 CCIR-656 OUTPUT MODE (CCSEL = 1): CB0 CR0 CB2 CR2 YY(7:0) 80 10 80 10 FF 00 00 SAV CB0 Y0 CR0 YI CB2 Y2 CR2 Y3 Fig.5 Start of Active Video HBlank HACT HBlank/8 HSYNC HBlank/2 BFLAG Fig.6 Horizontal Sync Timing HACT H VACT 2.5H FIELD VSYNC Fig.7 Even Field Timing 18 VP7615 HACT H VACT FIELD VSYNC 3.0H Fig.8 Odd Field Timing TIMING REQUIREMENTS Name fCPX tCPX dcCPX tsuCPDX frequency CPCKA or CPCKB period CPCKA or CPCKB duty cycle CPCKA or CPCKB setup time, CPDA [3..0] to CPCKA or CPDB [3..0] to CPCKB thCPDX hold time, CPDA [3..0] to CPCKA or CPDB [3..0] to CPCKB fRCK twRSTN frequency RCLK pulse width of RSTN 4 10 110 33 ns MHz ns 4 ns Description 0 33 40 Value Min. Max. 30 60 MHz ns % Unit TIMING CHARACTERISTICS Name tcqRCLK tcpCPX tcqCK2f tcpCK1f tpdCK2 tpdINV tpdSCL tdis toen Description Min. RCLK to output (CPSEL, SDAO, SDMN) rising edge of CPCKA or CPCKB to output (YY[7..0], UV[7..0], CLK1, VSYNC, HSYNC,VACT, HACT, BFLAG) falling edge of CLK2 to output (YY[7..0], UV[7..0], CLK1, VSYNC, HSYNC, VACT, HACT, BFLAG) falling edge of CLK1 to output (YY[7..0], UV[7..0],VSYNC, HSYNC, VACT, HACT, BFLAG) propagation delay from CPCKA or CPCKB to CK2 propagation delay from INVI to INVO propagation delay from SCLI to SCLOA or SCLOB rising edge of OUTEN to outputs tri-state (CLK1, CLK2, VSYNC, HSYNC, VACT, HACT, BFLAG, FIELD, YY[7:0], UV[7:0]) falling edge of OUTEN to outputs (CLK1, CLK2, VSYNC, HSYNC, VACT, HACT, BFLAG, FIELD, YY[7:0], UV[7:0]) 30 ns -3 5 12 11 15 30 ns ns ns ns ns -2 7 ns 21 ns Value Max. 20 Unit ns 19 VP7615 ABSOLUTE MAXIMUM RATINGS [See Notes] Supply voltage VDD -0.5V to 7.0V Input voltage VIN -0.5V to VDD + 0.5V Output voltage VOUT -0.5V to VDD + 0.5V Clamp diode current per pin IK (see note 2) 18mA Static discharge voltage (HBM) 500V -55°C to 150°C Storage temperature TS Ambient temperature with power applied TAMB 0°C to 70°C Junction temperature 125°C Package power dissipation 1000mW NOTES ON MAXIMUM RATINGS 1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. 2. Maximum dissipation for 1 second should not be exceeded, only one output to be tested at any one time. 3. Exposure to absolute maximum ratings for extended periods may affect device reliablity. 4. Current is defined as negative into the device. STATIC ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise stated) Tamb = 0°C to +70°C VDD = 5.0v ± 10% Value Characteristic Symbol Min. Output high voltage Output low voltage Input high voltage (CMOS input) Input low voltage (CMOS input) Input high voltage (TTL input) Input low voltage (TTL input) Input leakage current Input capacitance Output leakage current Output S/C current VOH VOL VIHC VILC VIHT VILT IIN CIN IOZ ISC 0.8VDD 0.7VDD 2.0 -1 10 -1 10 +1 300 Typ. Max. 0.4 0.2VDD 0.8 +1 V V V V V V µA pF µA mA IOH = 4mA IOL = -4mA Units Conditions GND < VIN < VDD GND < VOUT < VDD VDD = Max 20 VP7615 21 VP7615 22 VP7615 23 VP7615 PACKAGE DETAILS Dimensions are shown thus: mm (in). For further package information, please contact your local Customer Service Centre. 0° - 7° 0·20 (0·008) MAX. 1·35 /1·45 (0·053/0·057) 13·80/14·20 (0·543/0·559) SQ. 12·00 (0·472) NOM. 15·80/16·20 (0·622/0·638) 1·60 (0·063) MAX. PIN 100 INDEX 0·45/0·75 (0·018/0·030) PIN 1 0·17/0·27 (0·007/0·011) 100 LEADS AT 0·50 (0·020) NOM. SPACING 0·05/0·15 (0·002/0·006) NOTES 1. Controlling dimensions are millimetres. 2. Pin 1 indicator may be a corner chamfer, dot or both. 3. This package outline diagram is for guidance only. Please contact your Mitel Semiconductor Customer Service Centre for further information. 100-LEAD FINE PITCH PLASTIC QUAD FLATPACK – FPD100 Purchase of Mitel Semiconductor I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips HEADQUARTERS OPERATIONS MITEL SEMICONDUCTOR Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 MITEL SEMICONDUCTOR 1500 Green Hills Road, Scotts Valley, California 95066-4922 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576/6231 Internet: http://www.gpsemi.com CUSTOMER SERVICE CENTRES G FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax : (1) 64 46 06 07 G GERMANY Munich Tel: (089) 419508-20 Fax : (089) 419508-55 G ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993 G JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 G KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933 G NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 5576/6231 G SOUTH EAST ASIA Singapore Tel:(65) 3827708 Fax: (65) 3828872 G SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 G TAIWAN, ROC Taipei Tel: 886 2 25461260 Fax: 886 2 27190260 G UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 726666 Fax : (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. © Mitel Corporation 1998 Publication No. DS4602 Issue No. 3.1 August 1997 TECHNICAL DOCUMENTATION – NOT FOR RESALE. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s conditions of sale which are available on request. M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation Mitel Semiconductor is an ISO 9001 Registered Company Copyright 1999 MITEL Corporation All Rights Reserved Printed in CANADA TECHNICAL DOCUMENTATION - NOT FOR RESALE