MTP3N50

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP3N50E/D ™ Data Sheet TMOS E-FET.™ High Energy Power FET Designer's MTP3N50E Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate This advanced high voltage TMOS E–FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain–to–source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Capability Specified at Elevated Temperature • Low Stored Gate Charge for Efficient Switching • Internal Source–to–Drain Diode Designed to Replace External Zener Transient Suppressor — Absorbs High Energy in the Avalanche Mode • Source–to–Drain Diode Recovery Time Comparable to Discrete Fast Recovery Diode TMOS POWER FET 3.0 AMPERES 500 VOLTS RDS(on) = 3.0 OHMS ® D G S CASE 221A–06, Style 5 TO–220AB MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltage — Non–repetitive (tp ≤ 50 µs) Drain Current — Continuous Drain Current — Pulsed Total Power Dissipation @ TC = 25°C Derate above 25°C Operating and Storage Temperature Range Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg Value 500 500 ± 20 ± 40 3.0 10 50 0.4 – 65 to 150 Unit Vdc Vdc Vdc Vpk Adc Watts W/°C °C UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C) Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C Single Pulse Drain–to–Source Avalanche Energy — TJ = 100°C Repetitive Pulse Drain–to–Source Avalanche Energy WDSR (1) WDSR (2) 210 33 5.0 mJ THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case° — Junction to Ambient° Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds (1) VDD = 50 V, ID = 3.0 A (2) Pulse Width and frequency is limited by TJ(max) and thermal response Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. RθJC RθJA TL 2.5 62.5 260 °C/W °C E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 © Motorola TMOS Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTP3N50E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = 500 V, VGS = 0) (VDS = 400 V, VGS = 0, TJ = 125°C) Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) (TJ = 125°C) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.5 Adc) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 3.0 A) (ID = 1.5 A, TJ = 100°C) Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS* Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge SOURCE–DRAIN DIODE CHARACTERISTICS* Forward On–Voltage Forward Turn–On Time Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) * Indicates Pulse Test: Pulse Width = 300 µs Max, Duty Cycle ≤ 2.0%. ** Limited by circuit inductance. Ld — — Ls — 3.5 4.5 7.5 — — — nH (IS = 3.0 A) (IS = 3.0 A, di/dt = 100 A/µs) VSD ton trr — — — — ** 200 1.5 — — Vdc ns (VDS = 400 V, ID = 3.0 A, VGS = 10 V) (VDD = 250 V, ID ≈ 3.0 A, RG = 18 Ω, RL = 83 Ω, VGS(on) = 10 V) td(on) tr td(off) tf Qg Qgs Qgd — — — — — — — 14 14 30 20 15 2.5 10 — — — — 21 — — nC ns (VDS = 25 V, VGS = 0, f = 1.0 MHz) Ciss Coss Crss — — — 435 56 9.2 — — — pF VGS(th) 2.0 1.5 RDS(on) VDS(on) — — gFS 1.0 — — — 10 8.0 — mhos — — — 2.4 4.0 3.5 3.0 Ohm Vdc Vdc V(BR)DSS IDSS — — IGSSF IGSSR — — — — — — 0.25 1.0 100 100 nAdc nAdc 500 — — Vdc mAdc Symbol Min Typ Max Unit 2 Motorola TMOS Power MOSFET Transistor Device Data MTP3N50E TYPICAL ELECTRICAL CHARACTERISTICS VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) 6 5 I D, DRAIN CURRENT (AMPS) 4 3 2 1 0 0 1.2 VDS = VGS ID = 0.25 mA TJ = 25°C VGS = 10 V 7V 1.1 1 6V 0.9 5V 4V 2 8 12 16 6 10 14 18 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 4 20 0.8 –50 –25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 Figure 1. On–Region Characteristics VBR(DSS), DRAIN–TO–SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 2. Gate–Threshold Voltage Variation With Temperature 5 VDS ≥ 10 V I D, DRAIN CURRENT (AMPS) 4 1.2 VGS = 0 ID = 250 µA 1.1 3 1 2 100°C 25°C 0.9 1 0.8 TJ = –55°C 8 0 0 2 4 6 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) –50 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) Figure 3. Transfer Characteristics Figure 4. Breakdown Voltage Variation With Temperature RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 8 VGS = 10 V 6 TJ = 100°C 4 25°C 2 –55°C 0 0 1 2 3 4 5 ID, DRAIN CURRENT (AMPS) 2.5 VGS = 10 V ID = 1.5 A 2 1.5 1 0.5 –50 –25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 5. On–Resistance versus Drain Current Figure 6. On–Resistance versus Temperature Motorola TMOS Power MOSFET Transistor Device Data 3 MTP3N50E SAFE OPERATING AREA INFORMATION 10 I D, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C 100 µs 1 ms 10 ms dc 1 µs I D, DRAIN CURRENT (AMPS) 10 µs 16 12 1 8 TJ ≤ 150°C 4 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0 1 100 10 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 1000 0 500 100 200 300 400 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 600 Figure 7. Maximum Rated Forward Biased Safe Operating Area Figure 8. Maximum Rated Switching Safe Operating Area FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain–to–source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, “Transient Thermal Resistance–General Data and Its Use” provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn– on and turn–off of the devices for switching times less than one microsecond. 1 0.7 0.5 0.3 0.2 0.1 0.1 0.07 0.05 0.03 0.02 0.05 0.02 0.01 SINGLE PULSE 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 t2 DUTY CYCLE, D = t1/t2 10 20 30 t1 P(pk) RθJC(t) = r(t) RθJC RθJC = 2.5°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 50 100 200 300 500 1000 1000 VDD = 250 V ID = 3 A VGS = 10 V TJ = 25°C td(off) 100 t, TIME (ns) td(on) 10 tf tr 1 1 10 100 RG, GATE RESISTANCE (OHMS) 1000 Figure 9. Resistive Switching Time Variation versus Gate Resistance r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.01 0.01 t, TIME (ms) Figure 10. Thermal Response 4 Motorola TMOS Power MOSFET Transistor Device Data MTP3N50E COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VR for a given commutation speed. It is applicable when waveforms similar to those of Figure 11 are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. The time interval tfrr is the speed of the commutation cycle. Device stresses increase with commutation speed, so tfrr is specified with a minimum value. Faster commutation speeds require an appropriate derating of IFM, peak VR or both. Ultimately, tfrr is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 80% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances, Li in Motorola’s test circuit are assumed to be practical minimums. 15 V VGS 0 IFM 90% IS 10% ton IRM 0.25 IRM VDS(pk) VR VDS dVDS/dt VdsL MAX. CSOA STRESS AREA dls/dt trr Vf Figure 11. Commutating Waveforms RGS DUT – 4 + I D, DRAIN CURRENT (AMPS) VR IFM + 3 VGS 2 di/dt ≤ 50 A/µs 1 20 V – IS VDS Li VR = 80% OF RATED VDS VdsL = Vf + Li ⋅ dls/dt Figure 13. Commutating Safe Operating Area Test Circuit 0 500 100 200 300 400 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 600 V(BR)DSS Vds(t) IO L VDS ID C 4700 µF 250 V VDD t RGS 50 Ω VDD tP WDSR t, (TIME) ID(t) 0 Figure 12. Commutating Safe Operating Area (CSOA) + 1 LI 2 O 2 V(BR)DSS V(BR)DSS – VDD Figure 14. Unclamped Inductive Switching Test Circuit Motorola TMOS Power MOSFET Transistor Device Data Figure 15. Unclamped Inductive Switching Waveforms 5 MTP3N50E VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 1000 800 C, CAPACITANCE (pF) TJ = 25°C VGS = 0 16 VDS = 100 V 12 TJ = 25°C ID = 3 A 400 V 8 250 V 600 Ciss 400 Crss 200 VDS = 0 0 10 Coss 4 0 10 20 25 5 5 15 VGS VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0 0 5 10 15 QG, TOTAL GATE CHARGE (nC) 20 25 Figure 16. Capacitance Variation Figure 17. Gate Charge versus Gate–To–Source Voltage +18 V VDD 1 mA 47 k Vin 15 V 2N3904 2N3904 100 k 47 k 100 FERRITE BEAD 10 V 100 k 0.1 µF SAME DEVICE TYPE AS DUT DUT Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10% Figure 18. Gate Charge Test Circuit 6 Motorola TMOS Power MOSFET Transistor Device Data MTP3N50E PACKAGE DIMENSIONS –T– B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 Q 123 A U K STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN H Z L V G D N R J CASE 221A–06 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 7 MTP3N50E Motorola reserves the right to make changes without further notice to any products herein. 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