MTP2P50EG
Power MOSFET
2 Amps, 500 Volts, P−Channel TO−220
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this Power MOSFET is designed
to withstand high energy in the avalanche and commutation modes.
The energy efficient design also offers a drain−to−source diode with a
fast recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters and PWM motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
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2 AMPERES, 500 VOLTS
RDS(on) = 6 W
P−Channel
D
Features
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
G
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• This is a Pb−Free Device*
S
MARKING DIAGRAM
AND PIN ASSIGNMENT
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−Source Voltage
VDSS
500
Vdc
Drain−Gate Voltage (RGS = 1.0 MW)
VDGR
500
Vdc
Gate−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
ID
ID
2.0
1.6
6.0
Adc
75
0.6
W
W/°C
TJ, Tstg
−55 to 150
°C
EAS
80
mJ
RqJC
RqJA
1.67
62.5
TL
260
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 ms)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL = 4.0 Apk, L = 10 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 sec
IDM
PD
Apk
4
Drain
4
TO−220AB
CASE 221A
STYLE 5
1
2
MTP
2P50EG
AYWW
3
1
Gate
2
Drain
°C/W
MTP2P50E = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
°C
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Device
MTP2P50EG
3
Source
Package
Shipping
TO−220AB
(Pb−Free)
50 Units/Rail
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 7
1
Publication Order Number:
MTP2P50E/D
MTP2P50EG
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
500
−
−
564
−
−
Vdc
mV/°C
−
−
−
−
10
100
−
−
100
nAdc
2.0
−
3.0
4.0
4.0
−
Vdc
mV/°C
−
4.5
6.0
W
−
−
9.5
−
14.4
12.6
gFS
0.5
−
−
mhos
Ciss
−
845
1183
pF
Coss
−
100
140
Crss
−
26
52
td(on)
−
12
24
tr
−
14
28
td(off)
−
21
42
tf
−
19
38
QT
−
19
27
Q1
−
3.7
−
Q2
−
7.9
−
Q3
−
9.9
−
−
−
2.3
1.85
3.5
−
trr
−
223
−
ta
−
161
−
tb
−
62
−
QRR
−
1.92
−
−
−
3.5
4.5
−
−
−
7.5
−
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
mAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 1.0 Adc)
RDS(on)
Drain−Source On−Voltage (VGS = 10 Vdc)
(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 250 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc, RG = 9.1 W)
Fall Time
Gate Charge (See Figure 8)
(VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1)
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
VSD
Vdc
ns
mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
nH
nH
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
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2
MTP2P50EG
TYPICAL ELECTRICAL CHARACTERISTICS
4
4
3.5
VDS ≥ 10 V
7V
3.5
8V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
VGS = 10 V
TJ = 25°C
3
6V
2.5
2
1.5
5V
1
3
100°C
TJ = - 55°C
2.5
25°C
2
1.5
1
0.5
0.5
4V
0
4
8
12
20
16
24
0
28
5
4.5
5.5
6
TJ = 100°C
6
25°C
4
- 55°C
2
0.5
1
2
2.5
1.5
3
ID, DRAIN CURRENT (AMPS)
3.5
4
7
6.5
6
TJ = 25°C
5.75
5.5
5.25
5
VGS = 10 V
4.75
15 V
4.5
4.25
4
0
Figure 3. On−Resistance versus Drain Current
and Temperature
0.5
1
1.5
2.5
2
3
ID, DRAIN CURRENT (AMPS)
3.5
4
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2
1000
VGS = 0 V
VGS = 10 V
ID = 1 A
TJ = 125°C
I DSS , LEAKAGE (nA)
RDS(on), DRAIN‐TO‐SOURCE RESISTANCE
(NORMALIZED)
4
Figure 2. Transfer Characteristics
8
1.5
1
0.5
- 50
3.5
Figure 1. On−Region Characteristics
VGS = 10 V
0
3
2.5
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
10
0
2
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
R DS(on) , DRAIN‐TO‐SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN‐TO‐SOURCE RESISTANCE (OHMS)
0
- 25
0
25
50
75
100
125
100
100°C
10
25°C
1
150
0
50
100
150
200
250
300
350
400
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
450
500
MTP2P50EG
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1800
1600
VGS = 0 V
1000
TJ = 25°C
C, CAPACITANCE (pF)
Ciss
1400
C, CAPACITANCE (pF)
VDS = 0 V
1200
1000
Ciss
800
600
Crss
400
200
0
5
0
VGS
Ciss
100
Coss
10
Crss
Coss
Crss
10
VGS = 0 V
TJ = 25°C
5
10
15
20
1
10
25
VDS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Figure 7a. Capacitance Variation
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4
1000
300
QT
10
250
VGS
8
200
Q1
Q2
6
150
ID = 2 A
TJ = 25°C
4
100
2
50
Q3
0
0
2
4
VDS
6
8
10
12
14
16
0
20
18
1000
VDD = 250 V
ID = 2 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
12
VDS , DRAIN‐TO‐SOURCE VOLTAGE (VOLTS)
VGS, GATE‐TO‐SOURCE VOLTAGE (VOLTS)
MTP2P50EG
100
td(off)
tf
tr
td(on)
10
1
10
QT, TOTAL CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
2
VGS = 0 V
TJ = 25°C
1.6
1.2
0.8
0.4
0
0.6
0.8
1
1.2
1.6
1.4
1.8
2
2.2
2.4
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MTP2P50EG
SAFE OPERATING AREA
80
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
10
10 ms
1
100 ms
1 ms
dc
10 ms
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
10
1
60
40
20
0
1000
100
ID = 2 A
25
50
75
100
150
125
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
P(pk)
0.05
0.1
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RqJC(t)
0.02
0.01
t1
SINGLE PULSE
0.01
1.0E-05
1.0E-04
t2
DUTY CYCLE, D = t1/t2
1.0E-03
1.0E-02
t, TIME (s)
1.0E-01
1.0E+00
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1.0E+01
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220
CASE 221A
ISSUE AK
DATE 13 JAN 2022
SCALE 1:1
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
BASE
EMITTER
COLLECTOR
EMITTER
STYLE 3:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
STYLE 5:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 6:
PIN 1.
2.
3.
4.
ANODE
CATHODE
ANODE
CATHODE
STYLE 7:
PIN 1.
2.
3.
4.
CATHODE
ANODE
CATHODE
ANODE
STYLE 8:
PIN 1.
2.
3.
4.
CATHODE
ANODE
EXTERNAL TRIP/DELAY
ANODE
STYLE 9:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
STYLE 10:
PIN 1.
2.
3.
4.
GATE
SOURCE
DRAIN
SOURCE
STYLE 11:
PIN 1.
2.
3.
4.
DRAIN
SOURCE
GATE
SOURCE
STYLE 12:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42148B
TO−220
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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