HR1001L
Enhanced LLC Controller with
Adaptive Dead-Time Control
DESCRIPTION
FEATURES
The HR1001L is an enhanced LLC controller
that provides new, adaptive, dead-time
adjustment (ADTA) and capacitive mode
protection (CMP) features. The HR1001L is the
OCP latch-off version of the HR1001B.
ADTA inserts a dead time between the two
complimentary gate outputs automatically by
keeping the outputs off while sensing the dV/dt
current of the half-bridge switching node. ADTA
features an easier design, lower EMI, and
higher efficiency.
The HR1001L incorporates anti-capacitive
mode protection, which prevents potentially
destructive capacitive mode switching if the
output is shorted or has a severe overload.
This feature protects the MOSFET during
abnormal conditions, making the converter
robust.
The HR1001L has a programmable oscillator
that sets both the maximum and minimum
switching frequencies. It starts up at a
programmed maximum switching frequency
and decays until the control loop takes over to
prevent excessive inrush current.
The HR1001L enters controlled burst mode at
light loads to minimize the power consumption
and tighten output regulation.
Full protection features include two-level overcurrent
protection
(OCP),
external-latch
shutdown, brown-in/brown-out, capacitive mode
protection (CMP), and over-temperature
protection (OTP).
HR1001L Rev.1.0
4/18/2016
Two-Level Over-Current Protection (OCP):
Frequency Shift and Latch-Off Mode
Adaptive Dead-Time Adjustment (ADTA)
Capacitive Mode Protection (CMP)
50% Duty Cycle, Variable Frequency
Control for Resonant Half-Bridge Converter
600V High-Side Gate Driver with Integrated
Bootstrap Diode with a High-Accuracy
Oscillator of High dV/dt Immunity
Operates up to 600kHz
Latched to Disable Input for Easy Protection
Remote On/Off Control and Brown-Out
Protection through BO
Programmable Burst Mode Operation at
Light Load
Non-Linear Soft Start for Monotonic Output
Voltage Rise
Available in a SOIC-16 Package
APPLICATIONS
LCD and PDP TVs
Desktop PCs and Servers
Telecom SMPS
AC/DC Adapter, Open-Frame SMPS
Video Game Consoles
Electronic Lighting Ballast
All MPS parts are lead-free, halogen-free, and adhere to the RoS directive. For
MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
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© 2016 MPS. All Rights Reserved.
1
HR1001L – ENHANCED LLC CONTROLLER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
TYPICAL APPLICATION
BO
SS
Css
16
1
Rss TIMER
15
2
CT
14
3
CT
FSET
4 HR1001L 13
Rfmax BURST
12
5
CS
Rfmin
11
6
BO
10
7
LATCH
9
8
BST
VDC
CBST
HG
S1
Lr
SW
NC
VCC
CHBVS
D1
S2
Output
Lm
LG
GND
VCC
HBVS
Cr
D2
Rf
Cf
Rs
Cs
TL431
HR1001L Rev.1.0
4/18/2016
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2
HR1001L – ENHANCED LLC CONTROLLER
ORDERING INFORMATION
Part Number*
Package
Top Marking
HR1001LGS
SOIC-16
See Below
* For Tape & Reel, add suffix –Z (e.g. HR1001LGS–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
HR1001L: Part number
LLLLLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
SS
1
16
BST
TIMER
2
15
HG
CT
3
14
SW
FSET
4
13
NC
BURST
5
12
VCC
CS
6
11
LG
BO
7
10
GND
LATCH
8
9
HBVS
HR1001L
SOIC-16
HR1001L Rev.1.0
4/18/2016
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3
HR1001L – ENHANCED LLC CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
Recommended Operating Conditions
BST voltage......………................. -0.3V to 618V
SW voltage …………...... ................ -3V to 600V
Max voltage slew rate of SW….. ............. 50V/ns
Supply voltage (VCC)…….. ............. Self-limited
Sink current of HBVS….. ........................ ±65mA
Voltage on HBVS.......…. ......... -0.3V to self-limit
Source current of FSET….. .........................2mA
Voltage rating of LG………. ............ -0.3V to VCC
Voltage on CS.......……....................... -3V to 6V
Other analog inputs and outputs ...... -0.3V to 6V
(2)
Continuous power dissipation (TA = +25°C)
PIC ………………………. .......................... 1.56W
Junction temperature…............................ 150°C
Lead temperature ….….............................260°C
Storage temperature….…. ....... -65°C to +150°C
ESD immunity…………………………...BST, HG,
SW passes HBM 2.5kV, other pins can pass
HBM 4kV.
Supply voltage (VCC)….. .............. 13V to 15.5V
Analog inputs and outputs ................ -0.3V to 6V
Operating junction temp (TJ).... .-40°C to +125°C
HR1001L Rev.1.0
4/18/2016
Thermal Resistance
(4)
(3)
θJA θJC
SOIC-16.................................80.....35…… °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on a JESD51-7, 4-layer PCB.
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4
HR1001L – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C~125°C, min and max values are
guaranteed by characterization, typical values are tested under 25°C, unless otherwise
specified.
Parameter
IC Supply Voltage (VCC)
VCC operating range
VCC high threshold, IC switch on
VCC low threshold, IC switch off
Hysteresis
VCC clamp voltage
IC Supply Current (VCC)
Symbol Condition
VCCH
VCCL
VCC-hys
VCC-Clamp IClamp = 1mA
Before the device turns on,
VCC = VCCH - 0.2V
Device on, VBurst < 1.23V,
IQ
RFSET =12k, FMIN = 60kHz
Quiescent current
Device on, VBurst < 1.23V,
IQ-f
RFSET = 3.57k, FBURST = 200kHz
Operating current
ICC-nor Device on VBurst = VFSET
VCC < 8.2V or VLATCH > 1.85V
or VCS > 1.5V or VTIMER > 3.5V
Residual consumption
IFault
or VBO < 1.81V or VBO > 5.5V
or OTP
High-Side Floating Gate Driver Supply (BST, SW)
BST leakage current
ILK-BST VBST = 600V, TJ = 25°C
SW leakage current
ILK-SW VSW = 582V, TJ = 25°C
Start-up current
Min
8.9
10.3
7.5
Istart-up
240
Typ
Max
Units
15.5
11.7
8.9
V
V
V
V
V
250
320
μA
1.2
1.5
mA
1.42
1.8
mA
3
5
mA
350
420
μA
12
12
µA
µA
2
µA
11
8.2
2.8
16.5
Current Sensing (CS)
Input bias current
ICS
VCS = 0 to VCSlatch
Frequency shift threshold
VCS-OCR
0.71
0.78
0.85
V
OCP threshold
VCS-OCP
1.41
1.5
1.59
V
VCSPR
50
85
131
mV
VCSNR
-131
-85
-50
mV
2.30
2.4
V
Current
polarity
comparator
reference when HG turns off
Current
polarity
comparator
reference when LG turns off
Line Voltage Sensing (BO)
Start-up threshold voltage
VBO-On
Turn-off threshold voltage
VBO-Off
1.72
1.81
VBO-Clamp
5.1
5.5
Clamp level
V
5.9
V
1
µA
1.95
V
Latch Function (LATCH)
Input bias current
(VLATCH = 0 to Vth)
ILATCH
LATCH threshold
VLATCH
HR1001L Rev.1.0
4/18/2016
1.72
1.85
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5
HR1001L – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C~125°C, min and max values are
guaranteed by characterization, typical values are tested under 25°C, unless otherwise
specified.
Parameter
Oscillator
Symbol Condition
Output duty cycle
D
Oscillation frequency
CT peak value
CT valley value
Voltage reference at FSET
Dead time
Timer for CMP
Half-Bridge Voltage Sense (HBVS)
fosc
VCFp
VCFv
VREF
DTMIN
DTMAX
DT-float
tCMP
TJ = 25°C
TJ = -40~125°C
CT ≤ 150pF, RFSET ≤ 2k
Min
Typ
Max
Units
48
47
50
50
52
53
600
%
%
kHz
V
V
2.05
290
V
ns
µs
ns
µs
3.8
0.9
CHBVS = 5pF, typically
1.87
180
HBVS floating
250
VHBVS-
Voltage clamp
2
235
1
350
52
450
7.6
V
Clamp
Minimum voltage change rate that
can be detected
Turn-on delay
Soft-Start Function (SS)
Discharge resistance
Standby Function (BURST)
Disable threshold
Hysteresis
dVmin/dt CHBVS = 5pF, typically
180
V/µs
Td
Slope finish to turn-on delay
100
ns
Rd
VCS > VCS-OCR
130
Ω
VBurst
VBurst-hys
1.17
1.23
30
1.28
100
V
mV
80
130
180
µA
1.80
2
2.10
V
Delayed Shutdown (TIMER)
Charge current
ITIMER
Threshold for forced operation at
maximum frequency
VTIMER = 1V, VCS = 0.85V,
TJ = 25°C
VTIMERfmax
Shutdown threshold
VTIMER-SD
3.2
3.5
3.7
V
Restart threshold
VTIMER-R
0.21
0.28
0.35
V
Low-Side Gate Driver (LG, Referenced to GND)
Peak source current
Peak sink current
Sourcing resistor
Sinking resistor
(5)
(5)
Isourcepk
0.75
A
Isinkpk
0.87
A
Rsource
Isrc = 0.1A
4
Ω
Rsink
Isnk = 0.1A
2
Ω
Fall time
tf
30
ns
Rise time
tLG-r
30
ns
UVLO saturation
HR1001L Rev.1.0
4/18/2016
VCC = 0 to VCCH,
Isink = 2mA
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1
V
6
HR1001L – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C~125°C, min and max values are
guaranteed by characterization, typical values are tested under 25°C, unless otherwise
specified.
Parameter
Symbol Condition
High-Side Gate Driver (HG, Referenced to SW)
Peak source current
(5)
Peak sink current
Sourcing resistor
Sinking resistor
Fall time
(5)
IHG-source-pk
IHG-sink-pk
RHG-source
RHG-sink
tHG-f
Rise time
Thermal Shutdown
Thermal shutdown threshold
Thermal shutdown recovery
(5)
threshold
tHG-r
(5)
Isrc = 0.01A
Isnk = 0.01A
Min
Typ
Max
Units
0.74
0.87
4
2
30
A
A
Ω
Ω
ns
30
ns
150
°C
120
°C
NOTE:
5) Guaranteed by design.
HR1001L Rev.1.0
4/18/2016
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7
HR1001L – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are generated using the evaluation board built with the design example
on page 22, VAC = 120V, VOUT = 24V, IOUT = 4.16A, TA = 25°C, unless otherwise noted.
HR1001L Rev.1.0
4/18/2016
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© 2016 MPS. All Rights Reserved.
8
HR1001L – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with the design example
on page 22, VAC = 120V, VOUT = 24V, IOUT = 4.16A, TA = 25°C, unless otherwise noted.
HR1001L Rev.1.0
4/18/2016
www.MonolithicPower.com
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9
HR1001L – ENHANCED LLC CONTROLLER
PIN FUNCTIONS
Pin #
Name
1
SS
2
TIMER
3
CT
4
FSET
5
BURST
6
CS
HR1001L Rev.1.0
4/18/2016
Description
Soft start. Connect an external capacitor from SS to GND and a resistor to FSET to set the
maximum oscillator frequency and the time constant for the frequency shift during start-up.
An internal switch discharges the capacitor when the chip turns off (VCC < UVLO, BO <
1.81V or > 5.5V, LATCH > 1.85V, CS > 1.5V, TIMER > 2V, thermal shutdown) to guarantee
a soft start.
Period between over-current and shutdown. Connect a capacitor and a resistor from
TIMER to GND to set the maximum duration from an over-current condition before the IC
stops switching. Whenever the voltage on CS exceeds 0.78V, an internal 130µA current
source charges the capacitor. An external resistor discharges this capacitor slowly. If the
voltage on TIMER reaches 2V, the soft-start capacitor discharges completely, raising its
switching frequency to its maximum value. The 130µA current source remains on. When
the voltage exceeds 3.5V, the IC stops switching and latches. The internal current source
turns off, and the voltage decays. Two events are required for the IC to resume soft start:
1) the voltage on TIMER must drop below 0.28V; 2) VCC must drop below the UVLO
threshold and rise up to the VCC high threshold.
Time set. An internal current source programmed by an external network connected to
FSET charges and discharges a capacitor connected to GND. This determines the
converter’s switching frequency.
Switching frequency set. FSET provides a precise 2V reference. A resistor connected
from FSET to GND defines a current that sets the minimum oscillator frequency. Connect
the phototransistor of an optocoupler to FSET through a resistor to close the feedback loop
that modulates the oscillator frequency. This regulates the converter’s output voltage. The
value of this resistor sets the maximum operating frequency. An R-C series connected from
FSET to GND sets the frequency shift at start-up to prevent excessive inrush energy.
Burst mode operation threshold. BURST senses the voltage related to the feedback
control, which is compared to an internal reference (1.23V). When the voltage on BURST is
lower than this reference, the IC enters an idle state and reduces its quiescent current.
When the feedback drives BURST above 1.26V (30mV hysteresis), the chip resumes
switching. There is no soft start. The burst function enables burst mode operation when the
load falls below a programmed level that is determined by connecting an appropriate
resistor to the optocoupler to FSET (see the Block Diagram on page 12). Connect BURST
to FSET if burst mode is not used.
Current sense of the half-bridge. CS uses a sense resistor or a capacitive divider to
sense the primary-side current. CS has the following functions:
Over-current regulation: If the sensed voltage exceeds the 0.78V threshold, the softstart capacitor on SS discharges internally. The frequency increases, limiting the
power throughout. Under an output short circuit, this normally results in a nearconstant peak primary current. TIMER limits the duration of this condition.
Over-current protection (OCP): If the primary-side current continues to rise despite the
frequency increase, OCP enters latch mode when VCS > 1.5V. This requires cycling
the IC supply voltage to restart. The latch is removed once the voltage on VCC drops
below the UVLO threshold.
Capacitive mode protection (CMP): Once LG turns off, CS is compared to the VCSNR
capacitive mode protection (CMP) threshold. If VCS > VCSNR, the HG gate is blocked
from turning on until the slope is detected or the CMP timer is complete. When HG
turns off, CS is compared to the VCSPR CMP threshold. If Vcs < VCSPR, the low-side
gate is blocked from turning on until the slope is detected or the CMP timer is
complete. If a capacitive mode status is detected, SS is not discharged immediately;
there is a 1µs delay. After the blanking time delay, SS is discharged if the capacitive
mode fault remains. This prevents the influence of CS noise effectively. Connect CS
to GND if the CMP function is not used.
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10
HR1001L – ENHANCED LLC CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name
7
BO
8
LATCH
9
HBVS
10
GND
11
LG
12
VCC
13
NC
14
SW
15
HG
16
BST
HR1001L Rev.1.0
4/18/2016
Description
Input voltage sense and brown-in/brown-out protection. If the voltage on BO is over
2.3V, the IC enables the gate driver. If the voltage on BO is below 1.81V, the IC is disabled.
IC latch off. When the voltage on LATCH exceeds 1.85V, the IC shuts down and lowers its
bias current to its pre-start-up level. LATCH is reset when the voltage on VCC is
discharged below its UVLO threshold. Connect LATCH to GND if the function is not used.
Half-bridge dV/dt sense. To detect the dV/dt of the half-bridge, a high-voltage capacitor is
connected between SW and HBVS. The dV/dt current through HVBS is used to adjust the
dead-time adaptively between the high-side gate and the low-side gate.
Ground. GND is the current return for both the low-side gate driver and the IC bias.
Connect all external ground connections with a trace to GND, one for signals and a second
for pulsed current return.
Low-side gate driver output. The driver is capable of a 0.8A of source/sink peak current
to drive the lower MOSFET of the half-bridge. LG is pulled to GND during UVLO.
Supply voltage. VCC supplies both the IC bias and the low-side gate driver. Use a small
bypass capacitor (e.g.: 0.1µF) to get a clean bias voltage for the IC signal.
High-voltage spacer. No internal connection. NC isolates the high-voltage pin and eases
compliance with safety regulations (creepage distance) on the PCB.
High-side switch source. SW is the current return for the high-side gate drive current. SW
requires careful layout to prevent large spikes below ground.
High-side floating gate driver output. HG is capable of a 0.8A source/sink peak current
to drive the upper MOSFET of the half-bridge. Connect an internal resistor to SW to ensure
that HG does not float during UVLO.
Bias for floating voltage supply of the high-side gate driver. Connect a bootstrap
capacitor between BST and SW. This capacitor is charged by an internal bootstrap diode
driven in phase with the low-side gate driver.
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11
HR1001L – ENHANCED LLC CONTROLLER
BLOCK DIAGRAM
VCC
Vbus
BST
Internal
Circuit
HSG
Driver
Level
Shifter
HG
SW
BURST
Driving
Logic
Standby
LG
1.26V/
1.23V
2V
Lr
VDD
OTP
LSG
Driver
Dtmin/
Dtada/
DTmax
CBOOT
GND
ADTA
Ifmin
Resonant Tank
Current
Cr
HBVS
FSET
Right
Slope Detected/
52µs Timer Out
SS
OCP
Control
Logic
OCR
CMP
Wrong
Current
Polarity
CS
1.5V
0.78V
Disable
LATCH
Q
S
R
Boost _OK
1.85V
UVLO
2.3V/1.81V
CT
VCLK
TIMER
BO
Figure 1: Functional Block Diagram
HR1001L Rev.1.0
4/18/2016
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12
HR1001L – ENHANCED LLC CONTROLLER
APPLICATION INFORMATION
Oscillator
Figure 2 shows the oscillator block diagram. A
modulated current charges and discharges the
CT capacitor repeatedly between its peak valley
thresholds, which determines the oscillator
frequency.
2V
Is-1
FSET
Rss
Iset
Iset
Rfmax
CT
Rfmin
Css
0.9V
GND
CT
3.8 V
+
-
R
+
-
S
Is-2
Q
2Iset
HR1001L
Figure 2: Oscillator Block Diagram
FSET sets the CT charging current, ISET (IS-1).
When CT passes its peak threshold (3.8V), the
filp-flop is set, and a discharging current source
of twice the charge current is enabled. The
difference between these two currents forces
the charging and discharging of CT to be equal.
When the voltage on the CT capacitor falls
below its valley threshold (0.9 V), the flip-flop is
reset and turns off the discharging current
source. This starts a new switching cycle.
Figure 3 shows the detailed waveform of the
oscillator.
CT
LG
TD
An R-C network connected to FSET
externally determines the normal switching
frequency and the soft start switching frequency.
Rfmin from FSET to GND contributes to the
maximum resistance of the external R-C
network when the phototransistor does not
conduct. This sets the FSET minimum source
current, which defines the minimum switching
frequency.
Under normal operation, the phototransistor
adjusts the current flow through Rfmax to
modulate the frequency for output voltage
regulation. When the phototransistor is
saturated, the current through Rfmax is at its
maximum, which sets the frequency at its
maximum.
An R-C in series connected between FSET and
GND shifts the frequency at start-up. Please
see the Soft-Start Operation section on page 14
for details.
Set the minimum and maximum frequencies
with Equation (1) and Equation (2):
1
3 CT Rfmin
(1)
1
3 CT (Rfmin || Rfmax )
(2)
fmin
fmax
Typically, the CT capacitance is between 0.1nF
and 1nF. Calculate Rfmin and Rfmax with
Equation (3) and Equation (4) :
Rfmin
t
HG
t
SW
t
t
1
3 CT fmin
Rfmax
Rfmin
fmax
1
fmin
(3)
(4)
It is recommended to use a CT capacitor less
than or equal to 330pF for best overall
temperature performance.
Figure 3: CT Waveform and Gate Signal
HR1001L Rev.1.0
4/18/2016
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13
HR1001L – ENHANCED LLC CONTROLLER
Soft-Start (SS) Operation
For the resonant half-bridge converter, the
power delivered is inversely proportional to its
switching frequency. To ensure that the
converter starts or restarts with safe currents,
the soft start forces a high initial switching
frequency until the value is controlled by the
closed loop.
The soft start is achieved using an external R-C
series circuit (see Figure 4).
FSET
4
RSS
Rfmin
SS
HR1001L
1
CSS
Figure 4: Soft-Start Block
When the IC starts up, the SS voltage is 0V,
and the soft-start resistor (RSS) is in parallel to
Rfmin. Rfmin and RSS determine the initial
frequency, which can be calculated with
Equation (5):
fstart
1
3 CT (Rfmin||R ss )
(5)
During start-up, CSS charges until its voltage
reaches the reference (2V) and the current
through RSS decays to zero. This period takes
about 5x(RSSxCSS) microseconds. During this
period, the switching frequency change follows
an exponential curve. Initially, the CSS charge
reduces the frequency relatively quickly, but the
rate decreases gradually.
Select an initial frequency (fstart) at least four
times fmin. When selecting CSS, there is a tradeoff between the desired soft-start operation and
the over-current protection (OCP) speed. See
the Over-Current Protection section on page 17
for details.
Adaptive Dead-Time Adjustment (ADTA)
When operating in inductive mode, the soft
switching of the power MOSFETs results in
high efficiency of the resonant converter. A
fixed dead time may result in hard switching at
light load, especially when the magnetizing
inductance (Lm) is too large. A dead time that is
too long may lead to loss of the ZVS state. The
current may change polarity during the dead
time, which can result in capacitive mode
switching. The adaptive dead-time control
adjusts the dead time automatically by
detecting the dV/dt of the half-bridge switching
node (SW).
The HR1001L incorporates an intelligent
adaptive dead-time adjustment (ADTA) logic
circuit, which detects the dV/dt of SW and
inserts a proper dead time automatically. For
the external circuit, connect a capacitor (5pF,
typically) between SW and HBVS to sense
dV/dt. Figure 5 shows the simplified block
diagram of ADTA. Figure 6 shows the operation
waveform of ADTA.
Vbus
BST
HSG
Driver
HG
With the soft start, the current of the resonant
tank increases gradually during start-up.
Select the soft-start R-C network with Equation
(6) and Equation (7) :
Rfmin
Rss
(6)
fstart
1
fmin
Css
HR1001L Rev.1.0
4/18/2016
3 10-3
Rss
Lr
SW
VDD
LG
LG
After the soft-start period, the switching
frequency is dominated by the feedback loop to
regulate the output voltage.
CBOOT
HG
LSG
Driver
CHBVS
GND
Cr
HG
LG
ADTA
Logic
CLK
id
HBVS
D1
CLKN
Figure 5: Block Diagram of ADTA
(7)
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14
HR1001L – ENHANCED LLC CONTROLLER
Dead time adaptively
adjusted
LG
HG
Design CHBVS using Equation (10):
HG
C HBVS
im
ir
700μA C oss
Im
2
(10)
Where Coss is the output capacitance when the
drain-source voltage on the MOSFET is near
zero volts (refer to the Coss characteristics curve
in the MOSFET’s datasheet).
VSW
VHBVS
TDmin
In a typical design, Lm = 870µH, VIN = 450Vdc,
and fmax = 140kHz, and CHBVS is calculated at
4.5pF. 5pF is suitable for most MOSFETs.
Current of CHBVS
id
CLK
Figure 6: Operation Waveform of ADTA
When HG switches off, the SW voltage swings
from high to low due to the resonant tank
current (Ir). Accordingly, this negative dV/dt
pulls current from HBVS via CHBVS. If the dV/dt
current is higher than the internal comparison
current, the HBVS voltage (VHBVS) is pulled
down and clamped at zero. When SW stops
slewing and the differential current stops, VHBVS
begins ramping up. LG turns on after a delay
(minimum dead time). Dead time is defined as
the duration between HG turning off and LG
turning on.
When LG switches off, the SW voltage swings
from low to high, and a positive dV/dt current is
detected via CHBVS. The dead time between LG
turning off and HG turning on is maintained
automatically by sensing the dV/dt current.
To avoid damaging HBVS, CHBVS should be
selected with careful consideration. Keep the
dV/dt current below 65mA using Equation (8):
Figure 7 illustrates a possible dead time by
ADTA logic. Note that there are three kinds of
dead time: minimum dead time (DTMIN),
maximum dead time (DTMAX), and adjusted
dead time (DTADJ), which is between DTMIN and
DTMAX. ADTA logic sets DTMIN = 235ns. When
the SW transition time is smaller than DTMIN, the
logic does not let the gate turn on, which
prevents a shoot-through between the low-side
and high-side MOSFETs. A maximum dead
time (DTMAX = 1µs) forces the gate to turn on,
preventing duty cycle losses or soft switching.
ADTA adjusts the dead time automatically and
ensures zero-voltage switching (ZVS), which
enables more flexibility in the MOSFET and Lm
selection. ADTA also prevents hard switching if
the design does not account for light load or no
load carefully. At light load, the switching
frequency goes high, and the magnetizing
current goes low, risking hard switching that
can lead to a thermal or reliability issue.
DTmin
DTmin
DTmax
Vosc
t
VCLK
id CHBVS
dv
65mA
dt
(8)
LG
If CHBVS is too low to sense the dV/dt, the
minimum voltage change rate (dVmin/dt) must be
accounted for to design the proper CHBVS.
First, calculate the peak magnetizing current (Im)
with Equation (9):
Im
HR1001L Rev.1.0
4/18/2016
Vin
8 Lm fmax
t
Vgate
(9)
HG
LG
HG
t
VSW
t
VDT
t
t1 t2 t3
t4 t5 t6
t7
t8
Figure 7: Dead Time in ADTA
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15
HR1001L – ENHANCED LLC CONTROLLER
If HBVS is not connected, the internal circuit
cannot detect the differential current from HBVS,
so the dead time remains fixed at 350ns.
Figure 8 and Figure 9 show the waveforms of
the dead time when HG turns off and when LG
turns off respectively. ADTA logic inserts the
dead time automatically according to the
transition shape of SW.
If HBVS is pulled down too low by the negative
current of CHBVS, the dead time from HG turning
off to LG turning on may be too long. To clamp
HBVS at zero and ensure an optimum dead
time, connect a Schottky diode (D1) (such as
BAT54) on HBVS to GND.
VSW
VLG
VHG
VHBVS
Capacitive Mode Protection (CMP)
When the resonant HB converter output is in
overload or short circuit condition, it may cause
the converter to run into a capacitive region. In
capacitive mode, the voltage applied to the
resonant tank causes the current of the
resonant tank to lag. Under this condition, the
body diode of one of the MOSFETs is
conducting. The other MOSFET should not be
turned on to avoid device failure. The functional
block diagram of capacitive mode protection
(CMP) is shown in Figure 10.
Figure 11 shows the operating current principle
of CMP. CSPOS and CSNEG stand for the
current polarity, which is generated by
comparing the voltage on CS with the internal
VCSNR and VCSPR voltage reference.
At t0, LG turns off. CSNEG is high, which
means the current is in the correct direction and
is operating in inductive mode.
At t1, HG turns off. CSPOS is high, which
means the current is in the correct direction and
is operating in inductive mode.
Figure 8: Dead Time at High-to-Low Transition
VSW
VLG
VHBVS
VHG
At t2, LG turns off for a second time. CSNEG is
low, indicating that the current is in the wrong
direction (the low-side MOSFET body diode is
conducting), and the converter is operating in
capacitive mode.
SW does not swing high until the current
returns to the correct polarity. DT stays high
and VOSC is stopped, preventing the other
MOSFET from turning on. This prevents
capacitive switching.
At t3, the current returns to the correct polarity,
and the other MOSFET turns on after the dV/dt
current is detected.
Between t2 and t5, the correct current polarity
cannot be detected, or there is so little current
that SW is unable to be pulled up or down.
Figure 9: Dead Time at Low-to-High Transition
HR1001L Rev.1.0
4/18/2016
Eventually, the timer (52µs) for CMP expires,
and the other MOSFET is forced to switch on
(see Figure 11).
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16
HR1001L – ENHANCED LLC CONTROLLER
Vbus
BST
HSG
Driver
2V
CBOOT
HG
HG
FSET
Lr
SW
Iset
VDD
Discharge:
OCR
SS
CMP
LSG
Driver
SET
Q
Q
Detected
Cr
GND
-85 mV
CLR
CS
SET
Q
130µA
D
CLK
Capacitive
D
85 mV
CLK
CMP
TIMER
LG
LG
Re-Start
Q
2.0 V
CLR
Latch Off
Protection
Q
S
QN
R
1.5 V
3.5 V
Control
Logic
Timer
0.28 V
UVLO
Protection Timer
OCP
OCR
Over-Current Protection (OCP)
The HR1001L provides two levels of overcurrent protection (see Figure 13).
0.78 V
HR1001L
Figure 10: Block Diagram of CMP and OCP
DTmin
DTmin
Timer out
Vosc
DTmax
t
VCLK
t
Vgate
LG
HG
LG
VSW
HG
HG
t
Slope Missing
t
Vcs
t
CSNEG
t
CSPOS
t
Vss
t
DT
t
t0
t1
Figure 12 shows the CMP behavior when the
output is shorted. The current polarity goes in
the wrong direction when LG switches off. The
CMP logic detects this capacitive mode
immediately and prevents HG from turning on.
This prevents destructive capacitive switching.
Once the current (Ir) returns to the correct
polarity, SW ramps up, dV/dt current is detected,
and HG turns on at the ZVS state.
t2
t3 t4
t5
t6
Figure 11: Operating Principle of CMP
When capacitive mode operation is detected,
the VSS control signal goes high, turning on an
internal transistor to discharge CSS (after a 1µs
blanking delay). This causes the frequency to
increase to a very high level quickly to limit the
output power. The VSS control is reset, and the
soft start is activated when the first gate driver
is switched off after CMP. The switching
frequency decreases smoothly until the control
loop takes over.
The first level of protection occurs when the
voltage on CS (VCS) exceeds 0.78V. Once this
occurs, two actions take place. First, the
internal transistor connected between SS and
GND turns on for at least 10µs, which
discharges CSS. This creates a sharp increase
in the oscillator frequency, reducing the energy
transferred to the output. Second, an internal
130µA current source turns on to charge CTIMER,
ramping up the TIMER voltage. If VCS drops
below 0.78V before the voltage on TIMER
(VTIMER) reaches 2V, both the discharge of CSS
and the charge of CTIMER are stopped. The
converter resumes normal operation.
tOC is the time for VTIMER to rise from 0V to 2V. It
is a delay time for over-current regulation.
There is no simple relationship between tOC and
CTIMER. Select CTIMER based on experimental
results. Based on experiments, CTIMER may
increase the operating time by 100ms. If VCS is
still larger than 0.78V after VTIMER rises to 2V,
Css is discharged completely. Simultaneously,
the internal 130µA current source continues to
charge CTIMER until VTIMER reaches 3.5V, then
turns off all gate drivers and enters a latch-off
mode. The latch is reset when the voltage on
VCC is lower than the UVLO threshold.
Use Equation (11) to calculate the time it takes
for VTIMER to rise from 2V to 3.5V:
VH
VL
VS
G
G
W
ir
Figure 12: Capacitive Mode Protection Waveform
HR1001L Rev.1.0
4/18/2016
t OP 104 CTIMER
(11)
Even if the latch is reset, the HR1001L will
enter soft start again until VTIMER decreases to
0.28V. Calculate this time period with Equation
(12):
t OFF =RTIMER CTIMER ln
3.5
2.5RTIMER CTIMER (12)
0.28
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17
HR1001L – ENHANCED LLC CONTROLLER
The second level of protection is triggered when
VCS rises to 1.5V. Typically, this condition
occurs when VCS continues to rise during a
short circuit. The IC stops switching
immediately and latches off until the voltage on
VCC drops below the UVLO threshold.
The time sequence of OCP is shown in Figure
13. OCP limits the energy transferred from the
primary side to the secondary side during an
overload or short-circuit condition. Excessive
power consumption due to high continuous
currents can damage the secondary-side
windings and rectifiers. When OCP is triggered,
the converter enters a latched-off protection
mode.
tOC
tOP
tSTOP
VCCH
VCCL
t
VSS
Rs<
C
0.8
(1 r )
ICrpk
CS
(14)
Where ICrpk is the peak current of the resonant
tank at a low input voltage and full load, and
can be calculated with Equation (15):
ICrpk (
NVO 2 IO 2
) ( )
4Lm fs
2N
(15)
Where N is the turns ratio of the transformer, lo
is the output current, Vo is the output voltage, fS
is the switching frequency, and Lm is the
magnetizing inductance.
For capacitive mode detection in no-load or
small-load condition, RS should fulfill the
condition in Equation (16):
tSS
VCC
SS
Calculate RS with Equation (14):
t
ICr
RS
t
VCS-OCP
VCS-OCR
VCS
TIMER
t
VTIMER-SD
VTIMER-fmax
VTIMER-R
t
Vout
Normal
Operation
Shutdown
(Latch)
Over Load
t
OCP(Latch-off Mode)
Soft-Start
Soft-Start
Pmin
Figure 13: OCP Timing Sequence
Current Sensing
There are two current sensing methods:
lossless current sensing and current sensing
with a sense resistor.
Generally, a lossless current sensing solution is
used in high-power applications (see Figure 14).
C
85mV
(1 r )
Im
CS
(16)
In some conditions, especially when a large Lm
is used, it is difficult to satisfy both Equation (14)
and Equation (16). The IC will operate without
CMP function at light load if it is not under the
restriction of Equation (16). The R1 and C1
network is used to attenuate switching noise on
CS. The time constant should be in the range of
100ns.
An alternate solution uses a sense resistor in
series with the resonant tank (see Figure 15).
This method is simple, but causes unnecessary
power loss on the sense resistor.
Lr
CS
R1
C1
Rs
Cs
CS
Cr
Figure 14: Current Sensing with a Lossless
Network
Design the lossless current sensing network
with Equation (13):
Cr
Cs
(13)
100
HR1001L Rev.1.0
4/18/2016
R1
Cr
C1
Rs
Figure 15: Current Sensing with a Sense
Resistor
Design the sense resistor using Equation (17):
RS
0.78
ICrpk
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(17)
18
HR1001L – ENHANCED LLC CONTROLLER
Input Voltage Sensing (BI/BO)
The HR1001L stops switching when the input
voltage drops below a specified value and
restarts when the input voltage returns to normal.
This function guarantees that the resonant halfbridge converter always operates within the
specified input-voltage range. The IC senses the
voltage on BO (VBO) through the tap of a resistor
divider connected to the rectified AC voltage or
the PFC output.
LG, only leaving the 2V reference voltage on
FSET and SS to retain the previous state and
minimize power consumption. When VBURST
exceeds 1.23V by over 30mV, the HR1001L
resumes normal operation.
Based on the burst mode operation principle,
BURST must be connected to the feedback loop.
Figure 17 shows a typical circuit connecting
BURST to the feedback signal for narrow input
voltage range applications.
Figure 16 shows the line-sensing internal block
diagram.
FSET
Rfmax
Rfmin
BURST
4
HR1001L
5
Shutdown
5.5 V
RH
BO 7
VinOK
2.3 V/
1.81 V
RL
Figure 17: Burst Mode Operation Set-Up
HR1001L
Figure 16: Input Voltage Sensing Block
If VBO is higher than 2.3V, the IC provides the
gate driver outputs. The IC does not stop the
gate driver until VBO drops below 1.81V.
For a minimum operation input voltage of the
half-bridge (VIN-min), select a value for RH large
enough to reduce power loss at no load. Then RL
can be calculated with Equation (18):
RL RH
1.81
VIN-min 1.81
(18)
For additional protection, the IC shuts down
when VBO exceeds the internal 5.5V clamp
voltage. When VBO is between 2.3V and 5.5V, the
IC operates normally.
Burst Mode Operation
At light load or in the absence of a load, the
maximum frequency limits the resonant halfbridge switching frequency. To control the output
voltage and limit power consumption, the
HR1001L enables compatible converters to
operate in burst mode. This greatly reduces the
average switching frequency, reducing the
average residual magnetizing current and the
associated losses.
In addition to setting the oscillator maximum
frequency at start-up, Rfmax determines the
maximum
burst
mode
frequency.
After
determining fmax, calculate Rfmax with Equation
(19):
Rfmax
3 Rfmin
8 fmax
1
fmin
(19)
fmax corresponds to a load point (PBurst) where the
peak current flow through the transformer is too
low to cause audible noise.
The above burst mode introduction is based on a
narrow input voltage range. The input voltage
determines the switching frequency as well. This
means that PBurst has a large variance over the
wide input voltage range. To stabilize PBurst over
the input range, use the circuit in Figure 18 to
insert the input voltage signal into the feedback
loop.
Vin
FSET
Rss
Rfmin
Css
Rfmax
BURST
HR1001L
BO
RH
RL
RB1
Css
RB2
Figure 18: Burst Mode Operation Set-Up for a
Wide Input Voltage Range
Operating in burst mode requires setting up
BURST. If the voltage on BURST (VBURST) drops
below 1.23V, the HR1001L shuts down HG and
HR1001L Rev.1.0
4/18/2016
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19
HR1001L – ENHANCED LLC CONTROLLER
RB1 and RB2 in Figure 18 correct against the wide
input voltage range. Select both resistors based
on experimental results. Note that the total
resistance of RB1 and RB2 should be much larger
than RH to minimize the effect on VBO. During
burst mode operation when the load is lower than
PBurst, the switching frequency is clamped at the
maximum frequency. The output voltage must
rise over the setting value to increase the current
flowing through the optocoupler. Therefore, the
voltage on Rfmax rises due to the increased
phototransistor current. Then VBURST drops below
1.23V, triggering the gate signal off state. The
current flows through the optocoupler decreases
until the output voltage falls below the setting
value, causing VBURST to rise. When VBURST
exceeds 1.23V by over 30mV, the IC restarts to
generate the gate signal. The IC operates in this
mode under no load or light load to decrease the
average power consumption.
Latch Operation
The HR1001L provides a simple latch-off function
through LATCH. Applying an external voltage
over 1.85V to HBVS causes the IC to enter a
latched shutdown. After the IC is latched, its
consumption drops. Resetting the IC requires
dropping the VCC voltage below the UVLO
threshold (see Figure 19).
VCC
12
16 BST
High-Side
Driver
15
CBST
HG
14 SW
Level
Shifter
HR1001L
Figure 20: High-Side Gate Driver
Low-Side Gate Driver (LG)
LG provides the gate driver signal for the lowside MOSFET. The maximum voltage on LG is
16V. Under certain applications, a large voltage
spike occurs on LG due to oscillations from the
long-gate driver wire, the MOSFET parasitic
capacitance, and the small gate driver resistor.
This voltage spike is dangerous to LG, so a 15V
Zener diode close to LG and GND is
recommended (see Figure 21).
SW
Vs
Cgd
Low-Side
Driver
Cgs
HR1001L
15 V
LATCH 9
HR1001L
+
S
1.85 V
Cds
Rg
11 LG
Q
10
GND
Disable
UVLO
R
Figure 21: Low-Side Gate Driver
Figure 19: Latch Function Block
High-Side Gate Driver (HG)
The external BST capacitor provides energy to
the high-side gate driver. An integrated bootstrap
diode charges this capacitor through VCC. This
diode simplifies the external driving circuit for the
high-side switch, allowing the BST capacitor to
charge when the low-side MOSFET is on (see
Figure 20).
To provide enough gate driver power
(considering the BST capacitor charge time), use
a 100nF to 470nF capacitor for the BST capacitor.
HR1001L Rev.1.0
4/18/2016
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20
HR1001L – ENHANCED LLC CONTROLLER
Design Example
A 100W LED driver is designed with the
specifications below (see Table 1).
Table 1: Design Example
Input AC voltage
Output voltage
Output current
90 - 305VAC
24V
4.16A
Figure 22 shows the detailed application
schematic. The typical performance and circuit
waveforms are shown in the Typical Performance
Characteristics section.
PFC Stage
LLC Stage
Figure 22: Design Example for a 24V/4.16A Output
HR1001L Rev.1.0
4/18/2016
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21
HR1001L – ENHANCED LLC CONTROLLER
CONTROL FLOW CHART
START
VCC capacitor is charged
by external circuit
N
VCC>11 V
& BO>2.3 V?
Y
Soft Start
Slope
detected?
Y
N
Fixed
DT=350ns
ADTA
Normal operation, IFset
controls fs
Latched
Shutdown
CMP
OCP
Monitor CS
Vcs>85mV or
Vcs2V
Y
Monitor current polarity
once the gate driver is
turning off
Polarity is
wrong?
N
Y
LATCH>1.85V
1. Discharge soft- start
capacitor
(10µs), increasing
switching frequency
2. TIMER capacitor is
charged (10µs) by an
internal 130µA current
source
1. Latch off the
switching pulse
2. Soft-start
capacitor is fully
discharged
N
Y
CMP timer out?
1. Stop
discharging the
soft-start capacitor
2. Stop charging
the TIMER
capacitor
3. Continue
normal operation
No slope
detected?
Monitor BO
Monitor VCC
Monitor Burst
Y(Latch)
N
N
BO>5.5 V or
BO
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