FDN337N

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This literature is subject to all applicable copyright laws and is not for resale in any manner. March 1998 FDN337N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features TM SuperSOT -3 N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. SuperSOTTM-8 SuperSOTTM-6 SOT-23 2.2 A, 30 V, RDS(ON) = 0.065 Ω @ VGS = 4.5 V RDS(ON) = 0.082 Ω @ VGS = 2.5 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SO-8 SOIC-16 SOT-223 D D 3 37 S TM SuperSOT -3 G Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS ID PD Maximum Power Dissipation TA = 25oC unless other wise noted FDN337N Units 30 V Gate-Source Voltage - Continuous ±8 V Drain/Output Current - Continuous 2.2 A - Pulsed TJ,TSTG S G 10 (Note 1a) 0.5 (Note 1b) 0.46 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W © 1998 Fairchild Semiconductor Corporation FDN337N Rev.C Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC 30 V IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward VGS = 8 V,VDS = 0 V IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS = 0 V -100 nA TJ = 55°C ON CHARACTERISTICS mV/ oC 41 1 µA 10 µA 100 nA (Note) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA ∆VGS(th)/∆TJ Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC 0.4 RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 2.2 A 0.7 1 V mV/ oC -2.3 TJ =125°C VGS = 2.5 V, ID = 2 A 0.054 0.065 0.08 0.11 0.07 0.082 10 Ω ID(ON) On-State Drain Current VGS = 4.5 V, VDS = 5 V A gFS Forward Transconductance VDS = 5 V, ID = 2.2 A 13 S VDS = 10 V, VGS = 0 V, f = 1.0 MHz 300 pF 145 pF 35 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge (Note) VDD = 5 V, ID = 1 A, VGS = 4.5 V, RGEN = 6 Ω VDS = 10 V, ID = 2.2 A, VGS = 4.5 V 4 10 ns 10 18 ns 17 28 ns 4 10 ns 7 9 nC 1.1 nC 1.9 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note) 0.65 0.42 A 1.2 V Note: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Typical RθJA using the board layouts shown below on FR-4 PCB in a still air environment : Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. a. 250oC/W when mounted on 0.02 in2 pad of 2oz Cu. a b. 270oC/W when mounted on a 0.001 in2 pad of 2oz Cu. FDN337N Rev.C Typical Electrical Characteristics VGS = 4.5V 5 2 R DS(ON ) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) 6 3.0 2.5 2.0 4 3 1.5 2 1 1.8 1.4 2.5 1.2 0 0.3 0.6 0.9 1.2 3.0 3.5 4.5 1 0.8 0 VGS = 2.0V 1.6 1.5 0 1 2 3 4 I D , DRAIN CURRENT (A) VDS , DRAIN-SOURCE VOLTAGE (V) 0.25 R DS(ON) , ON-RESISTANCE (OHM) R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.6 ID = 2.2A VGS = 4.5 V 1.2 1 0.8 0.6 -50 6 Figure 2. On-Resistance Variation with Drain Current and Gate Figure 1. On-Region Characteristics. 1.4 5 I D = 1.1A 0.2 0.15 25°C 0.05 0 -25 0 25 50 75 100 125 125°C 0.1 150 1 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) T , JUNCTION TEMPERATURE (°C) J Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. ID , DRAIN CURRENT (A) V DS = 5.0V TJ = -55°C 6 I S , REVERSE DRAIN CURRENT (A) 7 25°C 125°C 5 4 3 2 1 0 0 0.5 V GS 1 1.5 2 , GATE TO SOURCE VOLTAGE (V) 2.5 4 2 VGS = 0V TJ = 125°C 0.5 25°C 0.1 -55°C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 1 VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. FDN337N Rev.C Typical Electrical Characteristics (continued) 1000 I D = 2.2A VDS = 5V 4 500 15V 10V CAPACITANCE (pF) VGS , GATE-SOURCE VOLTAGE (V) 5 3 2 Ciss 200 Coss 100 50 1 0 20 0.1 0 2 4 6 f = 1 MHz VGS = 0V Crss 0.2 8 0.5 V DS 1 2 5 10 20 , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 50 20 5 VGS = 4.5V SINGLE PULSE Rθ JA =250 °C/W TA = 25°C 0.03 0.01 0.1 0.5 V 30 20 10 0 0.0001 1 DS ms 1s 10s DC 0.3 0.1 POWER (W) 100 1 SINGLE PULSE R θJA =270° C/W TA = 25°C 40 10m s 2 2 5 10 20 0.001 50 0.01 0.1 1 10 100 300 SINGLE PULSE TIME (SEC) , DRAI N-SOURCE VOLTAGE (V) Figure 10. Single Pulse Maximum Power Dissipation. Figure 9. Maximum Safe Operating Area. 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE I D , DRAIN CURRENT (A) 1m s IT LIM N) S(O RD 10 0.5 D = 0.5 0.2 0.1 0.05 0.02 0.01 0.2 R θJA (t) = r(t) * RθJA R θJA = 270 °C/W 0.1 0.05 0.02 0.01 P(pk) t1 Single Pulse 0.005 Duty Cycle, D = t1 /t2 0.002 0.001 0.0001 t2 TJ - TA = P * RθJA (t) 0.001 0.01 0.1 1 10 100 300 t1 , TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. FDN337N Rev.C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET  VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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