Precision Operational
Amplifier, 25 mV Offset,
Zero-Drift, 36 V Supply,
2 MHz
NCS21911, NCV21911,
NCS21912, NCV21912,
NCS21914, NCV21914
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MARKING
DIAGRAMS
The NCS2191x family of high precision op amps feature low input
offset voltage and near−zero drift over time and temperature. These op
amps operate over a wide supply range from 4 V to 36 V with low
quiescent current. The rail−to−rail output swings within 10 mV of the
rails. The family includes the single channel NCS(V)21911, the dual
channel NCS(V)21912, and the quad channel NCS(V)21914 in a
variety of packages. All versions are specified for operation from
−40°C to +125°C. Automotive qualified options are available under
the NCV prefix.
5
5
AEZAYWG
G
1
TSOP−5
CASE 483
1
8
8
1
Micro8
CASE 846A−02
1
Features
•
•
•
•
•
•
•
•
•
Input Offset Voltage: ±25 mV max
Zero−Drift Offset Voltage: ±0.085 mV/°C max
Voltage Noise Density: 22 nV/√Hz typical
Unity Gain Bandwidth: 2 MHz typical
Supply Voltage: 4 V to 36 V
Quiescent Current: 570 mA max
Rail−to−Rail Output
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−free, Halogen free/BFR free and are RoHS
compliant
•
•
•
•
•
•
8
8
1
SOIC−8 NB
CASE 751−07
1
914
ALYWG
G
14
1
TSSOP−14 WB
CASE 948G
1
14
1
SOIC−14 NB
CASE 751A−03
Temperature Measurements
Transducer Applications
Electronic Scales
Medical Instrumentation
Current Sensing
Automotive
912
ALYW
G
14
914G
AWLYWW
14
Typical Applications
912
AYWG
G
1
XXXXX = Specific Device Code
A
= Assembly Location
L or WL = Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2013
January, 2021 − Rev. 5
1
Publication Order Number:
NCS21911/D
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
PIN CONNECTIONS
Single Channel Configuration
NCS21911
OUT
1
VSS
2
IN+
3
5
VDD
4
IN−
Dual Channel Configuration
NCS21912
OUT 1
1
IN− 1
2
−
IN+ 1
3
+
VSS
4
Quad Channel Configuration
NCS21914
OUT 1
1
OUT 2
IN− 1
2
−
− 13 IN− 4
6
IN− 2
IN+ 1
3
+
+ 12 IN+ 4
5
IN+ 2
VDD
4
IN+ 2
5
+
+ 10
IN+ 3
IN− 2
6
−
−
9
IN− 3
8
OUT 3
8
VDD
7
−
+
OUT 2
14 OUT 4
11
7
VSS
ORDERING INFORMATION
Channels
Device
Package
Shipping †
Single
NCS21911SN2T1G
SOT23−5 / TSOP−5
3000 / Tape & Reel
Dual
NCS21912DR2G
SOIC−8
2500 / Tape & Reel
NCS21912DMR2G
MICRO−8
4000 / Tape & Reel
NCS21914DR2G
SOIC−14
2500 / Tape & Reel
NCS21914DTBR2G
TSSOP−14
2500 / Tape & Reel
Channels
Device
Package
Shipping †
Single
NCV21911SN2T1G
SOT23−5 / TSOP−5
3000 / Tape & Reel
Dual
NCV21912DR2G
SOIC−8
2500 / Tape & Reel
NCV21912DMR2G
MICRO−8
4000 / Tape & Reel
NCV21914DR2G
SOIC−14
2500 / Tape & Reel
NCV21914DTBR2G
TSSOP−14
2500 / Tape & Reel
Quad
Automotive Qualified
Quad
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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2
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
40
V
VSS – 0.3 to VDD + 0.3
V
Supply Voltage (VDD− VSS)
INPUT AND OUTPUT PINS
Input Voltage (Note 1)
Differential Input Voltage (Note 2)
±17
V
Input Current (Notes 1 and 2)
±10
mA
Continuous
mA
Operating Temperature
–40 to +125
°C
Storage Temperature
–65 to +150
°C
Junction Temperature
+150
°C
Human Body Model (HBM)
3000
V
Charged Device Model (CDM)
2000
V
100
mA
Output Short Circuit Current (Note 3)
TEMPERATURE
ESD RATINGS (Note 4)
OTHER RATINGS
Latch−up Current (Note 5)
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
2. The inputs are diode connected with a total input protection of 1.65 kW, increasing the absolute maximum differential voltage to ±17 VDC.
If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input
current to ±10 mA.
3. Short−circuit to VDD or VSS. Short circuits to either rail can cause an increase in the junction temperature. The total power dissipation must
be limited to prevent the junction temperature from exceeding the 150_C limit.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
5. Latch−up Current tested per JEDEC standard JESD78E (AEC−Q100−004).
THERMAL INFORMATION (Note 6)
Rating
Thermal Resistance, Junction to Ambient
Symbol
Package
Value
Unit
qJA
TSOP−5 /
SOT23−5
170
°C/W
Micro8/MSOP8
116
SOIC−8
87
SOIC−14
59
TSSOP−14
78
6. As mounted on an 80x80x1.5 mm FR4 PCB with 2S2P, 2 oz copper, and a 200 mm2 heat spreader area. Following JEDEC JESD51−7
guidelines.
OPERATING CONDITIONS
Symbol
Range
Unit
Supply Voltage (VDD − VSS)
Parameter
VS
4 to 36
V
Specified Operating Temperature Range
TA
−40 to 125
°C
VCM
VSS to VDD−1.5
V
VDIFF
±17
V
Input Common Mode Voltage Range
Differential Voltage (Note 7)
7. The inputs are diode connected with a total input protection of 1.65 kW, increasing the absolute maximum differential voltage to ±17 VDC.
If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input
current to ±10 mA.
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NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
ELECTRICAL CHARACTERISTICS VS = 4 V to 36 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = –40°C to 125°C, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
VOS
±1
±25
mV
Offset Voltage Drift vs Temp
DVOS/DT
±0.02
±0.085
mV/°C
Input Bias Current (Note 8)
IIB
±100
±500
pA
±3500
pA
Input Offset Current (Note 8)
IOS
±200
±500
pA
±3500
pA
Offset Voltage
Common Mode Rejection Ratio
CMRR
VSS ≤ VCM ≤
VDD−1.5 V
VS = 36 V
140
150
dB
130
VS = 12 V
(Note 8)
130
VS = 8 V
(Note 8)
130
VS = 4 V
120
150
120
140
120
130
110
Input Capacitance
EMI Rejection Ratio
CIN
Common Mode
3
pF
f = 5 GHz
100
dB
f = 400 MHz
80
EMIRR
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
Open Loop Output Impedance
Output Voltage High, Referenced to
Rail
Output Voltage Low, Referenced to
Rail
Short Circuit Current
Capacitive Load Drive
AVOL
VSS + 0.5 V < VO < VDD – 0.5 V
130
150
125
135
dB
ZOUT_OL
No Load
See
Figure 23
VOH
No Load
5
10
RL = 10 kW
100
210
140
250
VOL
ISC
W
No Load
5
10
RL = 10 kW
100
210
140
250
Sinking Current
18
Sourcing Current
16
CL
mV
mV
mA
1
nF
DYNAMIC PERFORMANCE
GBW
CL = 100 pF
2
MHz
Gain Margin
AM
CL = 100 pF
13
dB
Phase Margin
ϕM
CL = 100 pF
55
°
Slew Rate
SR
Settling Time
tS
Gain Bandwidth Product
Overload Recovery Time
tOR
G = +1
VS = 36 V
1.6
V/ms
0.1%
20
ms
0.01%
45
ms
1
ms
VS = ±18 V, AV = −10,
VIN = ±2.5 V
8. Guaranteed by characterization and/or design.
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4
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
ELECTRICAL CHARACTERISTICS VS = 4 V to 36 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = –40°C to 125°C, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
THD+N
fIN = 1 kHz, AV = 1, VOUT = 1
Vrms
Voltage Noise Density
eN
Current Noise Density
iN
Voltage Noise, Peak−to−Peak
Voltage Noise, RMS
PSRR
VS = 4 V to 36 V
Min
Typ
Max
Unit
NOISE PERFORMANCE
Total Harmonic Distortion + Noise
0.0003
%
f = 1 kHz
22
nV/√Hz
f = 1 kHz
100
fA/√Hz
ePP
f = 0.1 Hz to 10 Hz
400
nVPP
erms
f = 0.1 Hz to 10 Hz
70
nVrms
POWER SUPPLY
Power Supply Rejection Ratio
0.02
130
Quiescent Current
IQ
Per channel
0.3
475
570
570
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5
mV/V
dB
154
mA
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
GRAPHS
Typical performance at TA = 25°C, unless otherwise noted.
30
16
VS = 36 V
VCM = mid−supply
105 units
25
20
15
10
5
0
−20 −16 −12
VS = 36 V
VCM = mid−supply
105 units
14
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
35
−8 −4
0
4
8
OFFSET VOLTAGE (mV)
12
16
12
10
8
6
4
2
0
−0.10
20
−0.06
−0.02
0.02
0.06
OFFSET VOLTAGE DRIFT (mV/°C)
Figure 1. Offset Voltage Distribution
Figure 2. Offset Voltage Drift Distribution
15
15
VS = 36 V
VCM = mid−supply
5 typical units
5
0
−5
−10
5
0
−5
−10
−15
−25
0
25
50
75
TEMPERATURE (°C)
100
VS = 4 V
5 typical units
10
OFFSET VOLTAGE (μV)
OFFSET VOLTAGE (μV)
10
−15
−50
125
0
Figure 3. Offset Voltage vs. Temperature
15
OFFSET VOLTAGE (μV)
OFFSET VOLTAGE (μV)
−5
−10
15
20
25
30
3
VCM = mid−supply
5 typical units
10
0
10
1
1.5
2
2.5
COMMON MODE VOLTAGE (V)
15
5
5
0.5
Figure 4. Offset Voltage vs. Common Mode
Voltage
VS = 36 V
5 typical units
10
−15
0
0.10
5
0
−5
−10
−15
35
4
COMMON MODE VOLTAGE (V)
Figure 5. Offset Voltage vs. Common Mode
Voltage
8
12
16
20
24
28
SUPPLY VOLTAGE (V)
32
Figure 6. Offset Voltage vs. Power Supply
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6
36
120
25
100
20
PHASE MARGIN
10
60
GAIN
40
20
5
0
−5
−10
0
VS = 4 V, 36 V
RL = 10 kW
−20
10
1k
100k
FREQUENCY (Hz)
−20
10k
10M
1600
VS = 36 V
INPUT CURRENT (pA)
INPUT CURRENT (pA)
200
100
0
−100
−300
0
IIB+
IIB−
IOS
5
10
15
20
25
COMMON MODE VOLTAGE (V)
30
10M
VS = 36 V
VCM = mid−supply
800
400
0
−400
−40
35
IIB+
IIB−
IOS
1200
Figure 9. Input Current vs. Common Mode
Voltage
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120 140
Figure 10. Input Current vs. Temperature
120
140
RL = 10 kW
COMMON MODE REJECTION (dB)
POWER SUPPLY REJECTION (dB)
100k
1M
FREQUENCY (Hz)
Figure 8. Closed Loop Gain vs. Frequency
300
−200
AV = 1
AV = −1
AV = 10
−15
Figure 7. Open Loop Gain and Phase vs.
Frequency
120
100
80
PSRR+
PSRR−
60
VS = ±2, PSRR+
VS = ±18, PSRR+
VS = ±2, PSRR−
VS = ±18, PSRR−
40
20
0
VS = 36 V
RL = 10 kW
CL = 25 pF
15
80
GAIN (dB)
GAIN (dB) AND PHASE MARGIN (°)
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
VS = 4 V, 36 V
RL = 10 kW
100
80
60
40
20
0
10
Figure 11. PSRR vs. Frequency
100
1k
10k
FREQUENCY (Hz)
100k
Figure 12. CMRR vs. Frequency
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7
1M
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
0.5
5
VS = 4 V, 36 V
5 typical units
0.4
4
0.3
3.5
CMRR (mV/V)
0.2
PSRR (mV/V)
VCM = VSS+0.5 to VDD−1.5 V
VCM = VSS to VDD−1.5 V
4.5
0.1
0
−0.1
−0.2
−0.3
3
2.5
2
1.5
1
0.5
−0.4
0
−0.5
−50
−25
0
25
50
75 100
TEMPERATURE (°C)
125
−0.5
−50
150
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−50
400
VCM = VSS+0.5 to VDD−1.5 V
VCM = VSS to VDD−1.5 V
125
150
VS = 36 V
200
100
0
−100
−200
−300
−25
0
25
50
75 100
TEMPERATURE (°C)
1k
125
−400
150
0
0.01
VS = 36 V
100
10
10
100
1k
FREQUENCY (Hz)
10k
1
2
3
4
5
6
TIME (s)
7
8
9
Figure 16. 0.1 Hz to 10 Hz Noise
THD + N (%)
VOLTAGE NOISE (nV/√Hz)
25
50
75 100
TEMPERATURE (°C)
300
Figure 15. CMRR vs. Temperature at VS = 36 V
1
1
0
Figure 14. CMRR vs. Temperature at VS = 4 V
VOLTAGE (nV)
CMRR (mV/V)
Figure 13. PSRR vs. Temperature
−25
100k
VS = 36 V
RL = 10 kW
BW = 80 kHz
VIN = 1 Vrms
AV = 1
AV = −1
0.001
0.0001
10
Figure 17. Voltage Noise Density vs.
Frequency
100
1k
FREQUENCY (Hz)
Figure 18. THD+N vs. Frequency
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10k
10
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
0.50
VS = 36 V
RL = 10 kW
BW = 80 kHz
f = 1 kHz
THD + N (%)
1
AV = 1
AV = −1
0.48
QUIESCENT CURRENT (mA)
10
0.1
0.01
0.001
0.0001
0.01
0.1
1
OUTPUT AMPLITUDE (Vrms)
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
0
10
Figure 19. THD+N vs. Output Amplitude
12
16
20
24
SUPPLY VOLTAGE (V)
28
32
36
3.0
0.48
0.46
OPEN LOOP GAIN (mV/V)
QUIESCENT CURRENT (mA)
8
Figure 20. Quiescent Current vs. Supply
Voltage
0.50
0.44
0.42
0.40
0.38
0.36
0.34
VS = 4 V
VS = 36 V
0.32
0.30
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
125
2.0
1.5
1.0
0.5
0.0
−50
150
AV = 1
AV = −1
2.5
Figure 21. Quiescent Current vs. Temperature
−25
0
25
50
75 100
TEMPERATURE (°C)
125
150
Figure 22. Open Loop Gain vs. Temperature
50
10k
Riso = 0 W
Riso = 25 W
Riso = 50 W
45
1k
40
OVERSHOOT (%)
OUTPUT IMPEDANCE (W)
4
100
10
VS = 36 V
RL = 10 kW
AV = 1 V/V
35
30
25
20
15
10
1
5
0.1
1
10
100
100k
1k
10k
FREQUENCY (Hz)
1M
0
10M
0
Figure 23. Open Loop Output Impedance vs.
Frequency
200
400
600
CAPACITIVE LOAD (pF)
800
Figure 24. Small Signal Overshoot vs.
Capacitive Load (100 mV Output Step)
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9
1000
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
5
70
4
2
40
30
20
1
0
−1
−2
−3
10
−4
800
−5
1000
TIME (100 ms/div)
Figure 25. Small Signal Overshoot vs.
Capacitive Load (100 mV Output Step)
Figure 26. No Phase Reversal
4
20
3
15
2
10
1
5
0
0
−1
−5
−2
−3
−4
VS = ±18 V
RL = 10 kW
CL = 15 pF
AV = −10
−10
Input
Output
OUTPUT VOLTAGE (V)
600
400
CAPACITIVE LOAD (pF)
VS = 8 V
RL = 10 kW
CL = 15 pF
−15
−20
TIME (1 ms/div)
Figure 27. Positive Overload Recovery
4
3
Input
Output
2
VS = ±18 V
RL = 10 kW
CL = 15 pF
AV = −10
20
15
10
1
5
0
0
−1
−5
−2
−10
−3
−15
−4
−20
TIME (1 ms/div)
Figure 28. Negative Overload Recovery
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OUTPUT VOLTAGE (V)
200
INPUT VOLTAGE (V)
0
0
Input
Output
3
VOLTAGE (V)
50
RL = 10 kW
AV = −1
100 mV Step
Riso = 0 W
Riso = 25 W
Riso = 50 W
INPUT VOLTAGE (V)
OVERSHOOT (%)
60
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
0.1
0.08
0.06
0.08
0.06
0.04
VOLTAGE (V)
0.04
VOLTAGE (V)
0.1
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = 1
0.02
0
−0.02
−0.04
−0.06
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = −1
0.02
0
−0.02
−0.04
−0.06
Input
Output
−0.08
−0.1
Input
Output
−0.08
−0.1
TIME (10 ms/div)
TIME (10 ms/div)
Figure 29. Non−Inverting Small Signal Step
Response
10
10
8
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = 1
8
6
6
4
VOLTAGE (V)
4
VOLTAGE (V)
Figure 30. Inverting Small Signal Step
Response
2
0
−2
−4
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = −1
2
0
−2
−4
−6
−6
Input
Output
−8
−10
Input
Output
−8
−10
TIME (10 ms/div)
TIME (10 ms/div)
Figure 31. Non−Inverting Large Signal Step
Response
0.01
0.01
VS = 36 V
RL = 10 kW
CL = 15 pF
VIN = 10 V Step
0.008
0.006
0.002
0
−0.002
−0.004
−0.006
0.006
0.004
0.002
0
−0.002
−0.004
−0.006
Output
Input
−0.008
VS = 36 V
RL = 10 kW
CL = 15 pF
VIN = 10 V Step
0.008
VOLTAGE (V)
0.004
VOLTAGE (V)
Figure 32. Inverting Large Signal Step
Response
Output
Input
−0.008
−0.01
−0.01
TIME (5 ms/div)
TIME (5 ms/div)
Figure 33. Large Signal Settling Time,
Low−to−High
Figure 34. Large Signal Settling Time,
High−to−Low
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NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
20
35
ISC, Source
ISC, Sink
VS = 36 V
15
10
5
0
−5
−10
−15
−20
−25
−50
0
50
TEMPERATURE (°C)
25
20
VS = ±9 V
15
10
VS = ±5 V
5
0
1k
150
100
VS = ±18 V
30
OUTPUT VOLTAGE (Vpp)
SHORT CIRCUIT CURRENT (mA)
25
VS = ±2.5 V
Figure 35. Short Circuit Current vs.
Temperature
10M
VS = 36 V
TA = −40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 125°C
2.5
2
OUTPUT VOLTAGE HIGH (V)
OUTPUT VOLTAGE LOW (V)
1M
36
1.5
1
0.5
VS = 36 V
0
2
4
6
8 10 12 14 16 18
OUTPUT CURRENT (mA)
35.5
35
34.5
TA = −40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 125°C
34
33.5
33
0
20 22 24
2
Figure 37. Output Voltage Low vs. Output
Current
140
120
0
VS = 36 V
VIN = 100 mVp
AV = 1
6
8 10
12
14
OUTPUT CURRENT (mA)
16
18
20
VS = 36 V
−20
100
80
60
40
20
−40
−60
−80
−100
−120
−140
0
10M
4
Figure 38. Output Voltage High vs. Output
Current
CROSSTALK (dB)
160
EMI REJECTION (dB)
100k
FREQUENCY (Hz)
Figure 36. Maximum Output Voltage vs.
Frequency (AV = 1 for VS = +2.5 V, +5 V, +9 V;
AV = 2 for VS = +18 V)
3
0
10k
100M
1G
FREQUENCY (Hz)
−160
10G
10
Figure 39. EMIRR IN+ vs. Frequency
100
1K
100K
10K
FREQUENCY (Hz)
1M
Figure 40. Channel−to−Channel Crosstalk
www.onsemi.com
12
10M
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
APPLICATION INFORMATION
Overview
The NCS21911 series of amplifiers uses a
chopper−stabilized architecture, which provides the
advantage of minimizing offset voltage drift over
temperature and time. The simplified block diagram is
shown in Figure 41. Unlike the classical chopper
architecture, the chopper stabilized architecture has two
signal paths.
The NCS21911, NCS21912, and NCS21914 precision op
amps provide low offset voltage and zero drift over
temperature. With a maximum offset voltage of 25 mV and
input common mode voltage range that includes ground, the
NCS21911 series is well−suited for applications where
precision is required, such as low side current sensing and
interfacing with sensors.
Main amp
IN+
+
IN−
− +
Chopper
+
−
−
+
Chopper
RC notch filter
−
OUT
RC notch filter
Figure 41. Simplified NCS21911 Block Diagram
only does this help retain high frequency components of the
input signal, but it also improves the loop gain at low
frequencies. This is especially useful for low−side current
sensing and sensor interface applications where the signal is
low frequency and the differential voltage is relatively
small.
In Figure 41, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 250 kHz. The chopper−stabilized
architecture is optimized for best performance at
frequencies up to the related Nyquist frequency (1/2 of the
offset correction frequency). As the signal frequency
exceeds the Nyquist frequency, 125 kHz, aliasing may occur
at the output. This is an inherent limitation of all chopper and
chopper−stabilized architectures. Nevertheless, the
NCS21911 series op amps have minimal aliasing up to
200 kHz and are less susceptible to aliasing effects when
compared to competitor parts from other manufacturers.
ON Semiconductor’s patented approach utilizes two
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
The chopper−stabilized architecture also benefits from
the feed−forward path, which is shown as the upper signal
path of the block diagram in Figure 41. This is the high speed
signal path that extends the gain bandwidth up to 2 MHz. Not
Application Circuits
Low−Side Current Sensing
Low−side current sensing is used to monitor the current
through a load. This method can be used to detect
over−current conditions and is often used in feedback
control, as shown in Figure 42. A sense resistor is placed in
series with the load to ground. Typically, the value of the
sense resistor is less than 100 mW to reduce power loss
across the resistor. The op amp amplifies the voltage drop
across the sense resistor with a gain set by external resistors
R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
resistors are required for high accuracy, and the gain is set
to utilize the full scale of the ADC for the highest resolution.
www.onsemi.com
13
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
R3
VLOAD
VDD
VDD
Load
R1
VDD
Microcontroller
+
RSENSE
ADC
control
−
R2
R4
Figure 42. Low−Side Current Sensing
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Differential Amplifier for Bridged Circuits
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 43. In the measurement, the voltage change that is
RF
VDD
R1
R3
VDD
R3
−
Rx
+
Figure 43. Wheatstone Bridge Circuit Amplification
EMI Susceptibility and Input Filtering
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric coefficients and prevent
temperature gradients from heat sources or cooling fans.
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS2191x
integrates low−pass filters to decrease its sensitivity to EMI.
Figure 39 shows the EMIRR performance.
General Layout Guidelines
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
www.onsemi.com
14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
14X
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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