OKDx-T/12-W12-001-C
www.murata-ps.com
12A Digital PoL DC-DC Converter Series
PRODUCT OVERVIEW
Typical units
FEATURES
SIP, Horizontal mount, or SMT package
4.5 to 14Vdc Input voltage range
0.6 to 5.0Vdc Output voltage range, up to 12A
The OKDx-T/12-W12 is a high efficiency, digital
Point-of-Load (PoL) DC-DC power converter
capable of delivering 12A/60W. Designed for a
minimal footprint, the high power-density module
measures just 20.8 x 7.6 x 15.6 mm (0.82 x 0.3 x
0.612 in) (SIP version).
PMBus™ compatibility allows monitoring and
configuration of critical system level performance
requirements. Apart from standard PoL performance and safety features like OVP, OCP, OTP, and
UVLO, these digital converters have advanced features: Adaptive compensation of PWM control loop,
fast loop transient response, synchronization, and
phase spreading. These converters are ideal for use
in telecommunications, networking, and distributed
power applications
High efficiency, typ. 97.1% at 5Vin, 3.3Vout ½
load
Configuration and Monitoring via PMBus™
Synchronization & Phase Spreading
Voltage Tracking & Voltage margining
MTBF 21.2 Mh
ORDERING GUIDE
Model Number
OKDX-T/12-W12-001-C
OKDX-T/12-W12E-001-C
OKDH-T/12-W12-001-C
OKDY-T/12-W12-001-C
Package Type
SIP
SIP
Horizontal Mount TH
Surface Mount
Input
Output
4.5-14V
0.6-5.0V, 12A / 60W
PART NUMBER STRUCTURE
OKD X - T / 12 - W12 E - 001 - C
C = RoHS-6 compliant
Digital Non-isolated PoL
X = SIP
H = Horizontal mount
Y = Surface mount
Trimmable Output
Voltage Range
0.6 - 5Vdc
Maximum Rated Output
Current in Amps
For full details go to
www.murata-ps.com/rohs
001 = Positive logic (On/Off control)
Options:
E = 5.5mm pin length (SIP only)
Blank = Standard pin length
InputVoltage Range
4.5 - 14Vdc
PM
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MDC_OKDx-T/12-W12-C.A02 Page 1 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Absolute Maximum Ratings
Characteristics
Min
TP1
Operating temperature (see Thermal Consideration section)
TS
Storage temperature
VI
Input voltage (See Operating Information Section for input and output voltage relations)
Typ
Max
Unit
-40
120
°C
-40
125
°C
-0.3
16
V
6.5
V
Logic I/O voltage
CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC, GCB, PG
-0.3
Ground voltage differential
-S, PREF, GND
-0.3
0.3
V
Analog pin voltage
VO, +S, VTRK
-0.3
6.5
V
Stress in excess of Absolute Maximum Ratings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are
normally tested with one parameter at a time exceeding the limits in the Electrical Specification. If exposed to stress above these limits, function and performance
may degrade in an unspecified manner.
Configuration File
This product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and performance of the product.
The Electrical Specification table shows parameter values of functionality and performance with the default configuration file, unless otherwise specified. The default
configuration file is designed to fit most application need with focus on high efficiency. If different characteristics are required it is possible to change the
configuration file to optimize certain performance characteristics. In this Technical specification examples are included to show the possibilities with digital control.
See Operating Information section for information about trade offs when optimizing certain key performance characteristics.
Fundamental Circuit Diagram
VIN
VOUT
CI
CO
GND
+Sense
-Sense
(PGOOD)
SALERT
VSET
CTRL
Controller and digital interface
SYNC
SCL
SDA
SA0
GCB
VTRK
PREF
Ci=22 μF Co =100 μF
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MDC_OKDx-T/12-W12-C.A02 Page 2 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Electrical Specification
TP1 = -30 to +95°C, VI = 4.5 to 14 V, VI > VO + 1.0 V
Typical values given at: TP1 = +25°C, VI = 12.0 V, max IO, unless otherwise specified under Conditions.
Default configuration file, 190 10-CDA 102 0207/001.
External CIN = 470 µF/10 mΩ, COUT = 470 µF/10 mΩ. See Operating Information section for selection of capacitor types.
Sense pins are connected to the output pins.
Characteristics
VI
Conditions
Input voltage rise time
Output voltage without pin strap
Output voltage adjustment range
Output voltage adjustment including
margining
Output voltage set-point resolution
Output voltage accuracy
VO
Load regulation; IO = 0 - 100%
VOac
Output ripple & noise
CO=470 μF (minimum external
capacitance). See Note 12
IO
Output current
IS
Static input current at max IO
Ilim
Current limit threshold
Short circuit
current
RMS, hiccup mode,
See Note 3
50% of max IO
η
Efficiency
max IO
Pd
Pli
Max
Unit
2.4
V/ms
0.60
Power dissipation at max IO
Input idling
power
(no load)
Default configuration:
Continues Conduction
Mode, CCM
Typ
5.0
V
V
0.54
5.5
V
1.2
±0.025
Including line, load, temp.
See Note 15
-1
Internal resistance +S/-S to VOUT/GND
Line regulation
Isc
Min
monotonic
1
4.7
2
2
2
3
3
2
2
2
20
30
60
100
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
See Note 17
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
% VO
0.001
Ω
mV
mV
mVp-p
12
0.76
1.17
3.53
4.1
14
8
6
5
4
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
VO = 0.6 V
VO = 1.0 V
VO =3.3V
82.6
88.5
94.7
95.7
78.5
85.4
93.6
94.9
2.05
2.11
2.66
VO = 5.0 V
3.15
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
0.33
0.35
0.56
0.99
A
A
20
VO = 0.6 V
VO = 1.0 V
VO = 3.3V
VO = 5.0 V
%
A
A
%
%
W
W
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MDC_OKDx-T/12-W12-C.A02 Page 3 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Characteristics
PCTRL
Ci
Co
COUT
Vtr1
ttr1
fs
Input standby
power
Conditions
Turned off with
CTRL-pin
Internal input capacitance
Internal output capacitance
Total external output capacitance
ESR range of capacitors
(per single capacitor)
Load transient
peak voltage
deviation
Load step
25-75-25% of
max IO
Load transient
recovery time,
Note 5
Load step
25-75-25% of
max IO
Default configuration
di/dt = 2 A/μs
CO=470 μF (minimum
external capacitance)
see Note 13
Default configuration
di/dt = 2 A/μs
CO=470 μF (minimum
external capacitance)
see Note 13
Switching frequency
Switching frequency range
Switching frequency set-point accuracy
Control Circuit PWM Duty Cycle
Minimum Sync Pulse Width
Synchronization Frequency Tolerance
Input Under Voltage
Lockout,
UVLO
Input Over Voltage
Protection,
IOVP
Power Good, PG,
See Note 2
Output voltage
Over/Under Voltage
Protection,
OVP/UVP
UVLO threshold
UVLO threshold range
Set point accuracy
UVLO hysteresis
UVLO hysteresis range
Delay
Fault response
IOVP threshold
IOVP threshold range
Set point accuracy
IOVP hysteresis
IOVP hysteresis range
Delay
Fault response
PG threshold
PG hysteresis
PG delay
PG delay range
UVP threshold
UVP threshold range
UVP hysteresis
OVP threshold
OVP threshold range
UVP/OVP response time
UVP/OVP
response time range
Fault response
Min
Default configuration:
Monitoring enabled,
Precise timing enabled
Typ
Max
Unit
mW
180
22
100
μF
μF
See Note 10
300
7 500
μF
See Note 10
5
30
mΩ
VO = 0.6 V
55
VO = 1.0 V
65
VO = 3.3 V
110
VO = 5.0 V
190
VO = 0.6 V
230
VO = 1.0 V
210
VO = 3.3 V
200
VO =5.0 V
200
μs
320
200-640
±5
PMBus configurable
External clock source
mV
5
150
-13
95
13
3.85
3.85-14
PMBus configurable
-150
150
0.35
0-10.15
PMBus configurable
2.5
See Note 3
Automatic restart, 70 ms
16
4.2-16
PMBus configurable
-150
PMBus configurable
150
1
0-11.8
2.5
See Note 3
PMBus configurable
PMBus configurable
PMBus configurable
PMBus configurable
See Note 3
Automatic restart, 70 ms
90
5
10
0-500
85
0-100
5
115
100-115
25
5-60
kHz
kHz
%
%
ns
%
V
V
mV
V
V
μs
V
V
mV
V
V
μs
% VO
% VO
ms
s
% VO
% VO
% VO
% VO
% VO
μs
μs
Automatic restart, 70 ms
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MDC_OKDx-T/12-W12-C.A02 Page 4 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Characteristics
Over Current
Protection,
OCP
Over Temperature
Protection,
OTP at P1
See Note 9
VIL
VIH
IIL
VOL
VOH
IOL
IOH
tset
thold
tfree
Cp
Conditions
OCP threshold
OCP threshold range
Protection delay,
Protection delay range
Fault response
OTP threshold
OTP threshold range
OTP hysteresis
OTP hysteresis range
Fault response
Logic input low threshold
Logic input high threshold
Logic input low sink current
Logic output low
Logic output high
Logic output low sink current
Logic output high source current
Setup time, SMBus
Hold time, SMBus
Bus free time, SMBus
Internal capacitance on logic pins
Boot-up time
PMBus configurable
See Note 4
PMBus configurable
See Note 3
PMBus configurable
PMBus configurable
See Note 3
SYNC, SA0, SA1, SCL, SDA,
GCB, CTRL, VSET
Output Voltage
Delay Time
See Note 6
Delay accuracy
turn-on
Output Voltage
Ramp Time
See Note 14
Delay accuracy
turn-off
Ramp duration
Ramp duration range
Ramp time accuracy
VTRK Input Bias Current
VTRK Tracking Ramp Accuracy (VO - VVTRK)
VTRK Regulation Accuracy (VO - VVTRK)
READ_IOUT vs IO
Max
Tsw
°C
°C
°C
°C
0.6
0.4
SYNC, SCL, SDA, SALERT,
GCB, PG
2.25
See Note 1
See Note 1
See Note 1
300
250
2
4
2
10
PMBus configurable
Default configuration:
CTRL controlled
Precise timing enabled
PMBus controlled
Precise timing disabled
VVTRK = 5.5 V
100% Tracking, see Note 8
100% Tracking
IO =0-12 A, TP1 = 0 to +95°C
VI = 12 V
IO =0-12 A, TP1 = 0 to +95°C
VI = 4.5-14 V
V
V
mA
V
V
mA
mA
ns
ns
ms
pF
35
10
2-500000
ms
±0.25
ms
-0.25/+4
ms
-0.25/+4
ms
ms
10
0-200
100
PMBus configurable
Unit
A
A
Tsw
0.8
CTRL
READ_VIN vs VI
READ_VOUT vs VO
READ_IOUT vs IO
Typ
18
0-18
5
1-32
Automatic restart, 70 ms
120
-40…+120
15
0-160
Automatic restart, 240 ms
2
See Note 11
Delay duration
Delay duration range
Monitoring accuracy
Min
110
-100
-1
ms
µs
200
100
1
µA
mV
%
3
1
%
%
±1.6
A
±2.7
A
Note 1: See section I2C/SMBus Setup and Hold Times – Definitions.
Note 2: Monitorable over PMBus Interface.
Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart. See Operating Information for
other fault response options.
Note 4: Tsw is the switching period.
Note 5: Within +/-3% of VO
Note 6: See section Soft-start Power Up.
Note 8: Tracking functionality is designed to follow a VTRK signal with slewrate < 2.4V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth.
Note 9: See section Over Temperature Protection (OTP).
Note 10: See section External Capacitors.
Note 11: See section Start-Up Procedure.
Note 12: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.
Note 13: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.
Note 14: Time for reaching 100% of nominal Vout.
Note 15: For Vout < 1.0V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus.
Note 17: Without minimum load the monitoring function will cause an output voltage of ~0.6 V when the output is disabled. This does not apply if Low Power mode is used.
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MDC_OKDx-T/12-W12-C.A02 Page 5 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Typical Characteristics
Efficiency and Power Dissipation
Efficiency vs. Output Current, VI=5 V
Power Dissipation vs. Output Current, VI=5 V
[%]
100
[W]
5
95
4
90
3
0.6 V
85
0.6 V
2
1.0 V
80
3.3 V
75
1.0 V
1
3.3 V
0
0
2
4
6
8
10
12 [A]
0
2
4
6
8
10
12 [A]
Efficiency vs. load current and output voltage:
TP1 = +25°C. VI=5 V, fsw=320 kHz, CO=470 µF/10 mΩ.
Dissipated power vs. load current and output voltage:
TP1 = +25°C. VI=5 V, fsw=320 kHz, CO=470 µF/10 mΩ.
Efficiency vs. Output Current, VI=12 V
Power Dissipation vs. Output Current, VI=12 V
[%]
100
[W]
5
4
95
3
90
0,6 V
1,0 V
3,3 V
5,0 V
85
80
75
0,6 V
2
1,0 V
3,3 V
1
5,0 V
0
0
2
4
6
8
10
12 [A]
0
2
4
6
8
10
12 [A]
Efficiency vs. load current and output voltage at
TP1 = +25°C. VI=12 V, fsw=320 kHz, CO=470 µF/10 mΩ.
Dissipated power vs. load current and output voltage:
TP1 = +25°C. VI=12 V, fsw=320 kHz, CO=470 µF/10 mΩ.
Efficiency vs. Output Current and
Switch Frequency
Power Dissipation vs. Output Current and
Switch Frequency
[%]
95
[W]
5
90
200
kHz
4
200
kHz
85
320
kHz
3
320
kHz
80
480
kHz
2
480
kHz
75
640
kHz
1
640
kHz
70
0
0
2
4
6
8
10
Efficiency vs. load current and switch frequency at
TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 mΩ
Default configuration except changed frequency.
12 [A]
0
2
4
6
8
10
12 [A]
Dissipated power vs. load current and switch frequency at
TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 mΩ
Default configuration except changed frequency.
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MDC_OKDx-T/12-W12-C.A02 Page 6 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Typical Characteristics
Load Transient
Load Transient vs. External Capacitance, VO=1.0 V
[mV]
200
Load Transient vs. External Capacitance, VO=3.3 V
[mV]
200
Default
PID/NLR
150
Opt. PID, No
NLR
100
Default PID,
Opt. NLR
50
Opt.
PID/NLR
Default
PID/NLR
150
Opt. PID, No
NLR
100
Default PID,
Opt. NLR
50
Opt.
PID/NLR
0
0
0
1
2
3
4
0
5 [mF]
1
2
3
4
5 [mF]
Load transient peak voltage deviation vs. external capacitance.
Step-change (3-9-3 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25°C. VI=12 V, VO=1.0 V, fsw=320 kHz, di/dt=2 A/µs
Load transient peak voltage deviation vs. external capacitance.
Step-change (3-9-3 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25°C. VI=12 V, VO=3.3 V, fsw=320 kHz, di/dt=2 A/µs
Load transient vs. Switch Frequency
Output Load Transient Response, Default PID/NLR
[mV]
Default
PID/NLR
180
Opt. PID,
No NLR
150
120
Default
PID, Opt.
NLR
Opt.
PID/NLR
90
60
30
200
300
400
500
600
Load transient peak voltage deviation vs. frequency.
Step-change (3-9-3 A).
TP1 = +25°C. VI=12 V, VO=3.3 V, CO=470 µF/10 mΩ
[kHz]
Output voltage response to load current
step-change (3-9-3 A) at:
TP1 = +25°C, VI = 12 V, VO =3.3 V
di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10
mΩ
Top trace: output voltage (200
mV/div.).
Bottom trace: load current (5
A/div.).
Time scale: (0.1 ms/div.).
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MDC_OKDx-T/12-W12-C.A02 Page 7 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Typical Characteristics
Output Current Characteristic
Output Current Derating, VO=0.6 V
Output Current Derating, VO=1.0 V
[A]
14
[A]
14
12
3.0 m/s
10
2.0 m/s
8
1.0 m/s
6
0.5 m/s
4
Nat. Conv.
2
12
3.0 m/s
10
2.0 m/s
8
1.0 m/s
6
0.5 m/s
4
Nat. Conv.
2
0
0
80
90
100
110
120 [°C]
80
90
100
110
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO=0.6 V, VI = 12 V. See Thermal Consideration section.
Available load current vs. ambient air temperature and airflow at
VO=1.0 V, VI = 12 V. See Thermal Consideration section.
Output Current Derating, VO=3.3 V
Output Current Derating, VO=5.0 V
[A]
14
[A]
14
12
3.0 m/s
10
2.0 m/s
8
12
1.0 m/s
6
0.5 m/s
4
2.0 m/s
8
1.0 m/s
6
3.0 m/s
10
0.5 m/s
4
Nat. Conv.
Nat. Conv.
2
2
0
0
80
90
100
110
80
120 [°C]
90
100
110
120 [°C]
Available load current vs. ambient air temperature and airflow at
VO=5.0 V, VI = 12 V. See Thermal Consideration section.
Available load current vs. ambient air temperature and airflow at
VO=3.3 V, VI = 12 V. See Thermal Consideration section.
Current Limit Characteristics, VO=1.0 V
Current Limit Characteristics, VO=3.3 V
[V]
[V]
4
1.2
1.0
3
0.8
5V
0.6
12 V
14 V
0.4
5V
2
12 V
14 V
1
0.2
0
0.0
12
14
16
18
Output voltage vs. load current at TP1 = +25°C. VO=1.0 V.
20 [A]
12
14
16
18
20 [A]
Output voltage vs. load current at TP1 = +25°C. VO=3.3 V.
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MDC_OKDx-T/12-W12-C.A02 Page 8 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Typical Characteristics
Output Voltage
Output Ripple & Noise, VO=1.0 V
Output Ripple & Noise, VO=3.3 V
Output voltage ripple at:
Trace: output voltage (20 mV/div.).
TP1 = +25°C, VI = 12 V, CO=470 µF/10 Time scale: (2 µs/div.).
mΩ
IO = 12 A
Output voltage ripple at:
Trace: output voltage (20 mV/div.).
TP1 = +25°C, VI = 12 V, CO=470 µF/10 Time scale: (2 µs/div.).
mΩ
IO = 12 A
Output Ripple vs. Input Voltage
Output Ripple vs. Frequency
[mVpk-pk]
90
[mVpk-pk]
160
80
140
70
120
60
0.6 V
50
1.0 V
40
3.3 V
30
5.0 V
20
0.6 V
100
1.0 V
80
3.3 V
60
5.0 V
40
20
10
0
5
7
9
11
0
[V]
13
200
250
300
350
400
450
500
550
600 [kHz]
Output voltage ripple Vpk-pk at: TP1 = +25°C, CO=470 µF/10 mΩ,
IO =12 A.
Output voltage ripple Vpk-pk at: TP1 = +25°C, VI = 12 V, CO=470 µF/10 mΩ,
IO = 12 A. Default configuration except changed frequency.
Output Ripple vs. External Capacitance
Load regulation, VO=3.3 V
[mVpk-pk]
40
[V]
3.330
35
3.320
30
0.6 V
25
1.0 V
20
3,3 V
15
5V
10
4.5 V
3.310
5V
3.300
12 V
3.290
14 V
3.280
5
3.270
0
0
1
2
3
4
[mF]
Output voltage ripple Vpk-pk at: TP1 = +25°C, VI = 12 V. IO = 12 A. Parallel coupling
of capacitors with 470 µF/10 mΩ,
0
2
4
6
8
10
12 [A]
Load regulation at Vo=3.3 V at: TP1 = +25°C, CO=470 µF/10 mΩ
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MDC_OKDx-T/12-W12-C.A02 Page 9 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Typical Characteristics
Start-up and shut-down
Start-up by input source
Start-up enabled by connecting VI at:
TP1 = +25°C, VI = 12 V, VO = 3.3 V
CO = 470 µF/10 mΩ, IO = 12 A
Shut-down by input source
Top trace: Input voltage (5 V/div.).
Bottom trace: Output voltage (2 V/div.).
Time scale: (20 ms/div.).
Start-up by CTRL signal
Start-up by enabling CTRL signal at:
TP1 = +25°C, VI = 12 V, VO = 3.3 V
CO = 470 µF/10 mΩ, IO = 12 A
Shut-down enabled by disconnecting VI Top trace: Input voltage (5 V/div).
at:
Bottom trace: Output voltage (2 V/div.).
TP1 = +25°C, VI = 12 V, VO = 3.3 V
Time scale: (2 ms/div.).
CO = 470 µF/10 mΩ, IO = 12 A
Shut-down by CTRL signal
Top trace: output voltage (2 V/div.).
Bottom trace: CTRL signal (2 V/div.).
Time scale: (20 ms/div.).
Shut-down enabled by disconnecting VI Top trace: output voltage (2 V/div).
at:
Bottom trace: CTRL signal (2 V/div.).
TP1 = +25°C, VI = 12 V, VO = 3.3 V
Time scale: (2 ms/div.).
CO = 470 µF/10 mΩ, IO = 12 A
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MDC_OKDx-T/12-W12-C.A02 Page 10 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
EMC Specification
Conducted EMI measured according to test set-up and
standard MIL std 0141 - 58000.
The fundamental switching frequency is 320 kHz at VI = 12.0
V, max IO.
Output Ripple and Noise
Output ripple and noise is measured according to figure below.
A 50 mm conductor works as a small inductor forming together
with the two capacitances a damped filter.
Conducted EMI Input terminal value (typical for default
configuration)
+S
−S
50 mm conductor
Tantalum
Capacitor
Output
10 µF
Capacitor
470 µF//10 mΩ
GND
Ceramic
Capacitor
0.1 µF
Load
Vout
50 mm conductor
BNC-contact to
oscilloscope
Output ripple and noise test set-up.
Operating information
EMI without filter
Test set-up
Layout Recommendations
The radiated EMI performance of the product will depend on
the PWB layout and ground layer design. It is also important to
consider the stand-off of the product. If a ground layer is used,
it should be connected to the output of the product and the
equipment ground or chassis.
A ground layer will increase the stray capacitance in the PWB
and improve the high frequency EMC performance.
Power Management Overview
This product is equipped with a PMBus interface. The product
incorporates a wide range of readable and configurable power
management features that are simple to implement
with a minimum of external components. Additionally, the
product includes protection features that continuously
safeguard the load from damage due to unexpected system
faults. A fault is also shown as an alert on the SALERT pin.
The following product parameters can continuously be
monitored by a host: Input voltage, output voltage/current,
and internal temperature. If the monitoring is not needed it can
be disabled and the product enters a low power mode reducing
the power consumption. The protection features are not
affected.
The product is delivered with a default configuration suitable
for a wide range operation in terms of input voltage, output
voltage, and load. The configuration is stored in an internal
Non-Volatile Memory (NVM). All power management functions
can be reconfigured using the PMBus interface. Please contact
your local Murata Power Solutions representative for design
support of custom configurations or appropriate SW tools for
design and down-load of your own configurations.
Input Voltage
The input voltage range, 4.5 - 14 V, makes the product
easy to use in intermediate bus applications when powered
by a non-regulated bus converter or a regulated bus converter.
See Ordering Information for input voltage range.
Input Under Voltage Lockout, UVLO
The product monitors the input voltage and will turn-on and
turn-off at configured levels. The default turn-on input voltage
level setting is 4.20 V, whereas the corresponding turn-off input
voltage level is 3.85 V. Hence, the default hysteresis between
turn-on and turn-off input voltage is 0.35 V. Once an input turn-
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MDC_OKDx-T/12-W12-C.A02 Page 11 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
off condition occurs, the device can respond in a number of
ways as follows:
Eq. 1. I inputRMS = I load D (1 − D ) ,
1. Continue operating without interruption. The unit will
continue to operate as long as the input voltage can be
supported. If the input voltage continues to fall, there will
come a point where the unit will cease to operate.
where I load is the output load current and D is the duty cycle.
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device will remain in
shutdown until instructed to restart.
3. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
The default response from a turn-off is an immediate shutdown
of the device. The device will continuously check for the
presence of the fault condition. If the fault condition is no
longer present, the product will be re-enabled. The turn-on and
turn-off levels and response can be reconfigured using the
PMBus interface.
Remote Control
Vext
CTRL
GND
The product is equipped with a
remote control function, i.e., the
CTRL pin. The remote control
can be connected to either the
primary negative input
connection (GND) or an external
voltage (Vext), which is a 3 - 5 V
positive supply voltage in
accordance to the SMBus
Specification version 2.0.
The CTRL function allows the product to be turned on/off by an
external device like a semiconductor or mechanical switch. By
default the product will turn on when the CTRL pin is left open
and turn off when the CTRL pin is applied to GND. The CTRL
pin has an internal pull-up resistor. When the CTRL pin is left
open, the voltage generated on the CTRL pin is max 5.5 V.
If the device is to be synchronized to an external clock source,
the clock frequency must be stable prior to asserting the CTRL
pin.
The product can also be configured using the PMBus interface
to be “Always on”, or turn on/off can be performed with PMBus
commands.
Input and Output Impedance
The impedance of both the input source and the load will
interact with the impedance of the product. It is important that
the input source has low characteristic impedance. The
performance in some applications can be enhanced by
addition of external capacitance as described under External
Decoupling Capacitors. If the input voltage source contains
significant inductance, the addition a capacitor with low ESR at
the input of the product will ensure stable operation.
External Capacitors
Input capacitors:
The input ripple RMS current in a buck converter is equal to
The maximum load ripple current becomes I load 2 . The ripple
current is divided into three parts, i.e., currents in the input
source, external input capacitor, and internal input capacitor.
How the current is divided depends on the impedance of the
input source, ESR and capacitance values in the capacitors. A
minimum capacitance of 300 µF with low ESR is
recommended. The ripple current rating of the capacitors must
follow Eq. 1. For high-performance/transient applications or
wherever the input source performance is degraded, additional
low ESR ceramic type capacitors at the input is recommended.
The additional input low ESR capacitance above the minimum
level insures an optimized performance.
Output capacitors:
When powering loads with significant dynamic current
requirements, the voltage regulation at the point of load can be
improved by addition of decoupling capacitors at the load.
The most effective technique is to locate low ESR ceramic and
electrolytic capacitors as close to the load as possible, using
several capacitors in parallel to lower the effective ESR. The
ceramic capacitors will handle high-frequency dynamic load
changes while the electrolytic capacitors are used to handle
low frequency dynamic load changes. Ceramic capacitors will
also reduce high frequency noise at the load.
It is equally important to use low resistance and low inductance
PWB layouts and cabling.
External decoupling capacitors are a part of the control loop of
the product and may affect the stability margins.
Stable operation is guaranteed for the following total
capacitance CO in the output decoupling capacitor bank where
Eq. 2.
CO = [Cmin , C max ] = [300, 7500] µF.
The decoupling capacitor bank should consist of capacitors
which have a capacitance value larger than C ≥ C min and has
an ESR range of
Eq. 3.
ESR = [ESRmin , ESR max ] = [5, 30] mΩ
The control loop stability margins are limited by the minimum
time constant τ min of the capacitors. Hence, the time constant
of the capacitors should follow Eq. 4.
Eq. 4. τ ≥ τ min = Cmin ESR min = 1.5µ s
This relation can be used if your preferred capacitors have
parameters outside the above stated ranges in Eq. 2 and Eq.3.
• If the capacitors capacitance value is C < C min one must
use at least N capacitors where
C
C
N ≥ min and ESR ≥ ESR min min .
C
C
• If the ESR value is ESR > ESRmax one must use at least N
capacitors of that type where
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MDC_OKDx-T/12-W12-C.A02 Page 12 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
ESR
C min
.
N≥
and C ≥
ESR
N
max
• If the ESR value is ESR < ESRmin the capacitance value
should be
ESRmin
.
C ≥ C min
ESR
For a total capacitance outside the above stated range or
capacitors that do not follow the stated above requirements
above a re-design of the control loop parameters will be
necessary for robust dynamic operation and stability.
the remote sense is not needed +S should be connected to
VOUT and −S should be connected to GND.
Control Loop Compensation
The product is configured with a robust control loop
compensation which allows for a wide range operation of input
and output voltages and capacitive loads as defined in the
section External Decoupling Capacitors. For an application
with a specific input voltage, output voltage, and capacitive
load, the control loop can be optimized for a robust and stable
operation and with an improved load transient response. This
optimization will minimize the amount of required output
decoupling capacitors for a given load transient requirement
yielding an optimized cost and minimized board space. The
control loop parameters can be reconfigured using the PMBus
interface.
RSET also sets the maximum output voltage, see section
“Output Voltage Range Limitation”. The resistor is sensed only
during product start-up. Changing the resistor value during
normal operation will not change the output voltage. The input
voltage must be at least 1 V larger than the output voltage in
order to deliver the correct output voltage. See Ordering
Information for output voltage range.
Load Transient Response Optimization
The product incorporates a Non-Linear transient Response,
NLR, loop that decreases the response time and the output
voltage deviation during a load transient. The NLR results in a
higher equivalent loop bandwidth than is possible using a
traditional linear control loop. The product is pre-configured
with appropriate NLR settings for robust and stable operation
for a wide range of input voltage and a capacitive load range
as defined in the section External Decoupling Capacitors. For
an application with a specific input voltage, output voltage, and
capacitive load, the NLR configuration can be optimized for a
robust and stable operation and with an improved load
transient response. This will also reduce the amount of output
decoupling capacitors and yield a reduced cost. However, the
NLR slightly reduces the efficiency. In order to obtain maximal
energy efficiency the load transient requirement has to be met
by the standard control loop compensation and the decoupling
capacitors. The NLR settings can be reconfigured using the
PMBus interface.
Remote Sense
The product has remote sense that can be used to
compensate for voltage drops between the output and the
point of load. The sense traces should be located close to the
PWB ground layer to reduce noise susceptibility. Due to
derating of internal output capacitance the voltage drop should
be kept below VDROPMAX = (5.5−VOUT) / 2 . A large voltage
drop will impact the electrical performance of the regulator. If
Output Voltage Adjust using Pin-strap Resistor
Using an external Pin-strap
resistor, RSET, the output
voltage can be set in the
VSET
range 0.6 V to 3.3 V at 28
RSET
different levels shown in the
PREF
table below. The resistor
should be applied between
the VSET pin and the PREF
pin.
The following table shows recommended resistor values for
RSET. Maximum 1% tolerance resistors are required.
VOUT [V]
RSET[kΩ]
VOUT [V]
RSET[kΩ]
0.60
10
1.50
46.4
0.65
11
1.60
51.1
0.70
12.1
1.70
56.2
0.75
13.3
1.80
61.9
0.80
14.7
1.90
68.1
0.85
16.2
2.00
75
0.90
17.8
2.10
82.5
0.95
19.6
2.20
90.9
1.00
21.5
2.30
100
1.05
23.7
2.50
110
1.10
26.1
3.00
121
1.15
28.7
3.30
133
1.20
31.6
4.00
147
1.25
34.8
5.00
162
1.30
38.3
5.50
178
1.40
42.2
The output voltage and the maximum output voltage can be pin
strapped to three fixed values by connecting the VSET pin
according to the table below.
VOUT [V]
0.60
VSET
Shorted to PREF
1.2
Open “high impedance”
2.5
Logic High, GND as reference
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MDC_OKDx-T/12-W12-C.A02 Page 13 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Output Voltage Adjust using PMBus
The output voltage set by pin-strap can be overridden by
configuration file or by using a PMBus command. See
Electrical Specification for adjustment range.
When setting the output voltage by configuration file or by a
PMBus command, the specified output voltage accuracy is
valid only when the set output voltage level falls within the
same bin range as the voltage level defined by the pin-strap
resistor RSET. The applicable bin ranges are defined in the
table below. Valid accuracy for voltage levels outside the
applicable bin range is two times the specified.
Example:
Nominal Vout is set to 1.10V by Rset=26.1kohm. 1.10V falls
within the bin range 0.988-1.383V, thus specified accuracy is
valid when adjusting Vout within 0.988-1.383V.
VOUT bin ranges [V]
0 – 0.988
0.988 – 1.383
1.383 – 1.975
1.975 – 2.398
2.398 – 2.963
2.963 – 3.753
3.753 – 4.938
4.938 –
Output Voltage Range Limitation
The output voltage range that is possible to set by
configuration or by the PMBus interface is limited by the pinstrap resistor RSET. The maximum output voltage is set to
110% of the nominal output value defined by RSET,
VOUT _ MAX = 1.1× VOUT _ RSET . This protects the load from an over
voltage due to an accidental wrong PMBus command.
Over Voltage Protection (OVP)
The product includes over voltage limiting circuitry for
protection of the load. The default OVP limit is 15% above the
nominal output voltage. If the output voltage exceeds the OVP
limit, the product can respond in different ways:
1. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
2. Turn off the high-side MOSFET and turn on the low-side
MOSFET. The low-side MOSFET remains ON until the
device attempts a restart, i.e. the output voltage is pulled to
ground level (crowbar function).
The default response from an overvoltage fault is to
immediately shut down as in 2. The device will continuously
check for the presence of the fault condition, and when the
fault condition no longer exists the device will be re-enabled.
For continuous OVP when operating from an external clock for
synchronization, the only allowed response is an immediate
shutdown. The OVP limit and fault response can be
reconfigured using the PMBus interface.
Under Voltage Protection (UVP)
The product includes output under voltage limiting circuitry for
protection of the load. The default UVP limit is 15% below the
nominal output voltage. The UVP limit can be reconfigured
using the PMBus interface.
Power Good
The product provides a Power Good (PG) flag in the Status
Word register that indicates the output voltage is within a
specified tolerance of its target level and no fault condition
exists. If specified in section Connections, the product also
provides a PG signal output. The PG pin is active high and by
default open-drain but may also be configured as push-pull via
the PMBus interface.
By default, the PG signal will be asserted when the output
reaches above 90% of the nominal voltage, and de-asserted
when the output falls below 85% of the nominal voltage. These
limits may be changed via the PMBus interface. A PG delay
period is defined as the time from when all conditions within
the product for asserting PG are met to when the PG signal is
actually asserted. The default PG delay is set to 10 ms. This
value can be reconfigured using the PMBus interface
Switching Frequency
The fundamental switching frequency is 320 kHz, which yields
optimal power efficiency. The switching frequency can be set
to any value between 200 kHz and 640 kHz using the PMBus
interface. The switching frequency will change the
efficiency/power dissipation, load transient response and
output ripple. For optimal control loop performance the control
loop must be re-designed when changing the switching
frequency.
Synchronization
Synchronization is a feature that allows multiple products to be
synchronized to a common frequency. Synchronized products
powered from the same bus eliminate beat frequencies
reflected back to the input supply, and also reduces EMI
filtering requirements. Eliminating the slow beat frequencies
(usually 15°C below
the over temperature threshold. The specified OTP level and
hysteresis are valid for worst case operation regarding cooling
conditions, input voltage and output voltage. This means the
OTP level and hysteresis in many cases will be lower. The
OTP level, hysteresis, and fault response of the product can be
reconfigured using the PMBus interface. The fault response
can be configured as follows:
1. Initiate a shutdown and attempt to restart an infinite number
of times with a preset delay period between attempts
(default configuration).
2. Initiate a shutdown and attempt to restart a preset number
of times with a preset delay period between attempts.
3. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
Optimization examples
This product is designed with a digital control circuit. The
control circuit uses a configuration file which determines the
functionality and performance of the product. It is possible to
change the configuration file to optimize certain performance
characteristics. In the table below is a schematic view on how
to change different configuration parameters in order to
achieve an optimization towards a wanted performance.
↑
→
↓
Increase
No change
Decrease
Config.
parameters
Switching
frequency
NLR
threshold
Diode
emulation
(DCM)
Min.
pulse
Optimized
performence
Maximize
efficiency
Control
loop
bandwidth
↓
→
↑
Enable
Disable
Minimize
ripple ampl.
↑
→
↑
Enable
or
disable
Enable
or
disable
↑
↑
↓
Disable
Disable
↓
↑
→
Enable
Enable
Improve
load
transient
response
Minimize
idle power
loss
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MDC_OKDx-T/12-W12-C.A02 Page 17 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Pli
Pli
PCTRL
Vtr1
Input idling
power
(no load)
Input idling
power
(no load)
Input
standby
power
Load
transient
peak
voltage
deviation
Load step
25-75-25%
of max IO
ttr1
Load
transient
recovery
time
Load step
25-75-25%
of max IO
Default
configuration:
Continues
Conduction
Mode, CCM
VO = 0.6 V
0.36
VO = 1.0 V
0.35
VO = 3.3 V
0.54
VO = 5.0 V
0.97
DCM,
Discontinues
Conduction
Mode
(diode
emulation)
DCM with
Adaptive
Frequency
and Minimum
Pulse
Enabled
DCM with
Adaptive
Frequency
and Minimum
Pulse
Disabled
VO = 0.6 V
0.30
VO = 1.0 V
0.37
VO = 3.3 V
0.41
VO = 5.0 V
Turned off
with
CTRL-pin
Default
configuration
di/dt = 2 A/μs
CO=470 μF
Optimized
PID and NLR
configuration
di/dt = 2 A/μs
CO=470 μF
Default
configuration
di/dt = 2 A/μs
CO=470 μF
Optimized
PID and NLR
configuration
di/dt = 2 A/μs
CO=470 μF
Efficiency vs. Output Current and Switching frequency
W
[%]
95
90
200
kHz
85
320
kHz
0.45
80
480
kHz
VO = 0.6 V
0.29
VO = 1.0 V
0.35
75
640
kHz
VO = 3.3 V
0.37
VO = 5.0 V
0.42
VO = 0.6 V
0.25
VO = 1.0 V
0.20
VO = 3.3 V
0.20
VO = 5.0 V
0.20
Default
configuration:
Monitoring
enabled,
Precise
timing
enabled
Monitoring
enabled,
Precise
timing
disabled
Low power
mode:
Monitoring
disabled,
Precise
timing
disabled
VO = 0.6 V
W
W
70
0
W
2
4
6
8
10
12 [A]
Efficiency vs. load current and switching frequency at
TP1 = +25°C. VI=12 V, VO=3.3V, CO=470 µF/10 mΩ
Default configuration except changed frequency
Power Dissipation vs. Output Current and Switching frequency
[W]
5
180
120
mW
mW
4
200
kHz
3
320
kHz
2
480
kHz
1
640
kHz
0
85
mW
65
VO = 3.3 V
110
VO = 5.0 V
190
VO = 0.6 V
40
VO = 1.0 V
35
VO = 3.3 V
55
VO = 5.0 V
105
VO = 0.6 V
230
VO = 1.0 V
210
VO = 3.3 V
200
VO = 5.0 V
200
VO = 0.6 V
45
VO = 1.0 V
40
VO = 3.3 V
40
VO = 5.0 V
35
2
4
6
8
10
12 [A]
Dissipated power vs. load current and switching frequency at
TP1 = +25°C. VI=12 V, VO=3.3V, CO=470 µF/10 mΩ
Default configuration except changed frequency
55
VO = 1.0 V
0
mV
Output Ripple vs. Switching frequency
[mVpk-pk]
160
140
mV
120
0.6 V
100
1.0 V
80
3.3 V
60
5.0 V
40
20
us
0
200
250
300
350
400
450
500
550
600 [kHz]
Output voltage ripple Vpk-pk at: TP1 = +25°C, VI = 12 V, CO=470 µF/10 mΩ,
IO = 12 A resistive load. Default configuration except changed frequency.
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MDC_OKDx-T/12-W12-C.A02 Page 18 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Load transient vs. Switching frequency
Output Load Transient Response, Default PID/NLR
[mV]
200
160
Default
PID/NLR
120
Opt. PID, No
NLR
80
Default PID,
Opt. NLR
40
Opt.
PID/NLR
0
200
300
400
500
600 [kHz]
Load transient peak voltage deviation vs. frequency.
Step-change (3-9-3 A).
TP1 = +25°C. VI=12 V, VO=3.3 V, CO=470 µF/10 mΩ
Output voltage response to load current step- Top trace: output voltage (200 mV/div.).
change (3-9-3 A) at:
Bottom trace: load current (5 A/div.).
TP1 = +25°C, VI = 12 V, VO =3.3 V
Time scale: (0.1 ms/div.).
di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 mΩ
Default PID Control Loop and NLR
Load Transient vs. Decoupling Capacitance, VO=1.0 V
Output Load Transient Response, Optimized PID, no NLR
[mV]
200
Default
PID/NLR
150
Opt. PID, No
NLR
100
Default PID,
Opt. NLR
50
Opt.
PID/NLR
0
0
1
2
3
4
5 [mF]
Load transient peak voltage deviation vs. decoupling capacitance.
Step-change (3-9-3 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25°C. VI=12 V, VO=1.0V, fsw=320 kHz, di/dt=2 A/µs
Output voltage response to load current step- Top trace: output voltage (200 mV/div.).
change (3-9-3 A) at:
Bottom trace: load current (5 A/div.).
TP1 = +25°C, VI = 12 V, VO =3.3 V
Time scale: (0.1 ms/div.).
di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 mΩ
Optimized PID Control Loop and no NLR
Load Transient vs. Decoupling Capacitance, VO=3.3 V
Output Load Transient Response, Optimized NLR
[mV]
200
Default
PID/NLR
150
Opt. PID, No
NLR
100
Default PID,
Opt. NLR
50
Opt.
PID/NLR
0
0
1
2
3
4
5 [mF]
Load transient peak voltage deviation vs. decoupling capacitance.
Step-change (3-9-3 A). Parallel coupling of capacitors with 470 µF/10 mΩ,
TP1 = +25°C. VI=12 V, VO=3.3 V, fsw=320 kHz, di/dt=2 A/µs
Output voltage response to load current step- Top trace: output voltage (200 mV/div.).
change (3-9-3 A) at:
Bottom trace: load current (5 A/div.).
TP1 = +25°C, VI = 12 V, VO =3.3 V
Time scale: (0.1 ms/div.).
di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 mΩ
Default PID Control Loop and optimized NLR
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MDC_OKDx-T/12-W12-C.A02 Page 19 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Thermal Consideration
SIP version
General
The product is designed to operate in different thermal
environments and sufficient cooling must be provided to
ensure reliable operation.
Cooling is achieved mainly by conduction, from the pins to the
host board, and convection, which is dependant on the airflow
across the product. Increased airflow enhances the cooling of
the product.
The Output Current Derating graph found in the Output section
for each model provides the available output current vs.
ambient air temperature and air velocity at specified VI.
The product is tested on a 254 x 254 mm, 35 µm (1 oz), test
board mounted vertically in a wind tunnel with a cross-section
of 608 x 203 mm. The test board has 8 layers.
Proper cooling of the product can be verified by measuring the
temperature at positions P1 and P2. The temperature at these
positions should not exceed the max values provided in the
table below.
Note that the max value is the absolute maximum rating
(non destruction) and that the electrical Output data is
guaranteed up to TP1 +95°C.
Top view
AIR
FLOW
Bottom view
P1
P2
Temperature positions and air flow direction.
Definition of reference temperature TP1
The reference temperature is used to monitor the temperature
limits of the product. Temperature above maximum TP1,
measured at the reference point P1 is not allowed and may
cause degradation or permanent damage to the product. TP1 is
also used to define the temperature range for normal operating
conditions. TP1 is defined by the design and used to guarantee
safety margins, proper operation and high reliability ot the
product.
Definition of product operating temperature
The product operating temperatures are used to monitor the
temperature of the product, and proper thermal conditions can
be verified by measuring the temperature at positions P1 and
P2. The temperature at these positions (TP1, TP2) should not
exceed the maximum temperatures in the table below. The
number of measurement points may vary with different thermal
design and topology. Temperatures above maximum TP1,
measured at the reference point P1 are not allowed and may
cause permanent damage.
Position
Description
Max Temp.
P1
Reference point, L1,
inductor
120°C
P2
N1, control circuit
120°C
AIR FLOW
Top view
P1
Bottom view
P2
Temperature positions and air flow direction.
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MDC_OKDx-T/12-W12-C.A02 Page 20 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Connections (Horizontal & SMT versions)
Connections (SIP version)
Pin layout, top view (component placement for illustration only).
Pin layout, bottom view (component placement for illustration only).
Pin
Designation
Function
Pin
Designation
Function
1A
VIN
Input Voltage
1A
VIN
Input Voltage
2A
GND
Power Ground
2A
GND
Power Ground
3A
VOUT
3A
VOUT
Output voltage
4A
+S
Positive sense
4B
-S
Negative sense
5A
VSET
Output voltage pin-strap
5B
VTRK
Voltage tracking input
6A
SALERT
PMBus Alert
6B
SDA
PMBus data
7A
SCL
PMBus Clock
7B
SYNC
Synchronization I/O
8A
SA0
PMBus address pin-strap
8B
CTRL
Remote Control
9A
GCB
Group Communication Bus
9B
PREF
Pin-strap Reference
4A
VTRK or PG *
Output Voltage
Voltage Tracking input or
Power Good
4B
PREF
Pin-strap reference
5A
+S
Positive sense
5B
−S
Negative sense
6A
SA0
PMBus address pinstrap
6B
GCB
Group Communication Bus
7A
SCL
PMBus Clock
7B
SDA
PMBus Data
8A
VSET
Output voltage pinstrap
8B
SYNC
Synchronization I/O
9A
SALERT
PMBus Alert
9B
CTRL
Remote Control
* For these products the PG pin is internally tied to the VTRK input of
the products’ controller. Typically the VTRK input bias current will be
equivalent to a 50 kohm pull-down resistor. This should be considered
when choosing pull-up resistor for the PG signal.
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MDC_OKDx-T/12-W12-C.A02 Page 21 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Unused input pins
Unused SDA, SCL and GCB pins should still have pull-up
resistors as specified.
Unused VTRK or SYNC pins should be left unconnected or
connected to the PREF pin.
Unused CTRL pin can be left open due to internal pull-up.
VSET and SA0/SA1 pins must have pinstrap resistors as
specified.
PWB layout considerations
The pinstrap resistors, RSET, and RSA0/RSA1 should be placed
as close to the product as possible to minimize loops that may
pick up noise.
Avoid current carrying planes under the pinstrap resistors and
the PMBus signals.
The capacitor CI (or capacitors implementing it) should be
placed as close to the input pins as possible.
Capacitor CO (or capacitors implementing it) should be placed
close to the load.
Care should be taken in the routing of the connections from
the sensed output voltage to the S+ and S– terminals. These
sensing connections should be routed as a differential pair,
preferably between ground planes which are not carrying high
currents. The routing should avoid areas of high electric or
magnetic fields.
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MDC_OKDx-T/12-W12-C.A02 Page 22 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Typical Application Circuit (SIP version)
OKDX-T/12-W12
Standalone operation with PMBus communication. Top view of product footprint.
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MDC_OKDx-T/12-W12-C.A02 Page 23 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
PMBus interface
This product provides a PMBus digital interface that enables
the user to configure many aspects of the device operation as
well as to monitor the input and output voltages, output current
and device temperature. The product can be used with any
standard two-wire I2C or SMBus host device. In addition, the
product is compatible with PMBus version 1.1 and includes an
SALERT line to help mitigate bandwidth limitations related to
continuous fault monitoring. The product supports 100 kHz
bus clock frequency only. The PMBus signals, SCL, SDA and
SALERT require passive pull-up resistors as stated in the
SMBus Specification. Pull-up resistors are required to
guarantee the rise time as follows:
Eq. 7
τ = RP Cp ≤ 1µ s
where Rp is the pull-up resistor value and Cp is the bus
loading, the maximum allowed bus load is 400 pF. The pull-up
resistor should be tied to an external supply voltage in range
from 2.7 to 5.5 V, which should be present prior to or during
power-up. If the proper power supply is not available, voltage
dividers may be applied. Note that in this case, the resistance
in the equation above corresponds to parallel connection of
the resistors forming the voltage divider.
Monitoring via PMBus
It is possible to monitor a wide variety of parameters through
the PMBus interface. Fault conditions can be monitored using
the SALERT pin, which will be asserted when any number of
pre-configured fault or warning conditions occur. It is also
possible to continuously monitor one or more of the power
conversion parameters including but not limited to the
following:
•
•
•
•
•
•
Snap shot parameter capture
This product offers a special feature that enables the user to
capture parametric data during normal operation or following a
fault. The following parameters are stored:
•
•
•
•
•
•
•
Input voltage
Output voltage
Output current
Internal junction temperature
Switching frequency
Duty cycle
Status registers
The Snapshot feature enables the user to read the parameters
via the PMBus interface during normal operation, although it
should be noted that reading the 22 bytes will occupy the bus
for some time. The Snapshot enables the user to store the
snapshot parameters to Flash memory in response to a
pending fault as well as to read the stored data from Flash
memory after a fault has occurred. Automatic store to Flash
memory following a fault is triggered when any fault threshold
level is exceeded, provided that the specific fault response is
to shut down. Writing to Flash memory is not allowed if the
device is configured to restart following the specific fault
condition. It should also be noted that the device supply
voltage must be maintained during the time the device is
writing data to Flash memory; a process that requires between
700-1400 μs depending on whether the data is set up for a
block write. Undesirable results may be observed if the input
voltage of the product drops below 3.0 V during this process.
Input voltage
Output voltage
Output current
Internal junction temperature
Switching frequency
Duty cycle
In the default configuration monitoring is enabled also when
the output voltage is disabled. This can be changed in order to
reduce standby power consumption.
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MDC_OKDx-T/12-W12-C.A02 Page 24 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
PMBus addressing
The PMBus address should be configured with resistors
connected between the SA0/SA1 pins and the PREF pin, as
shown in the figure below. Recommended resistor values for
hard-wiring PMBus addresses are shown in the table. 1%
tolerance resistors are required.
SA0
SA1
RSA1
0
low
open
high
low
20h
21h
22h
open
23h
24h
25h
high
26h
27h
Reserved
Logic High definitions see Electrical Specification
Index
RSA [kΩ]
Reserved Addresses
Address 4Bh is allocated for production needs and can not be
used.
10
13
34.8
1
11
14
38.3
2
12.1
15
42.2
3
13.3
16
46.4
4
14.7
17
51.1
5
16.2
18
56.2
6
17.8
19
61.9
0
General Call Address / START byte
7
19.6
20
68.1
1
CBUS address
Address reserved for different bus format
Addresses listed in the table below are reserved or assigned
according to the SMBus specification and may not be usable.
Refer to the SMBus specification for further information.
Address
(decimal)
8
21.5
21
75
2
9
23.7
22
82.5
3-7
10
26.1
23
90.9
8
11
28.7
24
100
9-11
12
31.6
The PMBus address follows the equation below:
Eq. 8
SA0
Low = Shorted to PREF
Open = High impedance
High = Logic high, GND as reference,
Schematic of connection of address resistor.
RSA [kΩ]
Alternatively the PMBus address can be defined by
connecting the SA0/SA1 pins according to the table below.
SA1 = open for products with no SA1 pin.
SA1
RSA0
PREF
Index
Optional PMBus Addressing
PMBus Address (decimal) = 25 x (SA1 index) +
(SA0 index)
The user can theoretically configure up to 625 unique PMBus
addresses, however the PMBus address range is inherently
limited to 128. Therefore, the user should use index values 0 4 on the SA1 pin and the full range of index values on the SA0
pin, which will provide 125 device address combinations.
Products with no SA1 pin have an internally defined SA1 index
as follows.
Product
SA1 index
All models
4
Comment
Reserved for future use
SMBus Host
Assigned for Smart Battery
12
SMBus Alert Response Address
40
Reserved for ACCESS.bus host
44-45
55
64-68
72-75
97
Reserved by previous versions of the SMBus
specification
Reserved for ACCESS.bus default address
Reserved by previous versions of the SMBus
specification
Unrestricted addresses
SMBus Device Default Address
120-123
10-bit slave addressing
124-127
Reserved for future use
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MDC_OKDx-T/12-W12-C.A02 Page 25 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
I2C/SMBus – Timing
Setup and hold times timing diagram
The setup time, tset, is the time data, SDA, must be stable
before the rising edge of the clock signal, SCL. The hold time
thold, is the time data, SDA, must be stable after the rising edge
of the clock signal, SCL. If these times are violated incorrect
data may be captured or meta-stability may occur and the bus
communication may fail. When configuring the product, all
standard SMBus protocols must be followed, including clock
stretching. Refer to the SMBus specification, for SMBus
electrical and timing requirements.
This product does not support the BUSY flag in the status
commands to indicate product being too busy for SMBus
response. Instead a bus-free time delay according to this
specification must occur between every SMBus transmission
(between every stop & start condition). In case of storing the
RAM content into the internal non-volatile memory an
additional delay of 20 ms has to be inserted.
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MDC_OKDx-T/12-W12-C.A02 Page 26 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
PMBus Commands
Designation
Cmd
Impl
OT_FAULT_LIMIT
4Fh
Yes
OT_WARN_LIMIT
51h
Yes
UT_WARN_LIMIT
52h
Yes
UT_FAULT_LIMIT
53h
Yes
VIN_OV_FAULT_LIMIT
55h
Yes
VIN_OV_WARN_LIMIT
57h
Yes
VIN_UV_WARN_LIMIT
58h
Yes
Standard PMBus Commands
VIN_UV_FAULT_LIMIT
59h
Yes
Control Commands
Fault Response Commands
The products are PMBus compliant. The following table lists
the implemented PMBus read commands. For more detailed
information see PMBus Power System Management Protocol
Specification; Part I – General Requirements, Transport and
Electrical Interface and PMBus Power System Management
Protocol; Part II – Command Language.
Designation
Cmd
Impl
PAGE
00h
No
VOUT_OV_FAULT_RESPONSE
41h
Yes
OPERATION
01h
Yes
VOUT_UV_FAULT_RESPONSE
45h
Yes
ON_OFF_CONFIG
02h
Yes
OT_FAULT_RESPONSE
50h
Yes
WRITE_PROTECT
10h
No
UT_FAULT_RESPONSE
54h
Yes
VIN_OV_FAULT_RESPONSE
56h
Yes
Output Commands
VOUT_MODE (Read Only)
20h
Yes
VIN_UV_FAULT_RESPONSE
5Ah
Yes
VOUT_COMMAND
21h
Yes
IOUT_OC_FAULT_RESPONSE
47h
No
VOUT_TRIM
22h
Yes
IOUT_UC_FAULT_RESPONSE
4Ch
No
VOUT_CAL_OFFSET
23h
Yes
Time setting Commands
VOUT_MAX
24h
Yes
TON_DELAY
60h
Yes
VOUT_MARGIN_HIGH
25h
Yes
TON_RISE
61h
Yes
VOUT_MARGIN_LOW
26h
Yes
TOFF_DELAY
64h
Yes
VOUT_TRANSITION_RATE
27h
Yes
TOFF_FALL
65h
Yes
VOUT_DROOP
28h
Yes
TON_MAX_FAULT_LIMIT
62h
No
MAX_DUTY
32h
Yes
Status Commands (Read Only)
FREQUENCY_SWITCH
33h
Yes
CLEAR_FAULTS
03h
Yes
VIN_ON
35h
No
STATUS_BYTE
78h
Yes
VIN_OFF
36h
No
STATUS_WORD
79h
Yes
IOUT_CAL_GAIN
38h
Yes
STATUS_VOUT
7Ah
Yes
IOUT_CAL_OFFSET
39h
Yes
STATUS_IOUT
7Bh
Yes
VOUT_SCALE_LOOP
29h
No
STATUS_INPUT
7Ch
Yes
VOUT_SCALE_MONITOR
2Ah
No
STATUS_TEMPERATURE
7Dh
Yes
COEFFICIENTS
30h
No
STATUS_CML
7Eh
Yes
STATUS_MFR_SPECIFIC
80h
Yes
POWER_GOOD_ON
5Eh
Yes
Monitor Commands (Read Only
POWER_GOOD_OFF
5Fh
No
READ_VIN
88h
Yes
VOUT_OV_FAULT_LIMIT
40h
Yes
READ_VOUT
8Bh
Yes
VOUT_OV_WARN_LIMIT
42h
No
READ_IOUT
8Ch
Yes
VOUT_UV_WARN_LIMIT
43h
No
READ_TEMPERATURE_1
8Dh
Yes
VOUT_UV_FAULT_LIMIT
44h
Yes
READ_TEMPERATURE_2
8Eh
No
IOUT_OC_FAULT_LIMIT
46h
Yes
READ_FAN_SPEED_1
90h
No
IOUT_OC_WARN_LIMIT
4Ah
No
READ_DUTY_CYCLE
94h
Yes
IOUT_UC_FAULT_LIMIT
4Bh
Yes
READ_FREQUENCY
95h
Yes
Fault Limit Commands
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MDC_OKDx-T/12-W12-C.A02 Page 27 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Designation
Cmd
Impl
Group Commands
Designation
Cmd
Impl
SNAPSHOT_CONTROL
F3h
Yes
INTERLEAVE
37h
Yes
DEVICE_ID
E4h
Yes
PHASE_CONTROL
F0h
Yes
USER_DATA_00
B0h
Yes
Identification Commands
Group Commands
PMBUS_REVISION
98h
Yes
SEQUENCE
E0h
Yes
MFR_ID
99h
Yes
GCB_CONFIG
D3h
Yes
MFR_MODEL
9Ah
Yes
GCB_GROUP
E2h
Yes
MFR_REVISION
9Bh
Yes
ISHARE_CONFIG
D2h
Yes
MFR_LOCATION
9Ch
Yes
PHASE_CONTROL
F0h
Yes
MFR_DATE
9Dh
Yes
Supervisory Commands
MFR_SERIAL
9Eh
Yes
PRIVATE_PASSWORD
FBh
Yes
PUBLIC_PASSWORD
FCh
Yes
Supervisory Commands
STORE_DEFAULT_ALL
11h
Yes
UNPROTECT
FDh
Yes
RESTORE_DEFAULT_ALL
12h
Yes
SECURITY_LEVEL
FAh
Yes
STORE_USER_ALL
15h
Yes
RESTORE_USER_ALL
16h
Yes
D4h
Yes
IOUT_AVG_OC_FAULT_LIMIT
E7h
Yes
IOUT_AVG_UC_FAULT_LIMIT
E8h
Yes
MFR_IOUT_OC_FAULT_RESPONSE
E5h
Yes
MFR_IOUT_UC_FAULT_RESPONSE
E6h
Yes
OVUV_CONFIG
D8h
Yes
MFR_CONFIG
D0h
Yes
USER_CONFIG
D1h
Yes
MISC_CONFIG
E9h
Yes
TRACK_CONFIG
E1h
Yes
PID_TAPS
D5h
Yes
PID_TAPS_CALC
F2h
Yes
INDUCTOR
D6h
Yes
NLR_CONFIG
D7h
Yes
TEMPCO_CONFIG
DCh
Yes
IOUT_OMEGA_OFFSET
BEh
Yes
DEADTIME
DDh
Yes
DEADTIME_CONFIG
DEh
Yes
DEADTIME_MAX
BFh
Yes
SNAPSHOT
EAh
Yes
Product Specific Commands
Notes:
Cmd is short for Command.
Impl is short for Implemented.
Time Setting Commands
POWER_GOOD_DELAY
Fault limit Commands
Fault Response Commands
Configuration and Control Commands
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MDC_OKDx-T/12-W12-C.A02 Page 28 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Mechanical Information (SIP version)
All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle,
unless explicitly described and dimensioned in this drawing.
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MDC_OKDx-T/12-W12-C.A02 Page 29 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Mechanical Information (Horizontal version)
All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle,
unless explicitly described and dimensioned in this drawing.
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MDC_OKDx-T/12-W12-C.A02 Page 30 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Mechanical Information (SMT version)
All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle,
unless explicitly described and dimensioned in this drawing.
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MDC_OKDx-T/12-W12-C.A02 Page 31 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Soldering Information - Surface Mounting
Lead-free (Pb-free) solder processes
The surface mount product is intended for forced convection or
vapor phase reflow soldering in SnPb or Pb-free processes.
For Pb-free solder processes, a pin temperature (TPIN) in
excess of the solder melting temperature (TL, 217 to 221°C for
SnAgCu solder alloys) for more than 30 seconds and a peak
temperature of 235°C on all solder joints is recommended to
ensure a reliable solder joint.
The reflow profile should be optimised to avoid excessive
heating of the product. It is recommended to have a sufficiently
extended preheat time to ensure an even temperature across
the host PCB and it is also recommended to minimize the time
in reflow.
A no-clean flux is recommended to avoid entrapment of
cleaning fluids in cavities inside the product or between the
product and the host board, since cleaning residues may affect
long time reliability and isolation voltage.
General reflow process specifications
SnPb eutectic
Pb-free
Average ramp-up (TPRODUCT)
3°C/s max
3°C/s max
Typical solder melting (liquidus)
temperature
TL
Minimum reflow time above TL
Minimum pin temperature
TPIN
Peak product temperature
TPRODUCT
183°C
221°C
30 s
30 s
210°C
235°C
225°C
260°C
6°C/s max
Maximum time 25°C to peak
6 minutes
8 minutes
Temperature
Pin
profile
Time in preheat
/ soak zone
Time 25°C to peak
Time in
reflow
For SnPb solder processes, the product is qualified for MSL 1
according to IPC/JEDEC standard J-STD-020C.
Pb-free solder processes
6°C/s max
TL
SnPb solder processes
During reflow TPRODUCT must not exceed 225 °C at any time.
Average ramp-down (TPRODUCT)
TPRODUCT maximum
TPIN minimum
Maximum Product Temperature Requirements
Top of the product PCB near pin 9B is chosen as reference
location for the maximum (peak) allowed product temperature
(TPRODUCT) since this will likely be the warmest part of the
product during the reflow process.
Product
profile
Time
Minimum Pin Temperature Recommendations
Pin number 2A chosen as reference location for the minimum
pin temperature recommendation since this will likely be the
coolest solder joint during the reflow process.
For Pb-free solder processes, the product is qualified for MSL 3
according to IPC/JEDEC standard J-STD-020C.
During reflow TPRODUCT must not exceed 260 °C at any time.
Dry Pack Information
Surface mounted versions of the products are delivered in
standard moisture barrier bags according to IPC/JEDEC
standard J-STD-033 (Handling, packing, shipping and use of
moisture/reflow sensitivity surface mount devices).
Using products in high temperature Pb-free soldering
processes requires dry pack storage and handling. In case the
products have been stored in an uncontrolled environment and
no longer can be considered dry, the modules must be baked
according to J-STD-033.
Thermocoupler Attachment
Pin 2A for measurement of minimum Pin (solder
joint) temperature TPIN
SnPb solder processes
For SnPb solder processes, a pin temperature (TPIN) in excess
of the solder melting temperature, (TL, 183°C for Sn63Pb37) for
more than 30 seconds and a peak temperature of 210°C is
recommended to ensure a reliable solder joint.
For dry packed products only: depending on the type of solder
paste and flux system used on the host board, up to a
recommended maximum temperature of 245°C could be used,
if the products are kept in a controlled environment (dry pack
handling and storage) prior to assembly.
Pin 9B for measurement of maximum
Product temperature TPRODUCT
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MDC_OKDx-T/12-W12-C.A02 Page 32 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Soldering Information - Hole Mounting
The hole mounted product is intended for plated through hole
mounting by wave or manual soldering. The pin temperature is
specified to maximum to 270°C for maximum 10 seconds.
A maximum preheat rate of 4°C/s and maximum preheat
temperature of 150°C is suggested. When soldering by hand, care
should be taken to avoid direct contact between the hot soldering
iron tip and the pins for more than a few seconds in order to prevent
overheating.
A no-clean flux is recommended to avoid entrapment of cleaning
fluids in cavities inside the product or between the product and the
host board. The cleaning residues may affect long time reliability
and isolation voltage.
Delivery Package Information (SMT version)
The products are delivered in antistatic carrier tape
(EIA 481 standard).
Carrier Tape Specifications
Material
Surface resistance
Bakeability
Tape width, W
Pocket pitch, P1
Pocket depth, K0
Reel diameter
Reel capacity
Reel weight
PS, antistatic
7
< 10 Ohm/square
The tape is not bakeable
44 mm [1.73 inch]
24 mm [0.95 inch]
12.3 mm [0.488 inch]
381 mm [15 inch]
200 products /reel
1290 g/full reel
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MDC_OKDx-T/12-W12-C.A02 Page 33 of 35
OKDx-T/12-W12-001-C
12A Digital PoL DC-DC Converter Series
Soldering Information - Hole Mounting
The product is intended for plated through hole mounting by
wave or manual soldering. The pin temperature is specified to
maximum to 270°C for maximum 10 seconds.
A maximum preheat rate of 4°C/s and maximum preheat
temperature of 150°C is suggested. When soldering by hand,
care should be taken to avoid direct contact between the hot
soldering iron tip and the pins for more than a few seconds in
order to prevent overheating.
A no-clean flux is recommended to avoid entrapment of
cleaning fluids in cavities inside the product or between the
product and the host board. The cleaning residues may affect
long time reliability and isolation voltage.
Delivery Package Information (SIP)
The products are delivered in antistatic/static dissipative trays
Tray Specifications
Material
Antistatic Polyethylene foam
Surface resistance
10 < Ohms/square
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