SM6453AB

SM6453AB 3-wire Serial Data Volume Control for Headphone Amplifier IC OVERVIEW The SM6453AB is a stereo headphone amplifier IC with built-in electronic volume controlled by 3-wire serial data. Two switchable input systems are supported. It features bass boost function, automatic gain control (AGC) function, power-down function, and beep sound input/output function, making it ideal for use in portable electronic products. FEATURES I I PINOUT (Top view) I I I I I I I I I I I 2 stereo system inputs, selectable 1 output system Headphone amplifier function • +12dB to -68dB output voltage gain range (GCNT) • +12dB headphone amplifier gain (GHPA) Attenuation function • 1.0dB step width, 81 steps, 0 to –80dB range (GEVR) Mute function Bass boost function (2 boost characteristics controlled by external RC network) Auto gain control function (AGC) Beep sound input/output circuit 26mW+26mW maximum output power (1kHz, THD + N = 10%, 16Ω load, 2.0V supply voltage) Power-down function 1.8 to 3.6V operating supply voltage range Low current consumption (2.3mA total, 2.4V supply voltage) Silicon-gate CMOS process 32-pin QFN package DVDD1 DVDD2 DVSS LRMXO AGCTC BSTC BSTN MLEN MCK MDT RSTN MUTEN PDN BEEPI VREF1 VREF2 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10 11 12 13 14 15 16 BSTO BEEPLO LOUT AVSS2 AVDD2 AVDD3 AVSS3 ROUT BEEPRO PACKAGE DIMENSIONS (Unit: mm) ORDERING INFORMATION Device SM6453AB Package 5.00 ± 0.05 5.20 ± 0.1 (Top view) 6.00 ± 0.05 − C0 AVDD1 LIN1 LIN2 AVSS1 RIN1 RIN2 VBIAS (Bottom view) .2 0 6.20 ± 0.1 3 3.22TYP 32 1.00 0.50 32-pin QFN 2.68TYP .7 0 1 0.22 ± 0.05 0.50 1.00 0.90 ± 0.05 0.60 ± 0.10 C0 0.05 0.22 ± 0.05 0.05 M NIPPON PRECISION CIRCUITS INC.—1 0.005MIN 0.02TYP 0.04MAX 0.60 ± 0.10 SM6453AB PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name MLEN MCK MDT RSTN MUTEN PDN BEEPI VREF1 VREF2 AVDD1 LIN1 LIN2 AVSS1 RIN1 RIN2 VBIAS BEEPRO ROUT AVSS3 AVDD3 AVDD2 AVSS2 LOUT BEEPLO BSTO BSTN BSTC AGCTC LRMXO DVSS DVDD2 DVDD1 I/O1 Ip Ip Ip Ip I I I O O − I I − I I O O O − − − − O O O I O O O − − − Description Microcontroller latch enable input Microcontroller clock input Microcontroller data input System reset (LOW-level reset) Mute input (LOW-level mute) Power-down mode select (LOW-level power-down) Beep signal input Reference voltage 1 Reference voltage 2 EVR-stage analog VDD Left-channel analog input 1 Left-channel analog input 2 EVR-stage analog VSS Right-channel analog input 1 Right-channel analog input 2 EVR-stage bias voltage Right-channel beep signal output Right-channel output Headphone amplifier right-channel analog VSS Headphone amplifier right-channel analog VDD Headphone amplifier left-channel analog VDD Headphone amplifier left-channel analog VSS Left-channel output Left-channel beep signal output Bass boost auxiliary output Bass boost auxiliary input Bass boost capacitor connection AGC time constant set capacitor connection Left and right-channel mixer detector output Digital VSS Digital VDD2 Digital VDD1 VDD2 VDD1 VDD2 VDD 1. Ip = input with pull-up resistance VDD1, VDD2, VSS definitions VDD1 = DVDD2 = AVDD1 = AVDD2 = AVDD3 VDD2 = DVDD1 VSS = DVSS = AVSS1 = AVSS2 = AVSS3 NIPPON PRECISION CIRCUITS INC.—2 SM6453AB BLOCK DIAGRAM LRMXO AGCTC DVDD1 DVDD2 32 MLEN 1 31 30 29 28 27 26 25 BST BSTN DVSS BSTC BSTO Microcontroller Interface MCK Level Shifter 2 AGC 24 BEEPLO MDT 3 +12dB HPA 23 LOUT RSTN 4 EVR(0 to -80dB) 22 AVSS2 MUTEN 5 EVR AMP 21 AVDD2 PDN 6 EVR(0 to -80dB) +12dB HPA 20 AVDD3 BEEPI 7 EVR AMP 19 AVSS3 VREF1 8 VREF1 BEEP 18 ROUT VREF2 9 VREF2 Selector 10 AVDD1 11 LIN1 12 LIN2 17 BEEPRO 13 AVSS1 14 RIN1 15 RIN2 16 VBIAS NIPPON PRECISION CIRCUITS INC.—3 SM6453AB SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage Digital system input voltage1 Analog system input voltage2 Storage temperature Output current Power dissipation3 Symbol VDD1, VDD2 VIND VINA TSTG IO PD Rating − 0.3 to 4.6 VSS − 0.3 to VDD2 + 0.3 VSS − 0.3 to VDD1 + 0.3 − 55 to 125 100 370 Unit V V V °C mA mW 1. Digital system inputs: MLEN, MDT, MCK, RSTN, MUTEN, PDN, BEEPI 2. Analog system inputs: LIN1, LIN2, RIN1, RIN2, BSTN 3. NPC specified value θJa = 107.6°C/W PD = {(TJMAX – Ta)/θJa} (TJMAX = 125°C, Ta = 85°C) Recommended Operating Conditions VSS = DVSS = AVSS1 = AVSS2 = AVSS3 = 0V, VDD1 = DVDD2 = AVDD1 = AVDD2 = AVDD3, VDD2 = DVDD1 Parameter Supply voltage 1 Supply voltage 2 Symbol VDD1 VDD2 DVDD2-AVDD1, DVDD2-AVDD2, DVDD2-AVDD3, AVDD1-AVDD2, AVDD1-AVDD3, AVDD2-AVDD3 Ta Conditions 1.8 to 3.6 1.8 to 3.6 Unit V V Supply voltage difference ± 0.1 V Operating temperature − 40 to 85 °C NIPPON PRECISION CIRCUITS INC.—4 SM6453AB DC Characteristics AVSS1 = AVSS2 = AVSS3 = DVSS = 0V, AVDD1 = AVDD2 = AVDD3 = DVDD2 = 1.8 to 3.6V, DVDD1 = 1.8 to 3.6V, Ta = – 40 to 85°C unless otherwise noted. Rating Parameter Pins Symbol IDDD1A IDDD1S DVDD2 Current consumption AVDD1 + AVDD2 + AVDD3 IDDD2A IDDD2S IDDAA IDDAS IDDAM1 IDDAM2 IDDAT H-level Input voltage 1 (*1) L-level H-level Input voltage 2 Input current 1 Input current 2 Input leakage current 1 Input leakage current 2 Input leakage current 3 Input leakage current 4 (*2) L-level (*1) (*3) (*1) (*2) (*2) (*3) IIL1 IIH1 IIH2 IIL2 IIH3 IIL3 VIH1 VIL1 VIH2 VIL2 VIN = 0V VIN = VDD1 VIN = VDD1 VIN = 0V VIN = VDD1 VIN = 0V Condition min (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 3) (Note 4) (Note 5) – – – – – – – – – 0.8×DVDD1 – 1.2 – – – – – – – DVDD1 typ 0.03 0.2 0.05 0.2 2.3 13.0 1.7 0.5 7.0 – – – – 25 280 – – – – max 0.06 1.0 0.3 1.0 3.6 25.0 3.1 – 10.0 – 0.2×DVDD1 – 0.4 90 900 1.0 1.0 1.0 1.0 mA µA mA µA mA µA mA mA mA V V V V µA µA µA µA µA µA Unit (Note 1) MUTEN = HIGH, PDN = HIGH, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB, Microcontroller clock frequency = 4MHz, data transfer from microcontroller. (Note 2) MUTEN = LOW, PDN = LOW, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB, data transfer from microcontroller stopped, Pins (*1) = VDD2. (Note 3) MUTEN = LOW, PDN = HIGH, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB, data transfer from microcontroller stopped, Pins (*1) = VDD2. Other than idling current of final stage of headphone amplifiers. (Note 4) MUTEN = HIGH, PDN = HIGH, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB, data transfer from microcontroller stopped, Pins (*1) = VDD2. Idling current of final stage of headphone amplifiers only. (Note 5) MUTEN = HIGH, PDN = HIGH, reference voltage see "Measurement circuit", All analog inputs (LIN1, LIN2, RIN1, RIN2) connected reference input voltage, Bass boost = OFF, AGC = OFF, Frequency = 1kHz, PO = 0.5mW + 0.5mW Pin types Pin types (*1) (*2) (*3) Name MLEN, MDT, MCK, RSTN MUTEN, PDN BEEPI NIPPON PRECISION CIRCUITS INC.—5 SM6453AB AC Characteristics AVDD1 = AVDD2 = AVDD3 = DVDD1 = DVDD2 = 1.8 to 3.6V, AVSS1 = AVSS2 = AVSS3 = DVSS = 0V, Ta = – 40 to 85°C unless otherwise noted. Serial inputs (MDT, MCK, MLEN) Rating Parameter MCK, MLEN rise time MCK, MLEN fall time MDT setup time MDT hold time Setup time Hold time MLEN LOW-level pulsewidth HIGH-level pulsewidth Symbol min tr tf tMDS tMDH tMCS tMCH tMEWL tMEWH – – 50 50 50 50 50 50 typ – – – – – – – – max 100 100 – – – – – – ns ns ns ns ns ns ns ns Unit MDT tMDS MCK tMCS MLEN tMEWL tf MLEN MCK 0.9VDD2 0.1VDD2 0.5V DD2 tMDH 0.5V DD2 tMCH 0.5V DD2 tMEWH tr 0.9VDD2 0.1VDD2 Reset input (RSTN) Rating Parameter RSTN LOW-level pulsewidth Symbol min tRSTN 100 typ – max – ns Unit NIPPON PRECISION CIRCUITS INC.—6 SM6453AB AC Analog Characteristics VDD1 = VDD2 = 2.0V, analog input amplitude = 0.025Vrms, input frequency = 1kHz, Ta = 25°C, Measurement circuit, PDN = HIGH, MUTEN = HIGH, MDT D0 to D12 = LOW, unless otherwise noted. Analog input characteristics (LIN1, RIN1, LIN2, RIN2) Parameter Reference input amplitude Input resistance Input clipping voltage Symbol VAI RIN VCLP GEVR = 0dB, PO = 26mW + 26mW Condition GEVR = 0dB, PO = 0.5mW + 0.5mW Rating min 0.015 18 0.17 typ 0.025 23 0.21 max 0.035 – – Unit Vrms kΩ Vrms Analog output characteristics (LOUT, ROUT) Parameter Residual noise voltage Total harmonic distortion + noise Reference output power Reference output voltage Maximum output power Maximum output voltage Bass boost response AGC detection level Step width Symbol VNS THD + N POREF VOREF POMAX VOMAX BBST1 BBST2 VAGC GSTEP GERR1 Attenuation error (1kHz) GERR2 GERR3 GO1 GO2 Absolute attenuation (1kHz) GO3 GO4 GO5 Mute factor (1kHz) GMUTE CT1 Channel crosstalk CT2 CT3 PSRR1 Power supply ripple rejection ratio PSRR2 PSRR3 (Note 1) (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) (Note 7) (Note 8) (Note 9) GEVR = 0dB to – 60dB GEVR = – 61dB to – 72dB GEVR = – 73dB to – 80dB GO = + 12dB (GEVR = 0dB) GO = – 8dB (GEVR = – 20dB) GO = – 28dB (GEVR = – 40dB) GO = – 48dB (GEVR = – 60dB) GO = – 68dB (GEVR = – 80dB) (Note 3) (Note 4) (Note 5) (Note 6) (Note 7) (Note 8) (Note 9) GEVR = 0dB, THD + N = 10% GEVR = 0dB, THD + N = 10% (Note 1) (Note 2) 0.5VDD1 reference voltage output Condition GEVR = 0dB, A-WTD PO = 0.5mW + 0.5mW Rating min – – 0.4 0.08 22 0.516 + 5.2 + 12.0 + 0.30 0.1 − 2.8 – 2.0 – 1.2 + 9.2 – 10.6 – 30.6 – 50.4 – 70.5 – 100.0 − 69.0 − 29.0 − 30.0 83.0 45.0 34.0 typ 26 0.3 0.5 0.09 26 0.645 + 7.2 + 14.0 + 0.48 1.0 – 0.8 0 0.8 + 11.2 – 8.6 − 28.6 − 48.4 − 66.0 − 120.0 − 75.0 − 35.0 − 36.0 93.0 55.0 44.0 max 38 1.0 0.6 0.098 – – + 9.2 + 16.0 + 0.66 1.6 1.2 2.0 2.8 + 13.2 – 6.6 – 26.6 – 46.4 – 61.5 – – – – – – – Unit µVrms % mW Vrms mW Vrms dBr dBr V dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Microcontroller data bit D9 = HIGH, D10 = LOW, D11 = LOW, 55Hz frequency, VOREF output Microcontroller data bit D9 = HIGH, D10 = HIGH, D11 = LOW, 55Hz frequency, VOREF output GEVR = 0dB, MDT D0 to D7 are muted, MUTEN = HIGH, VOREF output Microcontroller data bit D9 = LOW, D11 = LOW, GEVR = 0dB, cross-channel leakage signal with VOREF output and standard voltage input on one channel only Microcontroller data bit D9 = HIGH, D10 = LOW, D11 = LOW, GEVR = 0dB, cross-channel leakage signal with VOREF output and standard voltage input on one channel only, Frequency = 10kHz Microcontroller data bit D9 = HIGH, D10 = HIGH, D11 = LOW, GEVR = 0dB, cross-channel leakage signal with VOREF output and standard voltage input on one channel only, Frequency = 10kHz PDN = LOW, MUTEN = HIGH, MDT = muted, ripple frequency = 100Hz and ripple amplitude = 0.1Vrms on AVDD1/AVDD2/AVDD3 PDN = HIGH, MUTEN = LOW, MDT = muted, ripple frequency = 100Hz and ripple amplitude = 0.1Vrms on AVDD1/AVDD2/AVDD3 PDN = HIGH, MUTEN = HIGH, MDT D0 to D12 = LOW, ripple frequency = 100Hz and ripple amplitude = 0.1Vrms on AVDD1/AVDD2/AVDD3 NIPPON PRECISION CIRCUITS INC.—7 SM6453AB Analog output characteristics (BEEPLO, BEEPRO) Rating Parameter BEEP output voltage Symbol VBO Condition min 2VP-O amplitude, 50% duty, 400Hz rectangular wave − 55 typ − 49.3 max − 44 dBv Unit Reference voltage characteristics (VREF1, VREF2, VBIAS) Rating Parameter Reference voltage output 1 Reference voltage output 2 Bias voltage output Symbol VREF1 VREF2 VBIAS Condition min 0.45VDD1 – 0.45VDD1 typ 0.5VDD1 VDD1 − 0.815 0.5VDD1 max 0.55VDD1 – 0.55VDD1 V V V Unit Measurement circuit VDD2 VDD1 VDD1 VREF1 VDD1 VREF1 VREF1 *1 820kΩ *2 *3 *4 0.01µF 33µF 0.1µF + 2200pF 32 31 30 DVSS 29 28 27 BSTC 26 BSTN BSTO 25 DVDD1 DVDD2 1 MLEN LRMXO AGCTC 2 MCK BEEPLO 24 3 MDT LOUT 23 220µF + 16Ω 4.7Ω NPC SM6453 VDD2 4 RSTN AVSS2 22 0.47µF VDD2 5 MUTEN AVDD2 21 + 220µF VDD1 VDD2 6 PDN AVDD3 20 + VDD1 220µF 7 BEEPI AVSS3 19 0.47µF 4.7Ω 16Ω 8 VREF1 ROUT 18 + 220µF BEEPRO LIN1 11 1µF LIN2 9 VREF2 AVDD1 10 10µF + + 17 AVSS1 13 10µF + RIN1 14 1µF RIN2 15 1µF VBIAS 16 12 1µF 100µF VDD1 10µF *1 to *4: AGC time constant setting components. Measured with *4 open circuit. + NIPPON PRECISION CIRCUITS INC.—8 SM6453AB FUNCTIONAL DESCRIPTION Microcontroller Interface The SM6453AB uses a serial microcontroller interface comprising MDT (data), MCK (clock), MLEN (latch enable). Data format The data transfer format is shown in figure 1. MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCK MLEN Figure 1. Microcontroller data input timing The internal shift register shifts data on the rising edge of MCK, and the data is loaded and updated on the rising edge of MLEN (dotted lines also indicate valid data timing). Each cycle is completed by 16 or more MCK input cycles, even if there are unused data bits. NIPPON PRECISION CIRCUITS INC.—9 SM6453AB Microcontroller data description Definition: “L” = VIL1 level, “H” = VIH1 level MDT D15 D14 D13 D12 D11 D10 D9 AGC ON/OFF Bass boost mode select Bass boost ON/OFF Don't care D8 Input select D7 D6 D5 D4 D3 D2 D1 D0 EVR gain setting GEVR: 0dB to -80dB, MUTE Figure 2. Microcontroller data description I I D15 to D12: Not used (don’t care) bits. Can be either “L” or “H”. D11: AGC bit. OFF when “L”, and ON when “H”. AGC = OFF when system reset (see “Automatic gain control function”). D11 LOW HIGH AGC function OFF ON I D10, D9: Bass boost control bits. Bass boost = OFF and bass boost mode = BB1 when system reset (see “Bass boost function”). D9 D10 LOW LOW HIGH LOW HIGH HIGH BB2 BB1 OFF Bass boost characteristics I D8: Input select bit. LIN1 and RIN1 when “L”, and LIN2 and RIN2 when “H”. LIN1 and RIN1 input when system reset. D8 LOW HIGH Selected inputs LIN1, RIN1 LIN2, RIN2 LIN2 RIN2 LIN1 RIN1 Input Selector Input Input Selector Block D8=L/D8=H LIN1/LIN2 RIN1/RIN2 To EVR Block Output NIPPON PRECISION CIRCUITS INC.—10 SM6453AB I D7 to D0: EVR gain control bits. MUTE when system reset. LIN1 LIN2 Input Selector Block 0dB EVR Block Gain (GEVR) : 0 to −80dB variable, MUTE Headphone Amplifier Block Gain (GHPA) : +12dB fixed, MUTE LOUT Gain: GEVR + GHPA = GO GO: +12dB to −68dB, MUTE RIN1 RIN2 ROUT Microcontroller Interface Figure 3. Electronic volume gain (GEVR) setting and output voltage gain (GO) EVR gain (GEVR) 0dB – 1dB – 2dB : − 15dB − 16dB − 17dB : − 63dB − 64dB − 65dB : − 79dB − 80dB MUTE MUTE : MUTE MUTE LOUT, ROUT gain (GO) + 12dB + 11dB + 10dB : − 3dB − 4dB − 5dB : − 51dB − 52dB − 53dB : − 67dB − 68dB MUTE MUTE : MUTE MUTE D7 L L L : L L L : L L L : L L L L : H H D6 L L L : L L L : L H H : H H H H : H H D5 L L L : L L L : H L L : L L L L : H H D4 L L L : L H H : H L L : L H H H : H H D3 L L L : H L L : H L L : H L L L : H H D2 L L L : H L L : H L L : H L L L : H H D1 L L H : H L L : H L L : H L L H : H H D0 L H L : H L H : H L H : H L H L : L H HEX 00 01 02 : 0F 10 11 : 3F 40 41 : 4F 50 51 52 : FE FF MLEN MCK MDT NIPPON PRECISION CIRCUITS INC.—11 SM6453AB System Reset Function (RSTN) The system is reset using a LOW-level pulse on RSTN. After the system is reset, AGC is OFF, bass boost mode is BB1, input selector is LIN1/RIN1, and LOUT/ROUT output voltage gain is muted. AGC OFF Bass boost mode BB1 Bass boost function OFF Input Select LIN1, RIN1 EVR gain (GEVR) MUTE Output gain (GO) MUTE Bass Boost Function with Automatic Gain Control (AGC) Equivalent circuit 240kΩ ROUT 32kΩ 60kΩ Bass Boost Block CINR1 1µF Rch 1 RIN1 *2 *2 60kΩ Headphone Amp VREF1 C2 COUT 220µF 0.47µF ROUT 0.47µF ROUT 16Ω 16Ω R1 EVR Block RIN (Equivalent input resistance:23kΩ) *3 40kΩ BSTO CINR2 1µF Input Selector Rch 2 RIN2 *2 VREF1 BSTN 2200pF R3 *4 240kΩ LOUT LRMXO 60kΩ COUT 220µF CINL1 1µF Lch 1 LIN1 *2 0.1µF Lch 2 LIN2 VREF1 VREF1 VDD VREF1 VREF1 VREF1 33µF *1 *1 0.01µF AGCTC AGC Amp AGC Block VREF1 VREF1 VREF1 *1: From “Measurement circuit”. Adjustment AGC detection level and time constant. *2: CINR1 = CINL1, CINR2 = CINL2 → CIN *3: RIN1 = LIN1 → R1 = (R1R/2 + R1L/2) = 20kΩ *4: BB1 → R3 = 15kΩ, BB2 → R3 = 60kΩ NIPPON PRECISION CIRCUITS INC.—12 820kΩ *1 *1 4.7Ω CINL2 1µF Headphone Amp 32kΩ (Equivalent input resistance:23kΩ) BSTC C1 10kΩ R2 EVR Block RIN R1L 40kΩ 2kΩ Bass Boost Amp 60kΩ 4.7Ω R1R SM6453AB Bass boost function (BSTO, BSTN, BSTC) The bass boost characteristic (BB1, BB2) is selected using bit D10. The left-channel and right-channel bass components are mixed and amplified, and then added to the headphone driver amplifier. A capacitor (0.1µF std) connected between BSTC and VREF1 forms a lowpass filter through which the signal from the EVR block passes, boosting the bass component, which is then added to the original signal. Bass boost examples IC internal components are RIN = 23kΩ, R1 = 20kΩ, R2 = 10kΩ, R3 = 15kΩ (BB1) or 60kΩ (BB2). The bass boost characteristic also depends on the external resistor and capacitor components connected between BSTO and BSTN, as indicated below. I Example 1 C1 = 0.1µF, C2 = 2200pF, CIN = 1µF, COUT = 220µF, ROUT = 16Ω (Measurement circuit) 15 10 5 BB2 BB1 [dBr] 0 -5 BB OFF -10 -15 10 100 1000 Frequency [Hz] 10000 I Example 2 C1 = 0.1µF, C2 = 0.01µF, CIN = 1µF, COUT = 220µF, ROUT = 16Ω 15 10 5 BB2 BB1 [dBr] 0 -5 BB OFF -10 -15 10 100 1000 Frequency [Hz] 10000 NIPPON PRECISION CIRCUITS INC.—13 SM6453AB I Example 3 C1 = 0.1µF, C2 = 0.047µF, CIN = 1µF, COUT = 220µF, ROUT = 16Ω 15 BB2 10 BB1 5 [dBr] 0 -5 BB OFF -10 -15 10 100 1000 Frequency [Hz] 10000 I Example 4 C1 = 0.22µF, C2 = 6800pF, CIN = 0.47µF, COUT = 47µF, ROUT = 16Ω, 2700Ω resistor connected between BSTN and VREF1 Note that when the output coupling capacitance COUT is small, the bass signal component margin available before reaching the bass output saturation level is considerably reduced. 15 10 5 0 –5 – 10 – 15 – 20 – 25 – 30 – 35 10 BB2 BB1 [dBr] BB OFF 100 Frequency [Hz] 1000 10000 Automatic gain control (AGC) function The AGC function is selected using bit D11. When bass boost is on, whenever the magnitude of either the positive or negative output voltage peak value of LOUT or ROUT exceeds VREF1 + 0.48V (typ), half-wave rectification starts. The resulting detected and smoothed DC potential is compared with the VREF1 potential, and the comparator output signal is used to control the reduction in bass boost gain, thereby increasing the headphone amplifier output bass clip margin. NIPPON PRECISION CIRCUITS INC.—14 SM6453AB Power-down Function (PDN) The power-down function is selected when PDN goes LOW. This reduces the power consumption, while LOUT and ROUT become high impedance. A pull-down resistor connected to PDN is recommended. Mute Function Mute function (MUTEN) The mute function is selected when MUTEN goes LOW. At initial startup, it is recommended that a delay of 2.5 seconds (typ) occur before MUTEN goes HIGH to prevent pop-noise output on LOUT and ROUT that can occur when muting is released and after power-down is released (see mute release timing in figures 4 and 5). Note that when muting using the MUTEN pin, outputs LOUT and ROUT do not become high impedance. A pull-down resistor connected to MUTEN is recommended. 2.5 [sec] Reset RSTN PDN MUTEN MDT LOUT/ROUT Current consumption MUTE High Impedance Power Down MUTE ON Medium Impedance High Impedance (Power ON) MUTE OFF MUTE OFF Low Impedance Figure 4. Initial startup recommended mute release timing example 1 Reset 2.5 [sec] RSTN PDN MUTEN MDT LOUT/ROUT Current consumption MUTE High Impedance Power Down MUTE ON Medium Impedance (Power ON) MUTE OFF MUTE OFF Low Impedance Figure 5. Initial startup recommended mute release timing example 2 Mute function (Microcontroller Data) Mute is ON when Microcontroller Data D0 to D7 = LOW. Output impedance is HIGH when Microcontroller Data D0 to D7 = LOW, Mute function. Beep Signal Input/Output (BEEPI, BEEPLO, BEEPRO) The beep signal is a constant-current output signal on BEEPLO and BEEPRO in response to an input signal on BBEPI. The beep signal input/output circuit should be used when MUTEN is HIGH, when muting using the attenuation data bits D0 to D7, and during power-down. NIPPON PRECISION CIRCUITS INC.—15 SM6453AB TYPICAL RESPONSE VDD1 = VDD2 = 2.0V, analog input amplitude = 0.025Vrms, input frequency = 1kHz, Ta = 25°C, Measurement circuit, PDN = HIGH, MUTEN = HIGH, MDT D0 to D12 = LOW, unless otherwise noted 10 9 8 supply current [mA] 0.5mW+0.5mW (16Ω) 10 7 6 5 4 3 2 1 0 1.5 2.0 THD+N [%] 1 0.5mW+0.5mW (16Ω) No signal (16Ω) 10mW+10mW (16Ω) 2.5 3.0 supply voltage:VDD1 [V] 3.5 4.0 0.1 1.5 2.0 2.5 3.0 supply voltage:VDD1 [V] 3.5 4.0 Figure 6. Current consumption vs. Supply voltage Figure 7. THD+N vs. Supply voltage 100 100 THD+N [%] THD+N [%] 10 10 1 1 0.1 0.001 0.01 0.1 1 output power [mW] 10 100 0.1 0.001 0.01 input level [V] 0.1 1 Figure 8. THD+N vs. Output power Figure 9. THD+N vs. Input voltage 100 10 output power [mW] output power [mW] 0.01 input level [V] 0.1 1 1 0.1 0.01 100 90 80 70 60 50 40 30 20 10 0.001 0.0001 0.001 0 1.5 2.0 2.5 3.0 supply voltage:VDD1 [V] 3.5 4.0 Figure 10. THD+N vs. Input voltage Figure 11. Maximum output power vs. Supply voltage NIPPON PRECISION CIRCUITS INC.—16 SM6453AB 30 25 noise level:VNS [µV] cross talk:CT1, CT2, CT3 [dB] GEVR = 0dB 100 90 80 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 supply voltage:VDD1 [V] 3.5 4.0 BB2:CT3 BB1:CT2 BB OFF:CT1 20 15 10 5 0 1.5 GEVR = –12dB 2.0 2.5 3.0 supply voltage:VDD1 [V] 3.5 4.0 Figure 12. Noise level vs. Supply voltage Figure 13. Channel separation vs. Supply voltage 30 20 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 1.5 GEVR = 0dB (GO = +12dB) GEVR = –20dB (GO = –8dB) GEVR = –40dB (GO = –28dB) GEVR = –60dB (GO = –48dB) GEVR = –80dB (GO = –68dB) 12 2 –8 GO [dB] –18 –28 –38 –48 Absolute gain [dB] MUTE –58 –68 3.5 4.0 2.0 2.5 3.0 supply voltage:VDD1 [V] 0 –10 –20 –30 –40 GEVR [dB] –50 –60 –70 –80 Figure 14. Absolute gain vs. Supply voltage Figure 15. Output voltage gain vs. EVR gain setting 2.0 1.5 gain error:GERR [dB] 1.0 0.5 0.0 –0.5 –1.0 –0.5 –2.0 0 –10 –20 –30 –40 GEVR [dB] –50 –60 –70 –80 [dBr] 15 14 13 12 11 10 9 8 7 6 5 1.5 2.0 2.5 3.0 supply voltage:VDD1 [V] 3.5 4.0 BB1 BB2 Figure 16. Gain error Figure 17. Bass boost gain vs. Supply voltage NIPPON PRECISION CIRCUITS INC.—17 SM6453AB +20 +15 +10 +5 dBr +0 –5 –10 –15 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 0.70 BB2 AGC voltage:VAGC [V] 0.65 0.60 0.55 0.50 0.45 0.40 0.35 1.5 2.0 2.5 3.0 supply voltage:VDD1 [V] 3.5 4.0 BB1 BB OFF Figure 18. Frequency response vs. Bass boost Figure 19. AGC level vs. Supply voltage 0 –10 –40 VDD1 = 3.6V –50 VDD1 = 1.8V BEEP out level:VBO [dBv] BEEP out level:VBO [dBv] 3.5 4.0 –60 –70 –80 –90 –100 –110 0 0.5 1.0 1.5 2.0 2.5 BEEPI level [VP-O] 3.0 3.5 4.0 –20 –30 –40 BEEPI = 2.0VP-0 –50 –60 1.5 2.0 2.5 3.0 supply voltage:VDD1 [V] Figure 20. Beep sound output level vs. Supply voltage Figure 21. Beep sound output level vs. Beep input level NIPPON PRECISION CIRCUITS INC.—18 SM6453AB NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: sales@npc.co.jp NC0024AE 2002.04 NIPPON PRECISION CIRCUITS INC.—19