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54LS74LMQB

54LS74LMQB

  • 厂商:

    NSC

  • 封装:

  • 描述:

    54LS74LMQB - Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs ...

  • 数据手册
  • 价格&库存
54LS74LMQB 数据手册
54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs Features Y Alternate military aerospace device (54LS74) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6373 – 1 Order Number 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74AJ DM54LS74AW DM74LS74AM or DM74LS74AN See NS Package Number E20A J14A M14A N14A or W14B Function Table Inputs PR L H L H H H CLR H L L H H H CLK X X X D X X X H L X Outputs Q H L H H L Q0 Q L H H L H Q0 u u L H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level u e Positive-going Transition e This configuration is nonstable that is it will not persist when either the preset and or clear inputs return to their inactive (high) level Q0 e The output logic level of Q before the indicated input conditions were established C1995 National Semiconductor Corporation TL F 6373 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55 C to a 125 C DM54LS and 54LS DM74LS 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Clock High Preset Low Clear Low tW Pulse Width (Note 3) Clock High Preset Low Clear Low tSU tSU tH TA Setup Time (Notes 1 and 2) Setup Time (Notes 1 and 3) Hold Time (Note 1 and 4) Free Air Operating Temperature 0 0 18 15 15 25 20 20 20u 25u 0u b 55 DM54LS74A Nom 5 Max 55 Min 4 75 2 07 b0 4 DM74LS74A Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA MHz MHz 4 25 20 0 0 18 15 15 25 20 20 20u 25u 0u 125 0 8 25 20 ns ns ns ns ns 70 C Note 1 The symbol ( u) indicates the rising edge of the clock pulse is used for reference Note 2 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V Note 3 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V Note 4 TA e 25 C and VCC e 5V 2 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4 mA VCC e Min II Input Current Max Input Voltage VCC e Max VI e 7V DM54 DM74 DM54 DM74 DM74 Data Clock Preset Clear IIH High Level Input Current VCC e Max VI e 2 7V Data Clock Clear Preset IIL Low Level Input Current VCC e Max VI e 0 4V Data Clock Preset Clear IOS Short Circuit Output Current Supply Current VCC e Max (Note 2) VCC e Max (Note 3) DM54 DM74 b 20 b 20 Min Typ (Note 1) Max b1 5 Units V V 25 27 34 34 0 25 0 35 0 25 04 05 04 01 01 02 02 20 20 40 40 b0 4 b0 4 b0 8 b0 8 b 100 b 100 VOL V mA mA mA mA mA ICC 4 8 Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second For devices with feedback from the outputs where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2 25V and 2 125V for DM54 and DM74 series respectively with the minimum and maximum limits reduced by one half from their stated values This is very useful when using automatic test equipment Note 3 With all outputs open ICC is measured with CLOCK grounded after setting the Q and Q outputs high in turn Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 2 kX CL e 15 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clock to Q or Q Clock to Q or Q Preset to Q Preset to Q Clear to Q Clear to Q 3 25 25 30 25 30 25 30 Max CL e 50 pF Min 20 35 35 35 35 35 35 Max MHz ns ns ns ns ns ns Units Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS74LMQB NS Package Number E20A 14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS74DMQB or DM54LS74AJ NS Package Number J14A 4 Physical Dimensions inches (millimeters) (Continued) 14-Lead Small Outline Molded Package (M) Order Number DM74LS74AM NS Package Number M14A 14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS74AN NS Package Number N14A 5 54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flat Package (W) Order Number 54LS74FMQB or DM54LS74AW NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
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