LM3686TLE-AAED

LM3686 Step-Down DC-DC Converter with Integrated Post Linear Regulators System and LowNoise Linear Regulator December 17, 2008 LM3686 Step-Down DC-DC Converter with Integrated Post Linear Regulators System and Low-Noise Linear Regulator General Description The LM3686 is a step-down DC-DC converter with one integrated very low dropout linear regulator and a low noise linear regulator optimized for powering ultra-low voltage circuits from a single Li-Ion cell or 3 cell NiMH/NiCd batteries. It provides three outputs with combined load current up to 900 mA over an input voltage range from 2.7V to 5.5V. The device offers superior features and performance for many applications. Automatic intelligent switching between PWM low-noise and PFM low-current mode offers improved system control. During full-power operation, a fixed-frequency 3 MHz (typ.), PWM mode drives loads from ~70 mA to 600 mA max. Hysteretic PFM mode extends the battery life through reduction of the quiescent current to 28 μA (typ.) at light load and system standby. Internal synchronous rectification provides high efficiency. Three enable pins allow the separate operation of either the DC-DC, post-regulation linear regulator or the linear regulator alone. If the DC-DC is not enabled during startup of the postregulation linear regulator, a parallel small pass transistor supplies the linear regulator from VBATT with maximal 50 mA. In the combined operation where both enables are raised together, the small pass transistor is deactivated and the big pass transistor provides 350 mA output current. In shutdown mode (Enable pins pulled low), the device turns off and reduces battery consumption to 2.5 μA (typ.). The LM3686 is available in a 12-bump micro SMD package. A high-switching frequency of 3 MHz (typ.) allows the use of a few tiny surface-mount components. Only six external surface-mount components, an inductor and five ceramic capacitors, are required to establish a 15.66 mm2 total solution size. Features DC-DC REGULATOR ■ VOUT_DCDC = 1.2V to 2.5V ( in 100 mV steps - factory programmed ) ■ 600 mA maximum load capability (LILO = OFF) ■ 3 MHz PWM fixed switching frequency (typ.) ■ Automatic PFM/PWM mode switching ■ Internal synchronous rectification for high efficiency ■ Internal soft start DUAL RAIL LINEAR REGULATOR: LILO ■ Load transients < 50 mV peak typ. ■ Line transients < 1 mV peak typ. ■ VOUT_LILO = 0.7V to 2.0V ( in 50 mV steps - factory programmed ) ■ 70 µA typical IQ from VIN_LILO ■ 350 mA Maximum Load Capability (Large FET) LINEAR REGULATOR: LDO ■ Load transients < 80 mV peak typ. ■ Line transients < 1 mV peak typ. ■ VOUT_LDO = 1.5V to 3.3V ( in 100 mV steps - factory programmed ) ■ 50 µA typical IQ ■ 300 mA Maximum Load Capability COMBINED GLOBAL FEATURES ■ VBATT ≥ VOUT_LILO + 1.5V or 2.7V, whichever is higher ■ 900 mA maximum combined load capability ■ Operates from a single Li-Ion cell or 3 cell NiMH/NiCd batteries ■ Only six tiny surface-mount external components required (one inductor, five ceramic capacitors) ■ 12–bump micro SMD ■ 100 µA Iq from VBATT ■ 15.66 mm2 total solution size Applications ■ ■ ■ ■ ■ ■ ■ Moblie TV Hand-Held Radios Personal Digital Assistants Palm-top PCs Portable Instruments Battery-Powered Devices Portable Personal Clients © 2008 National Semiconductor Corporation 300255 www.national.com LM3686 Typical Application Circuit 30025501 FIGURE 1. Typical Application www.national.com 2 LM3686 30025502 FIGURE 2. Functional Diagram (Always Connenct VIN_LDO to VBATT) 3 www.national.com LM3686 Connection Diagram 30025503 12-pin micro SMD package Pin Descriptions Pin Number A1 A2 A3 B1 B2 B3 C1 C2 C3 D1 D2 D3 Symbol PGND SW FB_DCDC VBATT EN_LILO EN_DCDC VIN_LDO EN_LDO QGND VOUT_LDO VOUT_LILO VIN_LILO Name and Function Power Ground pin Switching node connection to the internal PFET switch and NFET synchronous rectifier. Feedback analog input for the DC-DC converter. Connect to the output filter capacitor. Power supply input for switcher. Connect to the input filter capacitor. Enable input for the linear regulator. The linear regulator is in shutdown mode if voltage at this pin is < 0.4V and enabled if > 1.1V. Do not leave this pin floating. Enable input for the DC-DC converter. The DC-DC converter is in shutdown mode if voltage at this pin is < 0.4V and enabled if > 1.1V. Do not leave this pin floating. Input power to LDO. ( Must tie to VBATT at all times ) Enable input for the linear regulator. The linear regulator is in shutdown mode if voltage at this pin is < 0.4V and enabled if > 1.1V. Do not leave this pin floating. Quiet GND pin for LDO and reference circuit. Voltage output of the linear regulator. Voltage output of the low input linear regulator Input power to LILO (VIN_LILO connects to output of DCDC or standalone). Order Information Part Number LM3686TL-AADW LM3686TLX-AADW LM3686TLE-AAED LM3686TLX-AAED LM3686TLE-AAEF LM3686TLX-AAEF Voltage Options 1.81.22.8 1.81.22.8 1.21.82.8 1.21.82.8 1.81.23.0 1.81.23.0 Package Marking ¢2¢X*$I¢CSUEB ¢2¢X*$I¢CSUEB ¢2¢X*$I¢CSUEB ¢2¢X*$I¢CSUEB ¢2¢X*$I¢CSUEB ¢2¢X*$I¢CSUEB Supplied as 250 units, tape and reel 3000 units, tape and reel 250 units, tape and reel 3000 units, tape and reel 250 units, tape and reel 3000 units, tape and reel *Voltage options are read as follow: 1.81.22.8 = 1.8V for VOUT_DC-DC, 1.2V for VOUT_LILO, and 2.8V for VOUT_LDO; Contact National Semiconductor for other factory VOUT programmed options. www.national.com 4 LM3686 Enable Combinations EN_DCDC 0 0 0 1 1 EN_LILO 0 0 1 0 1 EN_LDO 0 1 0 0 0 Function No Outputs Linear Regulator enabled only (EN_LDO), supply from VIN_LDO, IOUT_MAX = 300 mA Linear Regulator enabled only LILO supplies from VIN_LDO, IOUT_MAX = 50 mA, VIN_LDO > = VOUT_LILO DC-DC converter enabled only Linear Regulator & DCDC enabled 1) VIN_LILO < VOUT_LILO + 150 mV (typ.), the small NMOS device is active (IMAX = 50 mA) and supplied by VIN_LDO. 2) If VIN_LILO > VOUT_LILO + 250 mV (typ.), the large NMOS device is active (IMAX = 350 mA) and supplied by VIN_LILO. Maxium current of DC-DC when EN_LILO = High is 250 mA (Note A & B) DC-DC converter and linear regulator active. Linear regulator starts after DC-DC converter. 1 1 1 Note A: The LILO is turned on via a small NMOS device supplied by VIN_LDO . The maximum current is 50 mA when this small NMOS is ON. If higher current > 50 mA is desired the following condition must be done: EN_DC = HIGH . Note B: When the switcher is enabled, a transition occurs from the small NMOS to a larger NMOS. The transition occurs when VIN_LILO > VOUT_LILO + 250 mV. If VIN_LILO < VOUT_LILO + 150 mV, the LILO switches back to small NMOS (Switcher EN = low). 30025532 FIGURE 3. Mode Transition 5 www.national.com LM3686 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VBATT pin to GND and QGND Enable pins, Feedback pins, SW pin Junction Temperature (TJ-MAX ) Storage Temperature Range Continuous Power Dissipation (Note 3) Maximum Lead Temperature (Soldering) -0.2V to 6.0V (GND-0.2V) to (VBATT+0.2V) with 6.0V max 150°C -65°C to + 150°C Internally Limited (Note 4) Operating Ratings Input Voltage Range VBATT (DC-DC & LDO) Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 5) 2.7V to 5.5V -40°C to + 125°C -40°C to + 85°C Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) (Note 6) Micro SMD 12 120°C/W Electrical Characteristics (Notes 2, 7, 9, 10) Limits in standard typeface are for TA = 25°C. Limits appearing in boldface type apply over the full operating ambient temperature range: -40°C ≤ TA= TJ ≤ +85°C. Unless otherwise noted, specifications apply to the closed loop typical application circuits (linear regulator) with VIN_LDO = VBATT = 3.6V(Note 17) , VIN_LILO = VOUT_DCDC(NOM), VEN (All) = VBATT, CIN_DC = 4.7 µF, COUT_LILO = 2.2 µF, CIN_LDO = 1.0 µF , COUT_LDO = 1.0 µF ,COUT_DC = C IN_LILO = 10 µF Linear Regulator — LILO (EN_DCDC = EN_LILO = ON - Large NMOS) Symbol ΔVOUT_LILO / VOUT_LILO Parameter Output Voltage Accuracy, VOUT_LILO Load Regulation (Note 15) Condition Min IOUT_LILO = 1 mA to 350 mA VIN_LILO = VOUT_DCDC VBATT = 3.6V IOUT_LILO = 1 mA & 350 mA VIN_LILO = VOUT_DCDC VBATT = 3.6V VBATT = VOUT_LILO + 1.5V (VIN_LILO disconnected from VOUT_DCDC), IOUT = 350 mA VBATT = VIN_LILO = 3.6V VOUT = GND (VOUT_LILO = 0 ) 400 1.176 4 Limits Typ 1.2 1.224 12 V µV/mA Max Units ΔVOUT_LILO / ΔmA 50 80 mV VDROP Dropout Voltage (Note 8) Quiescent Current Short Circuit Current Limit Output Voltage Accuracy, VOUT_LILO Line Regulation (Small NMOS) (Note 14) Short circuit current Start up time IQ_VIN_LILO ISC_LILO 70 90 µA mA LILO (EN_DCDC = OFF, EN_LILO = ON - SMALL NMOS) ΔVOUT_LILO / VOUT_LILO ΔVOUT_LILO / ΔVBATT ISC_LILO TSTARTUP PSRR IOUT = 1 mA to 50 mA 1.176 1.224 V VIN_LILO = (VOUT_LILO + 0.3V) to 5.5V 0.4 1.5 mV/V VOUT_LILO = GND EN to 0.95VOUT 70 70 mA µS System Characteristic (Note 13) Signal to VBATT = 3.6V, VIN_LILO = 1.8V IOUT = 200 mA, Power Supply Rejection f = 100 Hz Ratio(Note 12) Signal to VIN_LILO = 1.8V IOUT = 200 mA, f = 1kHz 68 dB 60 www.national.com 6 LM3686 Symbol eN_LILO Parameter Condition Min BW = 10 Hz to 100 kHz, VIN_LILO = 1.8V, IOUT = 200 mA, VIN_LDO = 3.6V Pulsed load 1 mA - 350 mA di/dt = 350 mA/1µS VBATT = 3.1V to 3.7V VIN_LILO = VOUT_DCDC tr, tf = 10 µS, IOUT = 200 mA Limits Typ Max Units Output Noise voltage (Note 12) ΔVOUT_LILO ΔVIN_LILO Dynamic load transient response Dynamic line transient response on VBATT 166 µVRMS +/- 30 mV +/-15 mV Linear Regulator — LDO Symbol VIN_LDO ΔVOUT_LDO/ VOUT_LDO ΔVOUT_LDO/ΔmA Parameter LDO input voltage range Output voltage accuracy, VOUT_LDO Load regulation(Note 15) VIN = 3.6V IOUT_LDO = 1 mA & 300 mA IOUT_LDO = 1 mA & 300 mA Conditions Min 2.7 2.744 2.94 2.8 3.0 8 0.2 120 50 350 200 80 Typical Limit Typ Max 5.5 2.856 3.06 V µV/mA mV/V mV µA mA V Units ΔVIN_LDO/ΔVBATT Line regulation(Note 14) VIN_LDO = (VOUT_LDO(NOM) + 0.3V) to 5.5V VDROP IQ ISC-LDO PSRR Dropout voltage(Note 8) IOUT = 300 mA Quiescent current Ven = 0.95V, IOUT = 0 mA Short circuit current limit VOUT = GND Power supply rejection ratio EN_DC = EN_LILO = GND f = 1 kHz, IOUT = 200 mA f = 10 kHz, IOUT = 200 mA Signal to VIN_LDO = 3.6V eN_LDO Output noise voltage (Note 12) Dynamic line transient response Dynamic load transient response BW = 10 Hz to 100 kHz, VIN_LDO = 3.6V IOUT = 200 mA VIN_LDO = 3.8V to 4.4V tr, tf = 30 µs IOUT = 1 mA Pulsed load 1 mA & 300 mA tr, tf = 10 µs System Characteristic (Note 13) 85 dB 70 6.7 µVRMS ΔVIN_LDO ΔVOUT_LDO +/-2 mV +/-30 mV 7 www.national.com LM3686 DC-DC Converter Symbol VFB_DCDC VREF RDSON(P) RDSON(N) IQ_AUTO ILIM FOSC Parameter Feedback Voltage Accuracy Internal reference voltage Pin-Pin Resistance for VBATT = 3.6V PFET ISW = 100 mA Pin-Pin Resistance for VBATT = 3.6V NFET ISW = 100 mA Quiescent current for auto mode Switch peak current limit Internal Oscillator Frequency No load, device is not switching, FB = HIGH Open loop PWM Mode 1.035 2.4 Conditions Min PWM Mode (Note 11) 1.746 Limit Typ 1.8 0.5 Max 1.836 V V 450 250 40 1.375 3.4 mΩ mΩ µA A MHz Units 350 150 28 1.220 3 Global Parameters (DCDC, LILO, & LDO) Symbol Parameter Conditions Typical Limit Min Typ Max Units IQ_VBATT Full power mode I =I =I = 0 mA, DC-DC Quiescent current into OUT_DCDC OUT_LILO OUT_LDO is not switching (FB_DCDC forced higher than VBATT VOUT_DCDC) Ven = 1.1V, Shutdown current into VEN_DCDC = VEN_LILO = VEN_LDO = 0V VBATT Enable pin input current Logic high input Logic low input All EN = 0V 1.1 100 130 µA IQ_GLOBAL 2.5 4 µA Enable Pins (EN_DCDC, EN_LILO, EN_LDO) IEN VIH VIL .01 1 µA V 0.40 V www.national.com 8 LM3686 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1112: Micro SMD Wafer Level Chip Scale Package (AN-1112) Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special attention must be paid to thermal dissipation issues in board design. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical (typ.) numbers are not guaranteed, but do represent the most likely norm. Unless otherwise specified, conditions for typ. specifications are: VBATT = 3.6V and TA = 25°C. Note 8: Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100 mV below the nominal output voltage. Note 9: The parameters in the electrical characteristic table are tested at VBATT = 3.6V unless otherwise specified. For performance over the input voltage range refer to datasheet curves. Note 10: The input voltage range recommended for ideal applications performance for the specified output voltages is given below: VBATT = 2.7V to 5.5V for 1.0V ≤ VOUT_DCDC < 1.8V VBATT = (VOUT_DCDC + 1V) to 5.5V for 1.8V ≤ VOUT_DCDC < 3.6V Note 11: Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Note 12: The noise performance target is applied to PWM mode operation and this does not apply when DCDC converter is operating in PFM mode. Note 13: Parameters guaranteed by design. Note 14: To calculate the output voltage from the line regulation specified, use the following equation: ΔVOUT = Line Regulation (%/V) x Nominal VOUT (V) x ΔVIN (V). Note 15: To calculate the output voltage from the load regulation specified, use the following equation: ΔVOUT = Load Regulation (%/mA) x Nominal VOUT (V) x ΔIOUT (mA). Note 16: For line and load transient specifications, the + symbol represents an overshoot in the output voltage and the – symbol represents an undershoot in the output voltage. The first value signifies overshoot or undershoot at the rising edge and the second value signifies the overshoot or undershoot at the falling edge. Note 17: VIN_LDO must be ON at all time for biasing internal reference circuits 9 www.national.com LM3686 Typical Performance Characteristics VOUT_DCDC vs. IOUT_DCDC Unless otherwise specified, typical application (post regulation), VBATT = 3.6V, TA = 25°C, enable pins tied to VBATT, VOUT_DCDC = 1.8V, VOUT_LILO = 1.2V, VOUT_LDO = 2.8V VOUT_LILO vs. IOUT_LILO 30025511 30025512 Efficiency DC-DC vs. Output Current LILO and LDO disabled PSRR vs. Frequency (LILO - VIN_LILO = 3.6V) 30025534 30025540 PSRR vs. Frequency (LDO - VIN_LDO = 3.6V) Noise vs. Frequency (LDO - VIN_LDO = 3.6V) 30025536 30025535 www.national.com 10 LM3686 Switching Frequency vs. Temperature Current Limit vs. Temperature (Open Loop) 30025537 30025538 RDSON vs. Temperature Startup (all three enables tied together) 30025524 30025539 VBATT Line Transient Response Line Transient Response 30025525 30025518 11 www.national.com LM3686 Load Transient Response DC-DC (PWM Mode: 100mA to 350mA) Load Transient Response DC-DC (PFM Mode: 1mA to 150mA) 30025519 30025520 Load Transient Response LILO 50mA to 250mA Load Transient Response LDO 100mA to 250mA 30025521 30025522 www.national.com 12 LM3686 Operation Description DEVICE INFORMATION The LM3686 incorporates a high efficiency synchronous switching step-down DC-DC converter, a very low dropout linear regulator (LILO), and ultra low noise linear regulator. The DC-DC converter delivers a constant voltage from a single Li- Ion battery and input voltage rails from 2.7V to 5.5V to portable devices such as cell phones and PDAs. Using a voltage mode architecture with synchronous rectification, it has the ability to deliver up to 600 mA load current (when not powering the LILO) depending on the input voltage, output voltage, ambient temperature and the inductor chosen. The linear regulator delivers a constant voltage biased from VIN_LILO power input typically the output voltage of the DC-DC converter is used (post regulation) with a maximum load current of 350 mA. The other linear regulator delivers a constant voltage biased from VIN_LDO power input - with a maximum load current of 300 mA. Three enable pins allow the independent control of the three outputs. Shutdown mode turns off the device, offering the lowest current consumption (ISHUTDOWN = 2.5 µA typ). Besides the shutdown feature, for the DC-DC converter there are two more modes of operation depending on the current required: - PWM (Pulse Width Modulation), and - PFM (Pulse Frequency Modulation). The device operates in PWM mode at load current of approximately 80 mA or higher. Lighter load current cause the device to automatically switch into PFM for reduced current consumption (IQ_VBATT = 28 µA typ) and a longer battery life. Additional features include soft-start, startup mode of the linear regulator, under-voltage protection, current overload protection, and over-temperature protection. An internal reference generates a 1.8V biasing an internal resistive divider to create a reference voltage range from 0.7V to 1.8V (in 50 mV steps) for the LILO and the 0.5V reference used for the DC-DC converter. The ultra low noise linear regulator also has internal reference that generates a 1.8V biasing for a internal resistor divider. Thus, creating a reference voltage ranging from 1.5V to 3.3V The Under-voltage lockout feature enables the device to startup once VBATT has reached 2.65V typically and turns the device off if VBATT drops below 2.41V typically. Post Regulation Note: In the case that the DC-DC converter is switched off while the Linear Regulator is still enabled, the LILO can still support up to 50 mA. The linear regulator LILO is turned on via a small NMOS device supplied by VIN_LDO . The maximum current is 50 mA when this small NMOS is ON. If higher current > 50 mA is desired the following condition must be done: 1) EN_DC = HIGH When the condition is met, the LILO transitions to the large NMOS and can support up to 350 mA. DC-DC CONVERTER OPERATION During the first part of each switching cycle, the control block in the LM3686 turns on the internal PFET switch. This allows current to flow from the input VBATT through the switch pin SW and the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VBATT VOUT_DCDC) / L, by storing energy in the magnetic field. During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of (- VOUT_DCDC / L). The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. PWM Operation During PWM (Pulse Width Modulation) operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependency, feed forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the duty-cycle-comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. 30025509 FIGURE 4. Typical PWM Operation Internal Synchronous Rectification While in PWM mode, the DC-DC converter uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 13 www.national.com LM3686 Current Limiting A current limit feature allows the LM3686 to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1220mA (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold. This allows the inductor current more time to decay, thereby preventing runaway. PFM Operation At very light load, the DC-DC converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The NFET current reaches zero. B. The peak PMOS switch current drops below the IMODE level, (typically IMODE < 75 mA + VBATT / 55Ω ). During PFM operation, the DC-DC converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between ~0.2% and ~1.8% above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: IPFM = 112 mA + VBATT / 20Ω. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 6 ), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is 28µA (typ), which allows the part to achieve high efficiency under extremely light load conditions. If the load current should increase during PFM mode (see Figure 6) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixedfrequency PWM mode. When VBATT = 2.7V the part transitions from PWM to PFM mode at ~35 mA output current and from PFM to PWM mode at ~95 mA , when VBATT= 3.6V, PWM to PFM transition happens at ~42 mA and PFM to PWM transition happens at ~115 mA, when V BATT = 4.5V, PWM to PFM transition happens at ~60 mA and PFM to PWM transition happens at ~135 mA. 30025510 FIGURE 5. Typical PFM Operation 30025526 FIGURE 6. Operation in PFM Mode and Transfer to PWM Mode www.national.com 14 LM3686 Soft Start The DC-DC converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN_DCDC goes from logic low to logic high after VBATT reaches 2.7V. Soft start is implemented by increasing switch current limit in steps of 200 mA, 400 mA, 600 mA and 1220 mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Typical start-up times with a 10 µF output capacitor and 200 mA load is 350 µs and with 1 mA load is 200 µs. LINEAR REGULATOR OPERATION (LILO) In the typical post regulation application the power input voltage VIN_LILO for the linear regulator is generated by the DCDC converter. Using a buck converter to reduce the battery voltage to a lower input voltage for the linear regulator translates to higher efficiency and lower power dissipation. It's also possible to operate the linear regulator independent of the DC-DC converter output voltage either from VIN_LDO/ VBATT or from a different source (VIN_LILO) - (IOUT_LILO = 50 mA max in independent mode). An input capacitor of 1 µF at VIN_LILO is needed to be added if no other filter or bypass capacitor is present in the VIN_LILO path. Startup Mode If VIN_LILO > VOUT_LILO(NOM) + 250 mV the main regulator is active, offering a rated output current of 350 mA and supplied by VIN_LILO. (Large NMOS) If VIN_LILO < VOUT_LILO(NOM) + 150 mV the startup LILO is active, providing a reduced rated output current of 50 mA typical, supplied by VBATT. (Small NMOS) 30025533 FIGURE 7. Startup Sequence, VEN_DCDC = VEN_LILO = V EN_LDO= VBATT Current Limiting (LDO and LILO) The LM3686 incorporates also a current limit for the LDO and LILO to protect itself and external components during overload conditions at their outputs. In the event of a peak overcurrent condition at VOUT_LDO or VOUT_LILO the output current through the NFET pass device will be limited. 15 www.national.com LM3686 Application Selection It is strongly recommended to select the required components of LM3686 as described within the datasheet. If other components are selected, the device will not perform up to standard and electrical characteristics are not guaranteed. • • • • • IRIPPLE: average to peak inductor current IOUT_DCDCMAX: maximum load current (600 mA) VBATT: maximum input voltage in application L: minimum inductor value including worst case tolerances (30% drop can be considered for method 1) f: minimum switching frequency (2.55 MHz) Inductor Selection There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. The minimum value of inductance to guarantee good performance is 0.7 µH at ILIM (typ) dc current over the ambient temperature range. Shielded inductors radiate less noise and should be preferred. There are two methods to choose the inductor saturation current rating. METHOD 1 The saturation current should be greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as: ISAT > IOUT_DCDC_MAX + IRIPPLE where METHOD 2 A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum current limit of 1375 mA. A 1.0 µH inductor with a saturation current rating of at least 1375 mA is recommended for most applications. The inductor’s resistance should be less than 0.3Ω for good efficiency. Table 1 lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical applications, a toroidal or shielded- bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor, in the event that noise from low-cost bobbin models is unacceptable. TABLE 1. Suggested Inductors and their Suppliers Model BRL2518T1R0M MDT2520CR1R0M KSLI252010AG1R0 Vendor TAIYO YUDEN TOKO HITACHI METALS Dimensions LxWxH (mm) 2.5 X 1.8 X 1.2 2.5 X 2.0 X 1.0 2.5 X 2.0 X 1.0 DCR (max) 80 80 75 External Capacitors As common with most regulators, the LM3686 requires external capacitors to ensure stable operation. The LM3686 is specifically designed for portable applications requiring minimum board space and the smallest size components. These capacitors must be correctly selected for good performance. source. A ceramic capacitor’s low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The input current ripple can be calculated as: Input Capacitor Selection CIN_DC-DC A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as possible to the VBATT pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The minimum input capacitance to guarantee good performance is 2.2 µF at 3V dc bias; 1.5 µF at 5V dc bias including tolerances and over ambient temperature range. The input filter capacitor supplies current to the PFET switch of the LM3686 DC-DC converter in the first half of each cycle and reduces voltage ripple imposed on the input power www.national.com 16 CIN_LILO If the LILO is used as post regulation no additional capacitor is needed at VIN_LILO as the output filter capacitor of the DCDC converter is close by and therefore sufficient. In case of independent mode use, a 1.0 µF ceramic capacitor is recommended at VIN_LILO if no other filter capacitor is present in the VIN_LILO supply path. This capacitor must be LM3686 located a distance of not more than 1 cm from the VIN_LILO input pin and returned to QGND. CIN_LDO An input capacitor is required for stability. It is recommended to use a 1 µF ceramic capacitor and connected between the VIN_LDO and QGND. Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations is at the switching frequency of the part. COUT_LILO The linear regulator is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types X7R, Z5U, or Y5V) in the 2.2 µF range (up to 10 µF) and with an ESR between 3 mΩ to 300 mΩ is suitable as COUT_LIN in the LM3686 application circuit. This capacitor must be located a distance of not more than 1cm from the VOUT_LILO pin and returned to a clean analogue ground. It is also possible to use tantalum or film capacitors at the device output, VOUT_LILO but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics). COUT_LDO A ceramic capacitor in the 1 uF to 2.2 uF range, and with ESR between 5 mΩ to 500 mΩ, is suitable for the linear regulator. This output capacitor should be connected no more than 1 cm from VOUT_LDO and QGND Output Capacitor COUT_DCDC A ceramic output capacitor of 10 µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor selection process. The minimum output capacitance to guarantee good performance is 5.75 µF at 1.8V DC bias including tolerances and over ambient temperature range. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and can be calculated as: Voltage peak-to-peak ripple due to capacitance can be expressed as follow: Voltage peak-to-peak ripple due to ESR can be expressed as follow: VPP-ESR = (2*IRIPPLE) * RESR Because these two components are out of phase, the rms (root mean squared) value can be used to get an approximate value of peak-to-peak ripple. The peak-to-peak ripple voltage, rms value can be expressed as follow: 30025508 FIGURE 8. Graph Showing a Typical Variation In Capacitance vs. DC Bias TABLE 2. Suggested Capacitors and their Suppliers Capacitance / µF 10.0 4.7 2.2 1.0 Model C1608X5R0J106K C1608X5R0J475 C1608X5R0J225M C1005JB0J105KT Voltage Rating 6.3V 6.3V 6.3V 6.3V Vendor TDK TDK TDK TDK Type Ceramic, X5R Ceramic, X5R Ceramic, X5R Ceramic, X5R Case Size / Inch (mm) 0603 (1608) 0603 (1608) 0603 (1608) 0402 (1005) 17 www.national.com LM3686 Micro SMD Package Assembly And Use Use of the micro SMD package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section "Surface Mount Technology (SMD) Assembly Considerations". For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with micro SMD package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the soldermask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 12-bump package used for LM3686 has 300 micron solder balls and requires 275 micron pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should not exceed 183 micron, for a section approximately 183 micron long or longer, as a thermal relief. Then each trace should neck up or down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the LM3686 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A2, C1 and B3, because PGND, SGND, VBATT and VIN_LIN are typically connected to large copper planes, inadequate thermal relief can result in late or inadequate re-flow of these bumps. The micro SMD package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the micro SMD package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with frontside shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, micro SMD devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges. Board Layout Considerations PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. Good layout for the LM3686 can be implemented by following a few simple design rules below. Refer to Figure 10 for top layer board layout. 1. Place the LM3686, inductor and filter capacitor close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VBATT and PGND pin. Place the output capacitor of the linear regulator close to the output pin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor through the LM3686 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground through the LM3686 by the inductor to the output filter capacitor and then back through ground forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the LM3686 and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LM3686 by giving it a low impedance ground connection. Route SGND to the ground-plane by a separate trace. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. 5. Route noise sensitive traces, such as the voltage feedback path (FB_DCDC), away from noisy traces between the power components. The voltage feedback trace must remain close to the LM3686 circuit and should be direct but should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. 6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks and other noisy circuitry. Interference with noise sensitive circuitry in the system can be reduced through distance. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal plane; power to it is postregulated to reduce conducted noise, a good field of application for the on-chip low-dropout linear regulator. www.national.com 18 LM3686 Physical Dimensions inches (millimeters) unless otherwise noted 12–Bump (large) micro SMD, 0.5mm Pitch NS Package Number TLA12 Physical dimensions are as given: X1 = 2.49mm X2 = 1.74 mm X3 = 0.6 mm 19 www.national.com LM3686 Step-Down DC-DC Converter with Integrated Post Linear Regulators System and LowNoise Linear Regulator Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/AU Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero Solar Magic® Analog University® THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2008 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: support@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Technical Support Center Email: europe.support@nsc.com German Tel: +49 (0) 180 5010 771 English Tel: +44 (0) 870 850 4288 National Semiconductor Asia Pacific Technical Support Center Email: ap.support@nsc.com National Semiconductor Japan Technical Support Center Email: jpn.feedback@nsc.com