LMX2370SLBX

LMX2370/LMX2371/LMX2372 PLLatinum Dual Frequency Synthesizer for RF Personal Communications PRELIMINARY March 1999 LMX2370/LMX2371/LMX2372 PLLatinum™ Dual Frequency Synthesizer for RF Personal Communications LMX2370 LMX2371 LMX2372 2.5 GHz/1.2 GHz 2.0 GHz/1.2 GHz 1.2 GHz/1.2 GHz The LMX237X are available in a 24-pad chip scale (CSP) or a 20-pin TSSOP surface mount plastic package. Features n n n n n 2.7V–5.5V operation Ultra low current consumption Low phase detector noise floor Low voltage MICROWIRE™ interface (1.8V up to VCC) Low prescaler values 32/33 @ fIN ≤ 2.5 GHz 16/17 @ fIN ≤ 1.2 GHz 8/9 @ fIN ≤ 550 MHz Selectable charge pump current levels Selectable FastLock™ mode Enhanced ESD protection Small 24 pad chip scale package (3.5 x 4.5 x 1.0 mm) General Description The LMX237X family of monolithic, integrated dual frequency synthesizers, including prescalers, is designed to be used as a first and second local oscillator for dual mode or dual conversion transceivers. It is fabricated using National’s 0.5u ABiCV silicon BiCMOS process. The LMX237X contains two dual modulus prescalers. A 32/33 or a 16/17 prescaler can be selected for the 2.5 GHz and 2.0 GHz RF synthesizers with the 16/17 prescaler rated for input frequencies below 1.2 GHz. A 16/17 or an 8/9 prescaler can be selected for the 1.2 GHz RF synthesizers with the 8/9 prescaler rated for input frequencies below 550 MHz. Using a digital phase locked loop technique, the LMX237X can generate very stable, low noise control signals for UHF and VHF voltage controlled oscillators (VCO’s). Serial data is transferred into the LMX237X via a 1.8V three wire interface (Data, Enable, Clock) compatible with low voltage baseband processors. Supply voltage can range from 2.7V to 5.5V. The LMX237X family features very low current consumption typically: LMX2370 - 6.0 mA @ 3V, LMX2371 - 5.0 mA @ 3V, LMX2372 - 4.0 mA @ 3V. n n n n Applications n n n n Portable wireless communications (PCS/PCN, cordless) Dual mode cellular telephone systems Spread spectrum communication systems (CDMA) Cable TV tuners (CATV) Functional Block Diagram DS101026-1 FastLock™, PLLatinum™ and MICROWIRE™ are trademarks of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS101026 www.national.com Connection Diagrams TSSOP 20-Pin Package CSP 24-Pin Package DS101026-2 Top View Order Number LMX2370TM, LMX2370TMX, LMX2371TM, LMX2371TMX, LMX2372TM or LMX2372TMX See NS Package Number MTC20 DS101026-3 Top View Order Number LMX2370SLBX, LMX2371SLBX or LMX2372SLBX See NS Package Number SLB24A Pin Descriptions Pin No. 24-Pin CSP 24 20-Pin TSSOP 1 Pin Name VCC1 I/O — Description Power supply voltage input for RF analog and RF digital circuits. Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Power supply for Main charge pump. Must be ≥ VCC. Internal Main charge pump output. For connection to a loop filter for driving the input of an external VCO. Ground for Main digital circuitry. Main prescaler input. Small signal input from the VCO. Main prescaler complementary input. For single ended operation, a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Ground for Main analog circuitry. Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Ground for Aux digital, MICROWIRE, FoLD, and oscillator circuits. Multiplexed output of the Main/Aux programmable or reference dividers, Main/Auxiliary lock detect signals and Fastlock mode. CMOS output (see Programmable Modes in the Datasheet). High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge, into the 22-bit shift register. Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. Load enable. High impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). 2 3 4 5 6 2 3 4 5 6 Vp1 CPo1 GND fIN1 fIN1b — O — I I 7 8 10 11 7 8 9 10 GND OSCin GND Fo/LD — I — O 12 14 15 11 12 13 Clock Data LE I I I www.national.com 2 Pin Descriptions Pin No. 24-Pin CSP 16 20-Pin TSSOP 14 (Continued) Pin Name Vµc I/O — Description Power supply for MICROWIRE circuitry. Must be ≤ VCC. Typically connected to same supply level as µprocessor or baseband controller to enable programming at low voltages. Ground for Aux analog circuitry. Auxiliary prescaler input. Small signal input from the VCO. Ground for Aux digital, MICROWIRE, FoLD, and oscillator. Aux internal charge pump output. For connection to a loop filter for driving the input of an external VCO. Power supply for Aux charge pump. Must be ≥ VCC. Power supply voltage input for Aux analog, Aux digital, FoLD, and oscillator circuits. Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. No Connect 17 18 19 20 22 23 15 16 17 18 19 20 GND fIN2 GND CPo2 Vp2 VCC2 — I — O — — 1, 9, 13, 21 — NC — Block Diagram DS101026-4 3 www.national.com Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage −0.3V to 6.5V VCC1 −0.3V to 6.5V VCC2 Vp1 −0.3V to 6.5V Vp2 −0.3V to 6.5V Vµc −0.3V to 6.5V Voltage on any pin with −0.3V to VCC +0.3V GND = 0V (VI) −65˚C to +150˚C Storage Temperature Range (TS) +260˚C Lead Temperature (solder, 4 sec.) (TL) ESD - Human Body Model (Note 2) TBD Recommended Operating Conditions (Note 3) Power Supply Voltage VCC1 VCC2 VCC1–VCC2 Vp1 Vp2 Vµc Operating Temperature (TA) 2.7V to 5.5V 2.7V to 5.5V −0.2V to 0.2V VCC to 5.5V VCC to 5.5V 1.72V to VCC −40˚C to +85˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should only be done at ESD free workstations. Note 3: VCC is defined as VCC = VCC1 = VCC2. Electrical Characteristics GENERAL Symbol ICC Parameter Power Supply Current LMX2370 LMX2371 LMX2372 LMX2370 /71/72 ICC-PWDN fIN1 Power Down Current Main PLL Operating Frequency LMX2370 LMX2371 LMX2372 fIN2 ZfIN Main ZfIN Aux fφ PfIN1, PfIN2 Auxiliary PLL Operating Frequency Main PLL Input Impedance Aux Input Impedance Phase Detector Frequency RF Input Sensitivity (VCC = Vp = Vµc = 3.0V; −40˚C < TA < 85˚C except as specified). Value Conditions Main = On, Aux = On Main = On, Aux = On Main = On, Aux = On Aux Only EN_Main, EN_Aux = 0 P = 32/33 P = 16/17 P = 32/33 P = 16/17 P = 16/17 P = 8/9 P = 16/17 P = 8/9 RF On, fIN = 1800 MHz RF Off, fIN = 1800 MHz fIN = 120 MHz 2.7 ≤ VCC ≤ 3.6V 3.6 ≤ VCC ≤ 5.5V −15 −10 Value Min Typ 6 5 4 2 15 1.2 45 1.2 45 45 45 45 45 TBD TBD TBD 10 0 0 Max 8.5 7.5 6.0 3.25 50 2.5 1200 2.0 1200 1200 550 1200 550 Unit mA mA mA mA µA GHz MHz GHz MHz MHz MHz MHz MHz Ω Ω Ω MHz dBm dBm Unit MHz kΩ kΩ VCC 100 −100 VPP µA µA OSCILLATOR INPUT Symbol OSCin ZIN OSC VOSC IIH IIL Parameter Reference Oscillator Input Operating Frequency OSC Input Impedance Oscillator Input Sensitivity OSCin Input Current OSCin Input Current OSC On, Freq = 10 MHz OSC Off, Freq = 10 MHz OSCin VIH = VCC = 5.5V VIL = 0, VCC = 5.5V 0.5 Conditions Min 2 Typ Max 50 TBD TBD www.national.com 4 Electrical Characteristics CHARGE PUMP Symbol ICPo-source ICPo-sink ICPo-source ICPo-sink ICPo-TRI ICPo-sink vs ICPo-source ICPo vs VCPo ICPo vs TA Charge Pump TRI-STATE ® Current CP Sink vs Source Mismatch CP Current vs Voltage CP Current vs Temperature Parameter (VCC = Vp = Vµc = 3.0V; −40˚C < TA < 85˚C except as specified). (Continued) Value Conditions VCPo = Vp/2, ICPo_4X VCPo = Vp/2, ICPo_4X VCPo = Vp/2, ICPo_4X VCPo = Vp/2, ICPo_4X =0 =0 =1 =1 −2.5 Min Typ 1.0 −1.0 4.0 −4.0 0.1 3 8 8 Value Conditions Vµc = 1.72V to 5.5V Vµc = 1.72V to 5.5V VIH = Vµc = 5.5V VIL = 0, Vµc = 5.5V IOL = 1.0 mA, VEXT = 1.8V (Note 5) Min 0.8 Vµc 0.2 Vµc −1.0 −1.0 0.1 Value 1.0 1.0 0.4 Typ Max 2.5 10 15 Max Unit mA mA mA mA nA % % % Unit V V µA µA V Main and Auxiliary Charge Pump Output Current (Note 4) 0.5 ≤ VCPo ≤ Vp − 0.5, −40˚C < TA < 85˚C VCPo = Vp/2, TA = 25˚C 0.5 ≤ VCPo ≤ Vp − 0.5, TA = 25˚C VCPo = Vp/2, −40˚C < TA < 85˚C DIGITAL INTERFACE (DATA, CLOCK, LE) Symbol VIH VIL IIH IIL VOL Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Low-Level Output Current MICROWIRE TIMING Symbol tCS tCH tCWH tCWL tES tEW Parameter Data to Clock Setup Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Load Enable Setup Time Load Enable Pulse Width Conditions See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing Min 50 20 50 50 50 50 Typ Max Unit ns ns ns ns ns ns Note 4: Main and Auxiliary Charge Pump magnitude are controlled by Main_ICPo_4X and Aux_ICPo_4X bits respectively. Note 5: Lock Detect open drain output only pulled up to VEXT. Typically VEXT = VCC. 1.0 Functional Description The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer such as the National Semiconductor LMX2370/2371/2372, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R-counter to obtain a comparison reference frequency. This reference signal (fR) is then presented to the input of a phase/frequency detector and compared with the feedback signal (fN), which is obtained by dividing the VCO frequency down by way of the N-counter. The phase/frequency detector’s current source output pumps charge into the loop filter, which then integrates into the VCO’s control voltage. The function of the phase/frequency comparator is to adjust the control voltage presented to the VCO until the feedback signal frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency will be N times that of the comparison frequency, where N is the integer divide ratio. 1.1 REFERENCE OSCILLATOR INPUT The reference oscillator frequency for the Main and Auxiliary PLLs is provided from the external reference through the OSCin pin. OSCin can operate up to 50 MHz with input sensitivity of 0.5 VPP. The OSCin pin drives both the Main R-counter and the Auxiliary R-counter. The input has a VCC/2 input threshold that can be driven from an external CMOS or TTL logic gate. Typically, the OSCin is connected to the output of a crystal oscillator. 1.2 REFERENCE DIVIDERS (R-COUNTERS) The Main and Auxiliary R-counters are both clocked through the oscillator block in common. The maximum frequency is 50 MHz. Both R-counters are CMOS design and 15-bit in length with programmable divider ratio from 2 to 32,767. 5 www.national.com 1.0 Functional Description 1.3 PRESCALERS (Continued) The complimentary fIN and fINB inputs drive a differential-pair amplifier which feeds to the respective prescaler. The Main PLL complementary fIN1 and fIN1b inputs can be driven differentially, or the negative input can be AC coupled to ground through an external capacitor for single ended configuration. The Auxiliary PLL has the complimentary input AC coupled to ground through an internal 10 pF capacitor. The Auxilllary PLL complimentary input is not brought out to a pin, and is intended for single ended configuration only. The LMX237X has a dual modulus prescaler with 2 selectable modulo. For PLL’s rated at 2.5 GHz or 2.0 GHz a 32/33 or 16/17 prescaler is available. For PLL’s rated at 1.2 GHz a 16/17 or 8/9 can be chosen. Both Main and Auxiliary prescalers’ outputs drive the subsequent CMOS flip-flop chain comprising the programmable N feedback counters. The proper prescaler value must be chosen to in order not to exceed the maximum CMOS frequency. For fIN > 1.2 GHz, the 32/33 prescaler must be selected, similarly for fIN > 550 MHz, the prescaler value must be at least 16/17, and for fIN < 550 MHz, an 8/9 prescaler value is allowable. 1.4 FEEDBACK DIVIDERS (N-COUNTERS) The Main and Auxiliary N-counters are clocked by the output of Main and Aux prescalers respectively. The N-counter is composed of a 13-bit integer divider and a 5-bit swallow counter. Selecting a 32/33 prescaler provides a minimum continuous divider range from 992 to 262,143 while selecting a 16/17 or 8/9 prescaler value allows for continuous divider values between and 240 to 131,087 and 56 to 65,559 respectively. 1.5 PHASE/FREQUENCY DETECTORS The phase/frequency detectors are driven from their respective N- and R-counter outputs. The maximum frequency at the phase detector inputs is 10 MHz unless limited by the minimum continuous divide ratio of the dual-modulus prescaler. The phase detector output controls the charge pump. The polarity of the pump-up or pump-down control is programmed using Main_PD_POL or Aux_PD_POL, depending on whether Main or Auxiliary VCO characteristics is positive or negative. The phase detector also receives a feedback signal from the charge pump in order to eliminate dead zone. 1.6 CHARGE PUMPS The phase detector’s current source output pumps charge into an external loop filter, which then integrates into the VCO’s control voltage. The charge pump steers the charge pump output CPo to VP (pump-up) or Ground (pump-down). When locked, CPo is primarily in a TRI-STATE mode with small corrections. The charge pump output current magnitude can be selected as 1.0 mA or 4.0 mA by programming the Main_ICPo_4X or Aux_ICPo_4X bits. 1.7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed through the Microwire serial interface. The interface is comprised of three signal pins: clock, data and load enable (LE). The supply for the MICROWIRE circuitry is separate from the rest of the IC to allow for controller voltages down to 1.8V. Serial data is clocked into the 22-bit shift register upon the rising edge of clock. The MSB bit of data shifts first. The last two bits decode the internal register address. On the rising edge of LE, data stored in the shift register is loaded into one of the four latches according to the address bits. The synthesizer can be programmed even in power down state. A complete programming description is followed in Section 2.0. 1.8 MULTIFUNCTION OUTPUTS The LMX2370/LMX2371/LMX2372 FoLD output pin can be configured as the FastLock output or CMOS programmed output, analog lock detects as well as showing the internal block status such as the counter outputs. 1.8.1 Lock Detect Output An analog lock detect status generated from the phase detector is available on the Fo/LD output pin, if selected. The lock detect output goes high when the charge pump is inactive. It goes low when the charge pump is active during a comparison cycle. The lock detect signal output is an open drain configuration. When a PLL is in power down mode, the respective lock detect output is always high. 1.8.2 FastLock Outputs When configured as FastLock mode, the current can be increased 4x while maintaining loop stability by synchronously switching a parallel loop filter resistor to ground, resulting in a z2x change in loop bandwidth. The zero gain crossover point of the open loop gain, or the loop bandwidth is effectively shifted up in frequency by a factor of √4 = 2 during FastLock mode. For ω’ = 2ω, the phase margin during FastLock will also remain constant. The charge pump current is programmed via MICROWIRE interface. When the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error, an open drain NMOS on chip device (FoLD) switches in a second resistor element to ground. The user calculates the loop filter component values for the normal steady state considerations. The device configuration ensures that as long as a second resistor equal to the primary resistor value is wired in appropriately, the loop will lock faster without any additional stability considerations to account for. 1.9 POWER CONTROL Each PLL is individually power controlled by device power-down (PWDN) bits. The Main_PWDN and Aux_PWDN bits determine the state of power control. Activation of any PLL power-down condition results in the disabling of the respective N-counter and de-biasing of its respective fIN input (to a high impedance state). The R-counter functionality also becomes disabled under this condition. www.national.com 6 1.0 Functional Description (Continued) The reference oscillator input block is powered down when both Main_PWDN and Aux_PWDN bits are asserted. The OSCin pin reverts to a high impedance state when this condition exists. Power down forces the respective charge pump and phase comparator logic to a TRI-STATE condition. During the power down condition, both N- and R-counters are held at reset. Upon powering up, the N-counter resumes counting in “close” alignment with the R-counter. The maximum error is at most one prescaler cycle. The MICROWIRE interface remains active and it is capable of loading and latching in data during all of the power down modes. 2.0 Programming Description 2.1 MICROWIRE INTERFACE The LMX237X register set can be accessed through the MICROWIRE interface. A 22-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a 20-bit DATA[19:0] field and a 2-bit ADDRESS[1:0] field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data stored in the shift register is loaded into the addressed latch. MSB DATA[19:0] 21 2 1 LSB ADDRESS[1:0] 0 2.1.1 Registers’ Address Map When Load Enable (LE) is transitioned high, data is transferred from the 22-bit shift register into the appropriate latch depending on the state of the ADDRESS[1:0] bits. A multiplexing circuit decodes these address bits and writes the data field to the corresponding internal register. ADDRESS[1:0] FIELD 0 0 1 1 0 1 0 1 REGISTER ADDRESSED Aux_R Register Aux_N Register Main_R Register Main_N Register 7 www.national.com www.national.com SHIFT REGISTER BIT LOCATION 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Least Significant Bit 2 1 0 20 19 2.1.2 Registers’ Truth Table Most Significant Bit 21 2.0 Programming Description Data Field Aux_ CPo_ TRI Aux_R_CNTR[14:0] Aux_ R17 Aux_B_CNTR[12:0] Aux_ N17 Aux_ N16 Aux_ N15 Aux_ N14 Aux_ N13 Aux_ N12 Aux_ N11 Aux_ N10 Aux_ N9 Aux_ N8 Aux_ N7 Aux_ N6 Aux_ N5 Aux_ N4 Aux_ R16 Aux_ R15 Aux_ R14 Aux_ R13 Aux_ R12 Aux_ R11 Aux_ R10 Aux_ R9 Aux_ R8 Aux_ R7 Aux_ R6 Aux_ R5 Aux_ R4 Aux_ CPo_ 4X Aux_ PD_ POL Address Field Aux_R FoLD 1 FoLD 0 0 Aux_ R3 Aux_ R2 Aux_ R1 Aux_A_CNTR[4:0] Aux_ N3 Aux_ N2 Aux_ N1 Aux_ N0 0 Aux_ R0 0 Aux_ R19 P_ Aux Aux_ N18 Aux_ R18 (Continued) Aux_N 8 Main_R_CNTR[14:0] Main_ R18 P_ Main Main_B_CNTR[12:0] Main_ N18 Aux_ PWDN Aux_ N19 1 Main_R FoLD 3 FoLD 2 Main_ Main_ Main_ CPo_ CPo_ PD_ TRI 4X POL 1 0 Main_ R19 Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Main_A_CNTR[4:0] 1 1 Main_N Main_ PWDN Main_ N19 Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ Main_ N17 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 2.0 Programming Description (Continued) 2.2 PROGRAMMABLE REFERENCE DIVIDERS (Main and Aux R Counters) 2.2.1 Aux_R Register If the ADDRESS[1:0] field is set to 0 0, data is transferred from the 22-bit shift register into the Aux_R register when Load Enable (LE) signal goes high. The Aux_R register sets the Aux PLL’s 15-bit R-counter divide ratio and various programmable modes. The divide ratio is put into the Aux_R_CNTR[14:0] field. The divider ratio must be ≥ 2. For the description of bits Aux_R15–Aux_R19 see Section 2.4. Most Significant Bit 21 Aux_R FoLD 1 FoLD 0 20 19 Aux_R17 Aux_CPo_TRI 18 Aux_CPo_4X 17 Aux_R15 Aux_PD_POL 16 15 14 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 6 5 4 3 Least Significant Bit 2 1 0 Data Field Address Field Aux_R_CNTR[14:0] 0 Aux_R14 Aux_R13 Aux_R12 Aux_R11 Aux_R10 Aux_R9 Aux_R8 Aux_R7 Aux_R6 Aux_R5 Aux_R4 Aux_R3 Aux_R2 Aux_R1 Aux_R0 0 Aux_R19 Aux_R18 2.2.2 Main_R Register If the ADDRESS[1:0] field is set to 1 0, data is transferred from the 22-bit shift register into the Main_R register which sets the Main PLL’s 15-bit R-counter divide ratio when Load Enable (LE) signal goes high. The divide ratio is put into the Main_R_CNTR[14:0] field. The divider ratio must be ≥ 2. For the description of bits Main_R15–Main_R19 see Section 2.4. Most Significant Bit 21 Main_R FoLD 3 FoLD 2 20 19 Main_R17 Main_CPo_TRI 18 Main_CPo_4X 17 Main_R15 Main_PD_POL 16 15 14 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 6 5 4 3 Least Significant Bit 2 1 0 Aux_R16 Data Field Address Field Main_R_CNTR[14:0] 1 Main_R14 Main_R13 Main_R12 Main_R11 Main_R10 Main_R9 Main_R8 Main_R7 Main_R6 Main_R5 Main_R4 Main_R3 Main_R2 Main_R1 Main_R0 0 Main_R19 Main_R18 2.2.3 Reference Divide Ratio (Main and Auxiliary R-Counters) If the ADDRESS[1:0] field is set to 0 0 or 1 0 (00 for Aux and 10 for Main) data is transferred MSB first from the 22-bit shift register into a latch which sets the respective 15-bit R-counter. Serial data format is shown below. Main_R_CNTR[14:0] or Aux_R_CNTR[14:0] Divide Ratio 2 3 R14 0 0 R13 0 0 R12 0 0 R11 0 0 R10 0 0 R9 0 0 R8 0 0 R7 0 0 R6 0 0 R5 0 0 R4 0 0 R3 0 0 R2 0 0 R1 1 1 R0 0 1 • 32,767 • 1 Main_R16 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 Note: R-counter divide ratio must be from 2 to 32,767. 2.3 PROGRAMMABLE FEEDBACK [N] DIVIDERS 2.3.1 Aux_N Register If the ADDRESS[1:0] field is set to 0 1, data is transferred from the 22-bit shift register into the Aux_N register which sets the Auxiliary PLL’s 18-bit N-counter, prescaler value and power-down bit. The 18-bit N-counter consists of a 5-bit swallow counter, Aux_A_CNTR[4:0], and a 13-bit programmable counter, Aux_B_CNTR[12:0]. Serial data format is shown below. 9 www.national.com 2.0 Programming Description Most Significant Bit 21 Aux_N19 Aux_PWDN Aux_N 20 19 18 17 16 15 14 (Continued) Least Significant Bit 6 5 4 3 2 1 0 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 Data Field P_Aux Address Field Aux_B_CNTR[12:0] Aux_A_CNTR[4:0] 0 1 Aux_N18 Aux_N17 Aux_N16 Aux_N15 Aux_N14 Aux_N13 Aux_N12 Aux_N11 Aux_N10 Aux_N9 Aux_N8 Aux_N7 Aux_N6 Aux_N5 Aux_N4 Aux_N3 Aux_N2 Aux_N1 3 2.3.2 Main_N Register If the ADDRESS[1:0] field is set to 1 1, data is transferred from the 22-bit shift register into the Main_N register which sets the Main PLL’s 18-bit N-counter, prescaler value and power-down bit. The 18-bit N-counter consists of a 5-bit swallow counter, Main_A_CNTR[4:0], and a 13-bit programmable counter, Main_B_CNTR[12:0]. Serial data format is shown below. Most Significant Bit 21 Main_N19 Main_PWDN Main_N 20 19 18 17 16 15 14 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 6 5 4 Data Field P_Main Least Significant Bit 2 1 0 Aux_N0 Address Field Main_B_CNTR[12:0] Main_A_CNTR[4:0] 1 1 Main_N18 Main_N17 Main_N16 Main_N15 Main_N14 Main_N13 Main_N12 Main_N11 Main_N10 Main_N9 Main_N8 Main_N7 Main_N6 Main_N5 Main_N4 Main_N3 Main_N2 Main_N1 N8 0 0 2.3.3 Feedback Divide Ratio (Main B Counter, Auxiliary B Counter) Main_B_CNTR[12:0] or Aux_B_CNTR[12:0] Divide Ratio 3 4 N17 0 0 N16 0 0 N15 0 0 N14 0 0 N13 0 0 N12 0 0 N11 0 0 N10 0 0 N9 0 0 N7 0 1 N6 1 0 N5 1 1 • 8,191 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 Main_N0 • 1 • 1 • 1 Note: B-counter divide ratio must be ≥ 3. 2.3.4 Swallow Counter Divide Ratio (Main A Counter, Auxiliary A Counter) Main_A_CNTR[4:0] or Aux_A_CNTR[4:0] Divide Ratio 0 1 Main_N4 0 0 Main_N3 0 0 Main_N2 0 0 Main_N1 0 0 Main_N0 0 1 • 31 Notes: A < P, B > A. • 1 • 1 • 1 • 1 • 1 www.national.com 10 2.0 Programming Description 2.3.5 PLL Prescaler Select (P_Aux, P_Main) (Continued) The LMX2370, LMX2371 and LMX2372 contain two dual modulus prescalers. A 32/33 or a 16/17 prescaler can be selected for the 2.5 GHz and 2.0 GHz RF synthesizers in the LMX2370 and LMX2371 respectively. The 16/17 prescaler is only rated for input frequencies below 1.2 GHz. A 16/17 or an 8/9 prescaler can be selected for the both 1.2 GHz synthesizers on the LMX2372 as well as the 1.2 GHz synthesizers on the LMX2370 and LMX2371. The 8/9 prescaler is only rated for input frequencies below 550 MHz. Prescaler Value P_Main, (Main_N18) or P_Aux (Aux_N18) 0 1 2.5 GHz PLL 16/17 32/33 2.0 GHz PLL 16/17 32/33 Allowable Prescaler Values PLL Input Frequency fIN > 1.2 GHz 550 < fIN < 1200 MHz fIN < 550 MHz 2.3.5.1 Pulse Swallow Function fVCO = [(P x B) + A] x fOSC/R fVCO: B: A: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of binary 13-bit programmable counter (3 to 8191) Preset divide ratio of binary 5-bit swallow counter 0 ≤ A ≤ 31 {P = 32} 0 ≤ A ≤ 15 {P = 16} 0 ≤ A ≤ 7 {P = 8} A≤B Output frequency of the external reference frequency oscillator Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) Preset modulus of dual modulus prescaler (P = 8, 16, or 32) 2.5 GHz PLL 32/33 16/17 or 32/33 16/17 or 32/33 2.0 GHz PLL 32/33 16/17 or 32/33 16/17 or 32/33 1.2 GHz PLL NA 16/17 8/9 or 16/17 1.2 GHz PLL 8/9 16/17 fOSC: R: P: 2.3.6 PLL Power Down Control (Aux_PWDN, Main_PWDN) The Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) bits are used to power down either the Main or Auxiliary PLL’s charge pump portion, or the entire PLL block depending on the setting of the respective charge pump TRI-STATE bit (Aux_CPo_TRI or Main_CPo_TRI) in the R_CNTR register. The power-down mechanism is described below. The R and N counters for each respective PLL are disabled and held at reset during the synchronous and asynchronous power down modes. This will allow a smooth acquisition of the Main RF signal when the oscillator input buffer is still active (Auxiliary loop powered up) and vice versa. Upon powering up, both R and N counters will start at the “zero” state, and the relationship between R and N will not be random. Synchronous Power Down Mode One of the PLL loops can be synchronously powered down by first setting the respective loop’s TRI-STATE mode bit LOW (R17 = 0) and then asserting its power down mode bit (N19 = 1). The power down function is gated by the charge pump. Once the power down program bits Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) and TRI-STATE bits Aux_CPo_TRI (Aux_R17) or Main_CPo_TRI (Main_R17) are loaded, the part will go into power down mode upon the completion of a charge pump pulse event. Asynchronous Power Down Mode One of the PLL loops can be asynchronously powered down by first setting the respective loop’s TRI-STATE mode bit HI (R17 = 1) and then asserting its power down mode bit (N19 = 1). The power down function is NOT gated by the charge pump. Once the power down program bits Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) and its respective TRI-STATE bit Aux_CPo_TRI (Aux_R17) or Main_CPo_TRI (Main_R17) are loaded, the part will go into power down mode immediately. 11 www.national.com 2.0 Programming Description 2.3.7 Power Down Mode Table Main PLL Active Active Powered Down Powered Down Auxiliary PLL Active Powered Down Active Powered Down (Continued) Main Counters ON ON OFF OFF Auxiliary Counters ON OFF ON OFF OSCin Buffer ON ON ON OFF 2.4 PROGRAMMABLE MODES Several modes of operation can be programmed with bits R15–R19 including the phase detector polarity, charge pump magnitude, charge pump TRI-STATE and the output of the Fo/LD pin. The programmable modes are shown in Table 1. Truth table for the programmable modes and Fo/LD output are shown in Table 2 and Table 3. 2.4.1 Programmable Modes Table R19 R18 R17 Charge Pump TRI-STATE Aux_CPo_TRI Main_CPo_TRI R16 Charge Pump Magnitude Aux_CPo_4X Main_CPo_4X R15 Phase Detector Polarity Aux_PD_POL Main_PD_POL Address[1:0] fOUT/Lock Detect FoLD 1 FoLD 3 FoLD 0 FoLD 2 00 10 2.4.2 Mode Select Truth Table CPo_TRI (Note 6) 0 1 Normal Operation TRI-STATE CPo_4X (Note 7) 1X Current 4X Current PD_POL (Note 8) LOW HIGH Note 6: Both synchronous and asynchronous power down modes are available with the LMX237X family to be able to adapt to different types of applications. The MICROWIRE control register remains active and capable of loading and latching in data during all of the powerdown modes. Note 7: ICPo (charge pump current magnitude) is dependent on Vp. The ICPo LOW current state = 1/4 x ICPo HIGH current. Note 8: See Section 2.4.3 2.4.3 Phase Detector Polarity (Aux_PD_POL, Main_PD_POL) Depending upon VCO characteristics, the Aux_PD_POL (Aux_R15) and Main_PD_POL (Main_R15) bits should be set accordingly: When VCO characteristics are positive like (1), R15 should be set HIGH; When VCO characteristics are negative like (2), R15 should be set LOW. VCO CHARACTERISTICS DS101026-5 www.national.com 12 2.0 Programming Description 2.4.4 The FoLD Output Truth Table Main R[18] 0 0 1 1 X X X X 0 0 1 1 Aux R[18] 0 1 0 1 0 0 1 1 0 1 0 1 Main R[19] 0 0 0 0 0 1 0 1 1 1 1 1 Aux R[19] 0 0 0 0 1 0 1 0 1 1 1 1 (Continued) Fo/LD Output State Disabled Aux Lock Detect (Note 9) Main Lock Detect (Note 9) Main/Aux Lock Detect (Note 9) Aux Reference Divider Output Main Reference Divider Output Aux Programmable Divider Output Main Programmable Divider Output FastLock Output. Open Drain Output (Note 10) Reset Aux R and N Counters and TRI-STATE Aux Charge Pump (Note 11) Reset Main R and N Counters and TRI-STATE Main Charge Pump (Note 11) Reset All Four Counters and TRI-STATE both Charge Pumps (Note 11) X - don’t care condition Note 9: Open drain lock detect output is provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pin is HIGH, with narrow pulses LOW. In the Main/Aux lock detect mode a locked condition is indicated when Main and Aux are both locked. Note 10: The FastLock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during FastLock operation. Activation of FastLock occurs whenever the Main loop’s ICPo magnitude bit R[16] is selected HI while the R[18] and R[19] mode bits are set. Note 11: Aux and Main PLLs can be reset independently from each other by using the R[18] and R[19] bits. The Aux Counter Reset mode resets Aux PLL’s R and N counters and brings Aux charge pump output to TRI-STATE condition. The Main Counter Reset mode resets Main PLL’s R and N counters and brings Main charge pump output to a TRI-STATE condition. The Aux and Main Counter Reset modes reset all counters and bring both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset bits, the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) 2.5 Serial Data Input Timing Serial Data Input Timing DS101026-6 NOTES: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V. 13 www.national.com 2.0 Programming Description (Continued) 2.6 Typical Lock Detect Timing Typical Lock Detect Timing DS101026-7 www.national.com 14 Physical Dimensions inches (millimeters) unless otherwise noted Thin Shrink Small Outline (TSSOP) Package Order Number LMX2370TM, LMX2371TM or LMX2372TM *For Tape and Reel (2500 units per reel) Order Number LMX2370TMX, LMX2371TMX or LMX2372TMX NS Package Number MTC20 15 www.national.com LMX2370/LMX2371/LMX2372 PLLatinum Dual Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Chip Scale Package For Tape and Reel (2500 Units Per Reel) Order Numbers: LMX2370SLBX, LMX2371SLBX, LMX2372SLBX NS Package Number SLB24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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