MM54C195N

MM54C195 MM74C195 4-Bit Registers February 1988 MM54C195 MM74C195 4-Bit Registers General Description The MM54C195 MM74C195 CMOS 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear The following two modes of operation are possible Parallel Load Shift in direction QA towards QD Parallel loading is accomplished by applying the four bits of data and taking the shift load control of input low The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input During parallel loading serial data flow is inhibited Serial shifting is accomplished synchronously when the shift load control input is high Serial data for this mode is entered at the J-K inputs These inputs allow the first stage to perform as a J-K D or T-type flip flop as shown in the truth table Features Y Medium speed operation Y Y Y Y Y Y Y Y Y Y Y High noise immunity Low power Tenth power TTL compatible Supply voltage range Synchronous parallel load Parallel inputs and outputs from each flip-flop Direct overriding clear J and K inputs to first stage Complementary outputs from last stage Positive-edge triggered clocking Diode clamped inputs to protect against static charge 8 5 MHz (typ ) with 10V supply and 50 pF load 0 45 VCC (typ ) 100 nW (typ ) Drive 2 LPTTL loads 3V to 15V Applications Y Y Y Y Automotive Data terminals Instrumentation Medical electronics Y Y Y Y Alarm systems Remote metering Industrial electronics Computers Schematic and Connection Diagrams Pin 8 to GND Pin 16 to VCC TL F 5902 – 1 Dual-In-Line Package TL F 5902 – 2 Top View Order Number MM54C195 or MM74C195 C1995 National Semiconductor Corporation TL F 5902 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at any Pin Operating Temperature Range MM54C195 MM74C195 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (Soldering 10 sec ) b 65 C to a 150 C 700 mW 500 mW 3V to 15V 18V 260 C DC Electrical Characteristics Min Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Supply Current Parameter Max limits apply across temperature range unless otherwise noted Conditions Min Typ Max Units VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 15V VCC e 15V VCC e 15V 35 80 15 20 45 90 05 10 0 005 b1 0 b 0 005 V V V V V V V V mA mA 300 mA 10 0 05 CMOS LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) VOUT(0) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V IO e b360mA 74C VCC e 4 75V IO e b360mA 54C VCC e 4 5V IO e 360mA 74C VCC e 4 75V IO e 360mA 24 24 04 04 VCC b 1 5 VCC b 1 5 08 08 V V V V V V V V OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current Output Source Current Output Sink Current Output Sink Current VCC e 5V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 10V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 5V VIN(1) e 5V TA e 25 C VOUT e VCC VCC e 10V VIN(1) e 10V TA e 25 C VOUT e VCC b 1 75 b8 0 mA mA mA mA 1 75 80 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation 2 AC Electrical Characteristics Symbol tpd tpd tS tS tH tW tW tr tf fMAX CIN CPD Parameter TA e 25 C CL e 50 pF unless otherwise noted Conditions VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V (Note 2) (Note 3) 50 20 20 55 30 85 50 100 Min Typ 150 75 150 50 80 35 110 60 b 10 b5 0 Max 300 130 300 130 200 70 150 90 0 0 200 100 130 60 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms MHz MHz pF pF Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clear to Q or Q Time Prior to Clock Pulse that Data must be Present Time Prior to Clock Pulse that Shift Load must be Present Time After Clock Pulse that Data must be Held Minimum Clear Pulse Width (tWL e tWH) Minimum Clear Pulse Width Maximum Clock Rise and Fall Time Maximum Input Clock Frequency Input Capacitance Power Dissipation Capacitance 100 50 90 40 AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note AN-90 Truth Table Inputs AT tn J L L H H K H L H L QA QAn L H QAn Outputs AT tn a 1 QB QAn QAn QAn QAn QC QBn QBn QBn QBn QD QCn QCn QCn QCn QD QCn QCn QCn QCn Guaranteed Noise Margin as a Function of VCC Note H e High Level L e Low Level tn e bit time before clock pulse tn a 1 e bit time after clock pulse QAn e State of QA at tn TL F 5902 – 3 3 Switching Time Waveforms CMOS to CMOS TTL to CMOS TL F 5902 – 4 TL F 5902 – 5 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C195J or MM74C195J NS Package Number J16A 5 MM54C195 MM74C195 4-Bit Registers Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C195N or MM74C195N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 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