MM54HC195J

MM54HC195 MM74HC195 4-Bit Parallel Shift Register November 1995 MM54HC195 MM74HC195 4-Bit Parallel Shift Register General Description The MM54HC195 MM74HC195 is a high speed 4-bit SHIFT REGISTER utilizes advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads at LS type speeds This shift register features parallel inputs parallel outputs JK serial inputs SHIFT LOAD control input and a direct overriding CLEAR This shift register can operate in two modes PARALLEL LOAD SHIFT from QA towards QD Parallel loading is accomplished by applying the four bits of data and taking the SHIFT LOAD control input low The data is loaded into the associated flip flops and appears at the outputs after the positive transition of the clock input During parallel loading serial data flow is inhibited Serial shifting occurs synchronously when the SHIFT LOAD control input is high Serial data for this mode is entered at the J-K inputs These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truth table The 54HC 74HC logic family is functionally as well as pinout compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Y Y Y Y Y Typical operating frequency 45 MHz Typical propagation delay 16 ns (clock to Q) Wide operating supply voltage range 2 – 6V Low input current 1 mA maximum Low quiescent current 80 mA maximum (74HC Series) Fanout of 10 LS-TTL loads Connection Diagram Dual-In-Line Package TL F 5324 – 1 Top View Order Number MM54HC195 or MM74HC195 Function Table Inputs Clear Shift Clock Load L H H H H H H X L H H H H H X Serial J X X X L L H H K X X X H L H L Parallel ABCD X a X X X X X X b X X X X X X c X X X X X QA Outputs QB QC QD L d QD0 QCn QCn QCn QCn QD H d QD0 QCn QCn QCn QCn H e high level (steady state) L e low level (steady state) X e irrelevant (any input including transitions) e transition from low to high level a b c d e the level of steady-state input at inputs A B C or D respectively QA0 QB0 QC0 QD0 e the level of QA QB QC or QD respectively before the indicated steady-state input conditions were established QAn QBn QCn e the level of QA QB QC respectively before the most-recent transition of the clock u u L u u u u XL L L da b c X QA0 QB0 QC0 X QA0 QA0 QBn X L QAn QBn X H QAn QBn X QAn QAn QBn C1995 National Semiconductor Corporation TL F 5324 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Min Supply Voltage VCC DC Input or Output Voltage VIN VOUT Operating Temp Range (TA) MM HC MM HC Input Rise or Fall Times VCC e V tr tf VCC e V VCC e V b b If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 7 0V Supply Voltage (VCC) b 1 5 to VCC a 1 5V DC Input Voltage (VIN) b 0 5 to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C Max VCC Units V V a a C C ns ns ns DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V VIN e VIH or VIL lIOUTl s20 mA 2 0V 4 5V 6 0V 4 5V 6 0V 2 0V 4 5V 6 0V 4 5V 6 0V 6 0V 6 0V 20 45 60 42 57 0 0 0 02 02 TA e 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 15 3 15 42 05 1 35 18 19 44 59 3 98 5 48 01 01 01 0 26 0 26 g0 1 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits 15 3 15 42 05 1 35 18 19 44 59 3 84 5 34 01 01 01 0 33 0 33 g1 0 15 3 15 42 05 1 35 18 19 44 59 37 52 01 01 01 04 04 g1 0 V V V V V V V V V V V V V V V V mA mA VIL VOH VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VIN e VCC or GND IOUT e 0 mA 80 80 160 Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics VCC e 5V Symbol fMAX tPHL tPLH tPHL tREM tREM tS tS tW tH Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q Maximum Propagation Delay Reset to Q TA e 25 C CL e 15 pF tr e tf e 6 ns Conditions Typ 45 14 16 Guaranteed Limit 30 24 25 0 5 20 20 16 0 Units MHz ns ns ns ns ns ns ns ns Minimum Removal Time Shift Load to Clock Minimum Removal Time Reset Inactive to Clock Minimum Setup Time (A B C D J K to Clock) Minimum Setup Time Shift Load to Clock Minimum Pulse Width Clock or Reset Minimum Hold Time any Input except Shift Load tr e tf e 6 ns (unless otherwise specified) TA e 25 C Typ 74HC TA eb40 to 85 C 5 24 28 189 38 32 183 37 31 95 19 16 0 0 0 5 5 5 125 25 21 125 25 21 0 0 0 100 20 18 1000 500 400 AC Electrical Characteristics CL e 50 pF Symbol fMAX Parameter Maximum Operating Frequency Maximum Propagation Delay Reset to Q or Q Maximum Propagation Delay Clock to Q or Q Maximum Output Rise and Fall Time Minimum Removal Time Shift Load to Clock Minimum Removal Time Reset Inactive to Clock Minimum Setup Time (A B C D J K to Clock) Minimum Setup Time Shift Load to Clock Minimum Hold Time any Input except Shift Load Minimum Pulse Width Clock or Reset Maximum Input Rise and Fall Time Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 54HC TA eb55 to 125 C 4 20 24 224 45 38 216 43 37 110 22 19 0 0 0 5 5 5 150 30 25 150 30 25 0 0 0 120 24 20 1000 500 400 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF Guaranteed Limits 6 30 35 150 30 26 145 29 25 75 15 13 0 0 0 5 5 5 100 20 17 100 20 17 10 45 50 70 15 12 70 15 12 30 8 7 b2 b2 b2 tPHL tPHL tPLH tTHL tTLH tREM tREM tS tS tH b 10 b2 b2 0 0 0 80 16 14 1000 500 400 tW 30 10 9 tr tf CPD CIN 100 5 10 10 10 pF Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3 Logic and Timing Diagrams TL F 5324 – 2 TL F 5324 – 3 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC195J or MM74HC195J NS Package Number J16A 5 MM54HC195 MM74HC195 4-Bit Parallel Shift Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM74HC195N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the 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81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications