MM54HC123A

MM54HC123A MM74HC123A Dual Retriggerable Monostable Multivibrator January 1988 MM54HC123A MM74HC123A Dual Retriggerable Monostable Multivibrator General Description The MM54 74HC123A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits Each multivibrator features both a negative A and a positive B transition triggered input either of which can be used as an inhibit input Also included is a clear input that when taken low resets the one shot The ’HC123 can be triggered on the positive transition of the clear while A is held low and B is held high The ’HC123A is retriggerable That is it may be triggered repeatedly while their outputs are generating a pulse and the pulse will be extended Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques The output pulse equation is simply PW e (REXT) (CEXT) where PW is in seconds R is in ohms and C is in farads All inputs are protected from damage due to static discharge by diodes to VCC and ground Features Y Y Y Y Y Y Y Y Y Typical propagation delay 25 ns Wide power supply range 2V – 6V Low quiescent current 80 mA maximum (74HC Series) Low input current 1 mA maximum Fanout of 10 LS-TTL loads Simple pulse width formula T e RC Wide pulse range 400 ns to % (typ) Part to part variation g 5% (typ) Schmitt Trigger A B inputs enable infinite signal input rise and fall times Connection Diagram Dual-In-Line Package Timing Component Note Pin 6 and Pin 14 must be hard-wired to GND TL F 5206 – 2 TL F 5206 – 1 Top View Order Number MM54HC123A or MM74HC123A Truth Table Inputs Clear L X X H H A X H X L B X X L Q L L L Outputs Q H H H H e High Level L e Low Level ue ve Transition from Low to High Transition from High to Low e One High Level Pulse e One Low Level Pulse u H H X e Irrelevant v L u C1995 National Semiconductor Corporation TL F 5206 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Min Supply Voltage VCC DC Input or Output Voltage VIN VOUT Operating Temp Range (TA) MM HC MM HC Input Rise or Fall Times (Clear Input) VCC e V tr tf VCC e V VCC e V b b If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5V to a 7 0V Supply Voltage (VCC) b 1 5V to VCC a 1 5V DC Input Voltage (VIN) b 0 5V to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 C Max VCC Units V V a a C C ns ns ns DC Electrical Characteristics (Note 4) Symbol VIH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s mA Conditions VCC V V V V V V V V V V V V V V V V V V V V V V g g g TA e 25 C Typ 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA Guaranteed Limits VIL VOH VIN e VIH or VIL lIOUTl s mA lIOUTl s mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s mA VIN e VIH or VIL lIOUTl s mA lIOUTl s mA IIN IIN ICC ICC Maximum Input Current Pins Maximum Input Current all other pins Maximum Quiescent Supply Current standby Maximum Active Supply Current per monostable VIN e VCC or GND VIN e VCC or GND VIN e VCC or GND IOUT e mA VIN e VCC or GND R CEXT e VCC g g g Note 1 Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation Temperature Derating Plastic ‘‘N’’ Package b 12mW C from 65 C to 85 C Ceramic ‘‘J’’ Package b 12mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst-case output voltages (VOH VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst-case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst-case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used 2 AC Electrical Characteristics VCC e 5V Symbol tPLH tPHL tPHL tPLH tW tREM tWQ MIN tWQ Parameter Maximum Trigger Propagation Delay A B or Clear to Q Maximum Trigger Propagation Delay A B or Clear to Q Maximum Propagation Delay Clear to Q Maximum Propagation Delay Clear to Q Minimum Pulse Width A B or Clear Minimum Clear Removal Time Minimum Output Pulse Width Output Pulse Width TA e 25 C CL e 15 pF tr e tf e 6 ns Conditions Typ Limit Units ns ns ns ns ns ns CEXT e pF REXT e kX CEXT e REXT e pF kX ns ms AC Electrical Characteristics CL e 50 pF tr e tf e 6 ns (unless otherwise specified) Symbol tPLH Parameter Maximum Trigger Propagation Delay A B or Clear to Q Maximum Trigger Propagation Delay A B or Clear to Q Maximum Propagation Delay Clear to Q Maximum Propagation Delay Clear to Q Minimum Pulse Width A B Clear Minimum Clear Removal Time Conditions VCC V V V V V V V V V V V V V V V V V V V V V CEXT e pF REXT e kX REXT e kX VCC e V CEXT e REXT e mF kX Min Max V V V V V TA e 25 C Typ 74HC 54HC TA eb40 to 85 C TA eb55 to 125 C Units Guaranteed Limits ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ms ms pF pF Note pF tPHL tPHL tPLH tW tREM tTLH tTHL Maximum Output Rise and Fall Time tWQ MIN Minimum Output Pulse Width Output Pulse Width Maximum Input Capacitance Pins Maximum Input Capacitance other inputs Power Dissipation Capacitance tWQ CIN CIN CPD Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3 Logic Diagram TL F 5206 – 5 Theory of Operation TL F 5206 – 6 j POSITIVE EDGE TRIGGER k NEGATIVE EDGE TRIGGER l POSITIVE EDGE TRIGGER m POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING) n RESET PULSE SHORTENING o CLEAR TRIGGER FIGURE 1 TRIGGER OPERATION As shown in Figure 1 and the logic diagram before an input trigger occurs the one shot is in the quiescent state with the Q output low and the timing capacitor CEXT completely charged to VCC When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trigger is recognized which turns on comparator C1 and Nchannel transistor N1 j At the same time the output latch is set With transistor N1 on the capacitor CEXT rapidly discharges toward GND until VREF1 is reached At this point the output of comparator C1 changes state and transistor N1 turns off Comparator C1 then turns off while at the same time comparator C2 turns on With transistor N1 off the capacitor CEXT begins to charge through the timing re- 4 sistor REXT toward VCC When the voltage across CEXT equals VREF2 comparator C2 changes state causing the output latch to reset (Q goes low) while at the same time disabling comparator C2 This ends the timing cycle with the monostable in the quiescent state waiting for the next trigger A valid trigger is also recognized when trigger input B goes from GND to VCC (while input A is at GND and input clear is at VCC k ) The ’HC123A can also be triggered when clear goes from GND to VCC (while A is at GND and B is at VCC o ) It should be noted that in the quiescent state CEXT is fully charged to VCC causing the current through resistor REXT to be zero Both comparators are ‘‘off’’ with the total device current due only to reverse junction leakages An added feature of the ’HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage Thus propagation delay from trigger to Q is independent of the value of CEXT REXT or the duty cycle of the input waveform RETRIGGER OPERATION The ’HC123A is retriggered if a valid trigger occurs l followed by another trigger m before the Q output has returned to the quiescent (zero) state Any retrigger after the timing node voltage at the R CEXT pin has begun to rise from VREF1 but has not yet reached VREF2 will cause an increase in output pulse width T When a valid retrigger is initiated m the voltage at the R CEXT pin will again drop to VREF1 before progressing along the RC charging curve toward VCC The Q output will remain high until time T after the last valid retrigger Because the trigger-control circuit flip-flop resets shortly after CX has discharged to the reference voltage of the lower reference circuit the minimum retrigger time trr is a function of internal propagation delays and the discharge time of CX 187 565 a (0 256 VCC) CX a VCC b 0 7 2 VCC b 0 7 Another removal retrigger time occurs when a short clear pulse is used Upon receipt of a clear the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger This time is dependent on the capacitor used and is approximately trr 20 a trr e 196 a 640 522 a (0 3 VCC) CX a ns VCC b 0 7 (VCC b 0 7)2 RESET OPERATION These one shots may be reset during the generation of the output pulse In the reset mode of operation an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to VCC by turning on transistor Q1 n When the voltage on the capacitor reaches VREF2 the reset latch will clear and then be ready to accept another pulse If the clear input is held low any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change Since the Q output is reset when an input low level is detected on the Clear input the output pulse T can be made significantly shorter than the minimum pulse width specification Typical 1ms Pulse Width Variation vs Supply Typical Output Pulse Width vs Timing Components Typical Distribution of Output Pulse Width Part to Part TL F 5206–7 TL F 5206 – 8 TL F 5206 – 9 Minimum REXT vs Supply Voltage Typical 1ms Pulse Width Variation vs Temperature TL F 5206 – 10 TL F 5206 – 11 Note R and C are not subjected to temperature The C is polypropylene 5 MM54HC123A MM74HC123A Dual Retriggerable Monostable Multivibrator Physical Dimensions inches (millimeters) Dual-In-Line Package (J) Order Number MM54HC123AJ or MM74HC123AJ NS Package Number J16A Dual-In-Line Package (N) Order Number MM74HC123AN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be 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the right at any time without notice to change said circuitry and specifications