MM74C74J

MM54C74 MM74C74 Dual D Flip-Flop February 1988 MM54C74 MM74C74 Dual D Flip-Flop General Description The MM54C74 MM74C74 dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors Each flipflop has independent data preset clear and clock inputs and Q and Q outputs The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse Preset or clear is independent of the clock and accomplished by a low level at the preset or clear input Y Y Low power Medium speed operation 50 nW (typ ) 10 MHz (typ ) with 10V supply Applications Y Y Y Y Y Features Y Y Y Supply voltage range Tenth power TTL compatible High noise immunity 3V to 15V Drive 2 LPT2L loads 0 45 VCC (typ ) Y Y Y Automotive Data terminals Instrumentation Medical electronics Alarm system Industrial electronics Remote metering Computers Logic Diagram TL F 5885 – 1 Truth Table Preset 0 0 1 1 Clear 0 1 0 1 Qn 0 1 0 Qn Qn 0 0 1 Qn Connection Diagram Dual-In-Line Package No change in output from previous state Order Number MM54C74 or MM74C74 Top View Note A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’ A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’ C1995 National Semiconductor Corporation TL F 5885 TL F 5885 – 2 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin (Note 1) Operating Temperature Range MM54C74 MM74C74 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C b 65 C to a 150 C Storage Temperature Range Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (Soldering 10 seconds) 260 C Operating VCC Range VCC(Max) 3V to 15V 18V DC Electrical Characteristics Min Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Supply Current Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage Parameter Max limits apply across temperature range unless otherwise specified Conditions Min 35 80 15 20 45 90 05 10 10 b1 0 Typ Max Units V V V V V V V V mA mA mA VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 15V VCC e 15V VCC e 15V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 75V 74C VCC e 4 75V 54C VCC e 4 5V ID e b360 mA 74C VCC e 4 75V ID e b360 mA 54C VCC e 4 5V ID e 360 mA 74C VCC e 4 75V ID e 360 mA VCC e 5V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 10V VIN(0) e 0V TA e 25 C VOUT e 0V VCC e 5V VIN(1) e 5V TA e 25 C VOUT e VCC VCC e 10V VIN(1) e 10V TA e 25 C VOUT e VCC 0 05 60 CMOS LPTTL INTERFACE VCCb1 5 08 24 04 V V V OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) ISOURCE ISOURCE ISINK ISINK Output Source Current Output Source Current Output Sink Current Output Sink Current b 1 75 b8 0 mA mA mA mA 1 75 80 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation 2 AC Electrical Characteristics Symbol CIN tpd Parameter Input Capacitance Propagation Delay Time to a Logical ‘‘0’’ tpd0 or Logical ‘‘1’’ tpd1 from Clock to Q or Q Propagation Delay Time to a Logical ‘‘0’’ from Preset or Clear Propagation Delay Time to a Logical ‘‘1’’ from Preset or Clear Time Prior to Clock Pulse that Data Must be Present tSETUP Time after Clock Pulse that Data Must be Held Minimum Clock Pulse Width (tWL e tWH) Minimum Preset and Clear Pulse Width Maximum Clock Rise and Fall Time Maximum Clock Frequency Power Dissipation Capacitance TA e 25 C CL e 50 pF unless otherwise noted Conditions Any Input (Note 2) VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V (Note 3) 15 0 50 20 50 35 80 40 100 40 Min Typ 50 180 70 180 70 250 100 50 20 b 20 b8 0 Max Units pF 300 110 300 110 400 150 ns ns ns ns ns ns ns ns tpd tpd tS0 tS1 tH0 tH1 tPW1 tPW2 tr tf fMAX CPD 0 0 250 100 160 70 ns ns ns ns ns ns ms ms MHz MHz pF 100 40 100 40 AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90 Switching Time Waveform CMOS to CMOS TL F 5885 – 3 tr e tf e 20 ns 3 AC Test Circuit TL F 5885 – 4 Typical Applications Ripple Counter (Divide by 2n) TL F 5885 – 5 Shift Register TL F 5885 – 6 Guaranteed Noise Margin as a Function of VCC 74C Compatibility TL F 5885 – 7 TL F 5885 – 8 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C74J or MM74C74J NS Package Number J14A 5 MM54C74 MM74C74 Dual D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Ceramic Dual-In-Line Package (J) Order Number MM54C74N or MM74C74N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications