MM74HC74A

MM54HC74A MM74HC74A Dual D Flip-Flop with Preset and Clear January 1988 MM54HC74A MM74HC74A Dual D Flip-Flop with Preset and Clear General Description The MM54HC74A MM74HC74A utilizes advanced silicongate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads This flip-flop has independent data preset clear and clock inputs and Q and Q outputs The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse Preset and clear are independent of the clock and accomplished by a low level at the appropriate input The 54HC 74HC logic family is functionally and pinout compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Y Y Y Y Typical propagation delay 20 ns Wide power supply range 2 – 6V Low quiescent current 40 mA maximum (74HC Series) Low input current 1 mA maximum Fanout of 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package Truth Table Inputs PR L H L H H H CLR H L L H H H CLK X X X D X X X H L X Outputs Q H L H H L Q0 Q L H H L H Q0 u u L Note Q0 e the level of Q before the indicated input conditions were established This configuration is nonstable that is it will not persist when preset and clear inputs return to their inactive (high) level TL F 5106 – 1 Order Number MM54HC74A or MM74HC74A TL F 5106 – 2 C1995 National Semiconductor Corporation TL F 5106 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN OUT) Operating Temp Range (TA) MM74HC MM54HC Input Rise or Fall Times VCC e 2 0V (tr tf) VCC e 4 5V VCC e 6 0V Min 2 0 Max 6 VCC Units V V If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 7 0V Supply Voltage (VCC) b 1 5 to VCC a 1 5V DC Input Voltage (VIN) b 0 5 to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C b 40 b 55 a 85 a 125 C C ns ns ns 1000 500 400 DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V VIN e VIH or VIL lIOUTl s20 mA 2 0V 4 5V 6 0V 4 5V 6 0V 2 0V 4 5V 6 0V 4 5V 6 0V 6 0V 6 0V 20 45 60 43 52 0 0 0 02 02 TA e 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 15 3 15 42 05 1 35 18 19 44 59 3 98 5 48 01 01 01 0 26 0 26 g0 1 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits 15 3 15 42 05 1 35 18 19 44 59 3 84 5 34 01 01 01 0 33 0 33 g1 0 15 3 15 42 05 1 35 18 19 44 59 37 52 01 01 01 04 04 g1 0 V V V V V V V V V V V V V V V V mA mA VIL VOH VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VIN e VCC or GND IOUT e 0 mA 40 40 80 Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics VCC e 5V Symbol fMAX tPHL tPLH tPHL tPLH tREM ts tH tW Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q or Q Maximum Propagation Delay Preset or Clear to Q or Q Minimum Removal Time Preset or Clear to Clock Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clock Preset or Clear TA e 25 C CL e 15 pF tr e tf e 6 ns Typ 72 10 17 6 10 0 8 Guaranteed Limit 30 30 40 5 20 0 16 Units MHz ns ns ns ns ns ns Conditions AC Electrical Characteristics Symbol fMAX Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q or Q Maximum Propagation Delay Preset or Clear To Q or Q Minimum Removal Time Preset or Clear To Clock Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clock Preset or Clear Maximum Output Rise and Fall Time Maximum Input Rise and Fall Time Power Dissipation Capacitance (Note 5) Maximum Input Capacitance CL e 50 pF tr e tf e 6 ns (unless otherwise specified) VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 30 9 8 25 7 6 TA e 25 C Typ 22 72 94 34 12 10 66 20 16 20 6 5 35 10 8 6 30 35 110 22 19 150 30 26 50 10 9 80 16 14 0 0 0 80 16 14 75 15 13 1000 500 400 80 5 10 10 10 74HC TA eb40 to 85 C 5 24 28 140 28 24 190 38 33 65 13 11 100 20 17 0 0 0 101 20 17 95 19 16 1000 500 400 54HC TA eb55 to 125 C 4 20 24 165 33 28 225 45 38 75 15 13 120 24 20 0 0 0 119 24 20 110 22 19 1000 500 400 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Conditions Guaranteed Limits tPHL tPLH tPHL tPLH tREM ts tH tW tTLH tTHL tr tf CPD CIN (per flip-flop) Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3 MM54HC74A MM74HC74A Dual D Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) Order Number MM54HC74J or MM74HC74J NS Package J14A Order Number MM74HC74N NS Package N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications