74AHC1G00

74AHC1G00; 74AHCT1G00 2-input NAND gate Rev. 06 — 30 May 2007 Product data sheet 1. General description 74AHC1G00 and 74AHCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input NAND function. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features I I I I I I Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options ESD protection: N HBM JESD22-A114E: exceeds 2000 V N MM JESD22-A115-A: exceeds 200 V N CDM JESD22-C101C: exceeds 1000 V I Specified from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74AHC1G00GW 74AHCT1G00GW 74AHC1G00GV 74AHCT1G00GV −40 °C to +125 °C SC-74A −40 °C to +125 °C Name TSSOP5 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic surface-mounted package; 5 leads Version SOT353-1 SOT753 Type number NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 4. Marking Table 2. Marking codes Marking AA A00 CA C00 Type number 74AHC1G00GW 74AHC1G00GV 74AHCT1G00GW 74AHCT1G00GV 5. Functional diagram B 1 2 B A 1 Y 4 2 mna097 mna098 & 4 A Y mna099 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AHC1G00 74AHCT1G00 B A 1 2 5 VCC GND 3 001aaf092 4 Y Fig 4. Pin configuration 6.2 Pin description Table 3. Symbol B A GND Y VCC Pin description Pin 1 2 3 4 5 Description data input data input ground (0 V) data output supply voltage 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 2 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Inputs A L L H H B L H L H Output Y H H H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +7.0 +7.0 ±20 ±25 75 +150 250 Unit V V mA mA mA mA mA °C mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V [1] −20 −75 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For both TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Conditions Min 2.0 0 0 −40 74AHC1G00 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 4.5 0 0 −40 74AHCT1G00 Min Typ 5.0 +25 Max 5.5 5.5 VCC +125 20 V V V °C ns/V ns/V Unit 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 3 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter For type 74AHC1G00 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 0 0 0 1.5 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 0.1 1.0 10 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.8 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 1.0 10 10 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 2.0 40 10 V V V V V V V V V V V V V V V V µA µA pF Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V For type 74AHCT1G00 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 4.5 0 - 0.1 0.36 0.1 4.4 3.8 - 0.1 0.44 1.0 4.4 3.70 - 0.1 0.55 2.0 V V V V µA VOL II 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 4 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC ∆ICC Conditions Min supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance 25 °C Typ Max 1.0 1.35 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 10 1.5 Min Max 40 1.5 µA mA CI - 1.5 10 - 10 - 10 pF 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; tr = tf = ≤ 3.0 ns. For test circuit see Figure 6. Symbol Parameter For type 74AHC1G00 tpd propagation delay A and B to Y; see Figure 5 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power per buffer; dissipation CL = 50 pF; f = 1 MHz; capacitance VI = GND to VCC propagation delay A and B to Y; see Figure 5; VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power per buffer; dissipation VI = GND to VCC capacitance tpd is the same as tPLH and tPHL. Typical values are measured at VCC = 3.3 V. Typical values are measured at VCC = 5.0 V. CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. © NXP B.V. 2007. All rights reserved. Conditions Min [1] [2] 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max [3] 4.5 6.5 3.5 4.9 17 7.9 11.4 5.5 7.5 - 1.0 1.0 1.0 1.0 - 9.5 13.0 6.5 8.5 - 1.0 1.0 1.0 1.0 - 10.5 14.5 7.0 9.5 - ns ns ns ns pF [4] - For type 74AHCT1G00 tpd [1] [3] [4] 3.6 5.0 18 6.2 7.9 - 1.0 1.0 - 7.1 9.0 - 1.0 1.0 - 8.0 10.0 - ns ns pF - [1] [2] [3] [4] 74AHC_AHCT1G00_6 Product data sheet Rev. 06 — 30 May 2007 5 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 12. Waveforms A, B input VM tPHL tPLH Y output VM mna106 Measurement points are given in Table 9. Fig 5. The inputs (A and B) to output (Y) propagation delays Table 9. Type 74AHC1G00 74AHCT1G00 Measurement point Input VI GND to VCC GND to 3.0 V VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 0.5 × VCC VCC PULSE GENERATOR VI DUT RT CL VO mna101 Test data is given in Table 8. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Load circuitry for switching times 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 6 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE vMA Z 5 4 A2 A1 (A3) θ A 1 e e1 bp 3 wM detail X Lp L 0 1.5 scale 3 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 θ 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 7. Package outline SOT353-1 (TSSOP5) 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 7 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate Plastic surface-mounted package; 5 leads SOT753 D B E A X y HE vMA 5 4 Q A A1 c 1 2 3 detail X Lp e bp wM B 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT753 REFERENCES IEC JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 8. Package outline SOT753 (SC-74A) 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 8 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 14. Abbreviations Table 10. Acronym CDM DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20070530 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT1G00_5 Document ID 74AHC_AHCT1G00_6 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Package SOT353 changed to SOT353-1 in Section 3 and Section 13. Quick reference data and Soldering sections removed. Product specification Product specification Product specification Product specification Preliminary specification 74AHC_AHCT1G00_4 74AHC_AHCT1G00_3 74AHC_AHCT1G00_2 74AHC_AHCT1G00_N_1 - 74AHC_AHCT1G00_5 74AHC_AHCT1G00_4 74AHC_AHCT1G00_3 74AHC_AHCT1G00_2 20020527 20020227 20010131 19990127 74AHC_AHCT1G00_N_1 19981125 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 9 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 30 May 2007 10 of 11 NXP Semiconductors 74AHC1G00; 74AHCT1G00 2-input NAND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 May 2007 Document identifier: 74AHC_AHCT1G00_6