INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7046A
Phase-locked-loop with lock
detector
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
FEATURES
• Low power consumption
• Centre frequency up to 17 MHz
(typ.) at VCC = 4.5 V
• Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;
• Excellent VCO frequency linearity
• VCO-inhibit control for ON/OFF
keying and for low standby power
consumption
• Minimal frequency drift
• Operation power supply voltage
range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
• Zero voltage offset due to op-amp
buffering
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.
The 74HC/HCT7046 are
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.
A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
between pin 15 (CLD) and pin 8
(GND). The value of the CLD capacitor
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input
December 1990
amplifiers. With a passive low-pass
filter, the “7046” forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.
VCO
The VCO requires one external
capacitor C1 (between C1A and C1B)
and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.
The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEMOUT). In contrast to conventional
techniques where the DEMOUT
voltage is one threshold voltage lower
than the VCO input voltage, here the
DEMOUT voltage equals that of the
VCO input. If DEMOUT is used, a load
resistor (RS) should be connected
from DEMOUT to GND; if unused,
DEMOUT should be left open. The
VCO output (VCOOUT) can be
connected directly to the comparator
input (COMPIN), or connected via a
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.
The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators’ sections are identical,
so that there is no difference in the
2
74HC/HCT7046A
SIGIN (pin 14) or COMPIN (pin 3)
inputs between the HC and HCT
versions.
Phase comparators
The signal input (SIGIN) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (fi) must have a 50% duty
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (fr = 2fi) is
suppressed,
is:
V CC
V DEMOUT = ----------- ( φ SIGIN – φ COMPIN )
π
where VDEMOUT is the demodulator
output at pin 10;
VDEMOUT = VPC1OUT (via low-pass
filter).
The phase comparator gain
is:
V CC
K p = ----------- ( V ⁄ r ) .
π
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(VDEMOUT), is the resultant of the
phase differences of signals (SIGIN)
and the comparator input (COMPIN)
as shown in Fig.6. The average of
VDEMOUT is equal to 1/2 VCC when
there is no signal or noise at SIGIN
and with this input the VCO oscillates
at the centre frequency (fo). Typical
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
waveforms for the PC1 loop locked at
fo are shown in Fig.7.
The frequency capture range (2fc) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2fL) is defined
as the frequency range of input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration retains lock
even with very noisy input signals.
Typical behaviour of this type of
phase comparator is that it can lock to
input frequencies close to the
harmonics of the VCO centre
frequency.
Phase comparator 2 (PC2)
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIGIN and COMPIN are not important.
PC2 comprises two D-type flip-flops,
control-gating and a 3-state output
stage. The circuit functions as an
up-down counter (Fig.5) where SIGIN
causes an up-count and COMPIN a
down-count. The transfer function of
PC2, assuming ripple (fr = fi) is
suppressed,
is:
V CC
V DEMOUT = ----------- ( φ SIGIN – φ COMPIN )
4π
where VDEMOUT is the demodulator
output at pin 10;
VDEMOUT = VPC2OUT (via low-pass
filter).
December 1990
74HC/HCT7046A
The phase comparator gain is:
V CC
K p = ----------- ( V ⁄ r ) .
4π
the low-pass filter. With no signal
present at SIGIN the VCO adjusts, via
PC2, to its lowest frequency.
APPLICATIONS
VDEMOUT is the resultant of the initial
phase differences of SIGIN and
COMPIN as shown in Fig.8. Typical
waveforms for the PC2 loop locked at
fo are shown in Fig.9.
• FM modulation and demodulation
When the frequencies of SIGIN and
COMPIN are equal but the phase of
SIGIN leads that of COMPIN, the
p-type output driver at PC2OUT is held
“ON” for a time corresponding to the
phase difference (φDEMOUT). When
the phase of SIGIN lags that of
COMPIN, the n-type driver is held
“ON”.
• Data synchronization and
conditioning
When the frequency of SIGIN is higher
than that of COMPIN, the p-type
output driver is held “ON” for most of
the input signal cycle time, and for
the remainder of the cycle both n and
p- type drivers are “OFF” (3-state). If
the SIGIN frequency is lower than the
COMPIN frequency, then it is the
n-type driver that is held “ON” for
most of the cycle. Subsequently, the
voltage at the capacitor (C2) of the
low-pass filter connected to PC2OUT
varies until the signal and comparator
inputs are equal in both phase and
frequency. At this stable point the
voltage on C2 remains constant as
the PC2 output is in 3-state and the
VCO input at pin 9 is a high
impedance.
Thus, for PC2, no phase difference
exists between SIGIN and COMPIN
over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both p and n-type
drivers are “OFF” for most of the
signal input cycle. It should be noted
that the PLL lock range for this type of
phase comparator is equal to the
capture range and is independent of
3
• Frequency synthesis and
multiplication
• Frequency discrimination
• Tone decoding
• Voltage-to-frequency conversion
• Motor-speed control
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C;
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
HC
fo
VCO centre frequency
CI
input capacitance (pin 5)
CPD
power dissipation capacitance per package
C1 = 40 pF; R1 = 3 kΩ; VCC = 5 V
notes 1 and 2
Notes
1. Applies to the phase comparator section only (VCO disabled).
For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22.
2. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
4
HCT
19
19
MHz
3.5
3.5
pF
24
24
pF
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
LD
lock detector output (active HIGH)
2
PC1OUT
phase comparator 1 output
3
COMPIN
comparator input
4
VCOOUT
VCO output
5
INH
inhibit input
6
C1A
capacitor C1 connection A
7
C1B
capacitor C1 connection B
8
GND
ground (0 V)
9
VCOIN
VCO input
10
DEMOUT
demodulator output
11
R1
resistor R1 connection
12
R2
resistor R2 connection
13
PC2OUT
phase comparator 2 output
14
SIGIN
signal input
15
CLD
lock detector capacitor input
16
VCC
positive supply voltage
Fig.1 Pin configuration.
December 1990
Fig.2 Logic symbol.
5
Fig.3 IEC logic symbol.
December 1990
R1
R2
6
6
5
INH
11 R1
12 R2
C1A
7
4
3
RS
10
9
DEM OUT VCO IN
VCO
(a)
C1B VCO OUT COMP IN
C1
4046A
C2
R4
R3
Fig.4 Functional diagram.
PC3 OUT 15
PHASE
COMPARATOR
3
PHASE
COMPARATOR PCP OUT 1
2
PC2 OUT 13
PC1 OUT 2
PHASE
COMPARATOR
1
SIG IN
14
identical to 4046A
(b)
C CLD
C LD
15
LOCK
DETECTOR
PHASE
COMPARATOR
2
MGA847
LD 1
PC2 OUT 13
7046A
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.5 Logic diagram.
Fig.6
Phase comparator 1: average output
voltage versus input phase difference:
V CC
V DEMOUT = V PC1OUT = ----------- ( φ SIGIN – φ COMPIN )
π
Fig.7
φ DEMOUT = φ SIGIN – φ COMPIN
December 1990
7
Typical waveforms for PLL using phase
comparator 1, loop locked at fo.
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.8
Phase comparator 2: average output
voltage versus input phase difference:
V CC
V DEMOUT = V PC2OUT = ----------- ( φ SIGIN – φ COMPIN )
4π
Fig.9
φ DEMOUT
= ( φ SIGIN – ˙φ COMPIN ) .
December 1990
8
Typical waveforms for PLL using phase
comparator 2, loop locked at fo.
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT
74HC
74HCT
SYMBOL PARAMETER
UNIT
min.
typ.
max. min.
typ.
max.
VCC
DC supply voltage
3.0
5.0
6.0
4.5
5.0
5.5
V
VCC
DC supply voltage if VCO section is
not used
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
DC input voltage range
0
VCC
0
VCC
V
VO
DC output voltage range
0
VCC
0
VCC
V
CONDITIONS
Tamb
operating ambient temperature range −40
+85
−40
+85
°C
see DC and AC
Tamb
operating ambient temperature range −40
+125
−40
+125
°C
CHARACTER-
tr, tf
input rise and fall times (pin 5)
1000
500
400
ISTICS
6.0
6.0
500
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCC
DC supply voltage
−0.5
+7
V
±IIK
DC input diode current
20
mA
for VI < −0.5 V or VI > VCC + 0.5 V
±IOK
DC output diode current
20
mA
for VO < −0.5 V or VO > VCC + 0.5 V
±IO
DC output source or sink current
25
mA
for − 0.5 V < VO < VCC + 0.5 V
±ICC;
±IGND
DC VCC or GND current
50
mA
Tstg
storage temperature range
+150
°C
Ptot
power dissipation per package
−65
CONDITIONS
plastic DIL
750
mW
for temperature range: −40 to +125 °C
74HC/HCT
above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO)
500
mW
above +70 °C: derate linearly with 8 mW/K
December 1990
9
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
DC CHARACTERISTICS FOR 74HC
Quiescent supply current
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
+25
min.
ICC
quiescent supply
current
(VCO disabled)
December 1990
−40 to +85
−40 to +125
typ. max. min. max. min.
8.0
80.0
10
UNIT V
CC
(V)
OTHER
max.
160.0
µA
6.0
pins 3, 5, and 14 at
VCC; pin 9 at GND;
II at pins 3 and 14
to be excluded
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
+25
−40 to +85
min.
typ. max. min. max. min. max.
1.5
3.15
4.2
1.2
2.4
3.2
VIH
DC coupled HIGH
level input voltage
SIGIN, COMPIN
VIL
DC coupled LOW level
input voltage
SIGIN, COMPIN
VOH
HIGH level output
voltage
LD, PCnOUT
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
VOH
HIGH level output
voltage
LD, PCnOUT
3.98
5.48
4.32
5.81
3.84
5.34
VOL
LOW level output
voltage
LD, PCnOUT
0
0
0
VOL
LOW level output
voltage
LD, PCnOUT
±II
0.8
2.1
2.8
3-state
OFF-state current
PC2OUT
RI
input resistance
SIGIN, COMPIN
December 1990
1.5
3.15
4.2
0.5
1.35
1.8
1.5
3.15
4.2
UNIT V
CC
(V)
VI
OTHER
V
2.0
4.5
6.0
V
2.0
4.5
6.0
1.9
4.4
5.9
V
2.0
4.5
6.0
VIH
or
VIL
−IO = 20 µA
−IO = 20 µA
−IO = 20 µA
3.7
5.2
V
4.5
6.0
VIH
or
VIL
−IO = 4.0 mA
−IO = 5.2 mA
0.5
1.35
1.8
0.5
1.35
1.8
0.1
0.1
0.1
0.1
0.1
0.1
V
2.0
4.5
6.0
VIH
or
VIL
IO = 20 µA
IO = 20 µA
IO = 20 µA
0.15 0.26
0.16 0.26
0.33
0.33
0.4
0.4
V
4.5
6.0
VIH
or
VIL
IO = 4.0 mA
IO = 5.2 mA
3.0
7.0
18.0
30.0
4.0
9.0
23.0
38.0
5.0
11.0
27.0
45.0
µA
0.5
5.0
10.0
input leakage current
SIGIN, COMPIN
±IOZ
−40 to +125
0.1
0.1
0.1
800
250
150
11
2.0
3.0
4.5
6.0
VCC
µA
6.0
VIH
or
VIL
kΩ
3.0
4.5
6.0
VI at self-bias
operating point;
∆VI = 0.5 V; see
Figs 10, 11 and 12
or
GND
VO = VCC
or GND
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
VCO section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
SYMBOL
74HC
PARAMETER
VIH
HIGH level
input voltage
INH
VIL
LOW level
input voltage
INH
HIGH level
VOH
output voltage
VCOOUT
HIGH level
VOH
TEST CONDITIONS
output voltage
VCOOUT
+25
−40 to +85
−40 to +125
min.
typ. max. min. max.
min.
2.1
3.15
4.2
1.7
2.4
3.2
2.1
3.15
4.2
1.3
2.1
2.8
2.1
3.15
4.2
0.9
1.35
1.8
0.9
1.35
1.8
UNIT V
CC
(V)
VI
OTHER
max.
0.9
1.35
1.8
V
3.0
4.5
6.0
V
3.0
4.5
6.0
2.9
4.4
5.9
3.0
4.5
6.0
2.9
4.4
5.9
2.9
4.4
5.9
V
3.0
4.5
6.0
VIH
or
VIL
−IO = 20 µA
−IO = 20 µA
−IO = 20 µA
3.98
5.48
4.32
5.81
3.84
5.34
3.7
5.2
V
4.5
6.0
VIH
or
VIL
−IO = 4.0 mA
−IO = 5.2 mA
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
6.0
VIH
or
VIL
IO = 20 µA
IO = 20 µA
IO = 20 µA
0.15 0.26
0.16 0.26
0.33
0.33
0.4
0.4
V
4.5
6.0
VIH
or
VIL
IO = 4.0 mA
IO = 5.2 mA
LOW level output
voltage C1A, C1B
(test purposes only)
0.40
0.40
0.47
0.47
0.54
0.54
V
4.5
6.0
VIH
or
VIL
IO = 4.0 mA
IO = 5.2 mA
input leakage current
INH, VCOIN
0.1
1.0
1.0
µA
6.0
VOL
LOW level
output voltage
VCOOUT
0
0
0
VOL
LOW level
output voltage
VCOOUT
VOL
±II
0.1
0.1
0.1
VCC
or
GND
R1
resistor range
3.0
3.0
3.0
300
300
300
kΩ
3.0
4.5
6.0
note 1
R2
resistor range
3.0
3.0
3.0
300
300
300
kΩ
3.0
4.5
6.0
note 1
C1
capacitor range
40
40
40
no
limit
pF
3.0
4.5
6.0
VVCOIN
operating voltage
range at VCOIN
1.1
1.1
1.1
1.9
3.4
4.9
V
3.0
4.5
6.0
over the range
specified for R1;
for linearity see
Figs 18 and 19.
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.
December 1990
12
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Demodulator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
min.
RS
resistor range
VOFF
offset voltage
VCOIN to VDEMOUT
RD
dynamic output
resistance at DEMOUT
December 1990
+25
−40 to +85
−40 to +125
typ.
max. min. max. min.
UNIT
VCC
(V)
OTHER
max.
kΩ
3.0
4.5
6.0
at RS > 300 kΩ
the leakage
current can
influence
VDEMOUT
±30
±20
±10
mV
3.0
4.5
6.0
VI = VVCOIN =
1/2 VCC;
values taken
over RS range;
see Fig.13
25
25
25
Ω
3.0
4.5
6.0
VDEMOUT =
1/2 VCC
50
50
50
300
300
300
13
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
AC CHARACTERISTICS FOR 74HC
Phase comparator section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
+25
min.
−40 to +85
−40 to +125
typ.
max. min. max. min. max.
UNIT
VCC
(V)
OTHER
tPHL/ tPLH
propagation delay
SIGIN, COMPIN
to PC1OUT
58
21
17
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
Fig.14
tPZH/ tPZL
3-state output enable
time SIGIN, COMPIN
to PC2OUT
74
27
22
280
56
48
350
70
60
420
84
71
ns
2.0
4.5
6.0
Fig.15
tPHZ/ tPLZ
3-state output disable
time SIGIN, COMPIN
to PC2OUT
96
35
28
325
65
55
405
81
69
490
98
83
ns
2.0
4.5
6.0
Fig.15
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.14
VI(p-p)
AC coupled input sensitivity
(peak-to-peak value) at
SIGIN or COMPIN
9
11
15
33
mV
2.0
3.0
4.5
6.0
fi = 1 MHz
VCO section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
+25
min.
∆f/T
frequency stability
with temperature
change
fo
∆fVCO
max.
typ.
−40
to +125
UNIT V
CC
(V)
OTHER
max. min. max.
%/K
3.0
4.5
6.0
VI = VVCOIN =1/2 VCC ;
R1 = 100 kΩ; R2 = ∞;
C1 = 100 pF; see Fig.16
VCO centre
7.0
10.0
frequency
11.0 17.0
(duty factor = 50%) 13.0 21.0
MHz
3.0
4.5
6.0
VVCOIN = 1/2 VCC;
R1 = 3 kΩ; R2 = ∞;
C1 = 40 pF; see Fig.17
VCO frequency
1.0
0.4
0.3
%
3.0
4.5
6.0
R1 = 100 kΩ; R2 = ∞;
C1 = 100 pF; see Figs 18
and 19
50
50
50
%
3.0
4.5
6.0
linearity
δVCO
typ.
−40 to +85
duty factor at
VCOOUT
December 1990
0.20
0.15
0.14
14
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
DC CHARACTERISTICS FOR 74HCT
Quiescent supply current
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
+25
min.
ICC
quiescent supply current
(VCO disabled)
∆ICC
additional quiescent
supply current per input
pin for unit load coefficient
is 1 (note 1)
VI = VCC − 2.1 V
−40 to +85
−40 to +125
UNIT V
CC
(V)
OTHER
typ. max. min. max. min. max.
100
8.0
80.0
160.0 µA
6.0
pins 3, 5 and 14
at VCC; pin 9 at
GND; II at pins 3
and 14 to be
excluded
360
450
490
µA
4.5
to
5.5
pins 3 and 14 at
VCC; pin 9 at
GND; II at pins 3
and 14 to be
excluded
Note
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given above.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
INH
1.00
December 1990
15
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
SYM
BOL
74HCT
PARAMETER
+25
min. typ.
VIH
DC coupled
HIGH level input voltage 3.15 2.4
SIGIN, COMPIN
VIL
DC coupled
LOW level input voltage
SIGIN, COMPIN
VOH
VOH
TEST CONDITIONS
HIGH level output voltage
LD, PCnOUT
HIGH level output voltage
LD, PCnOUT
2.1
4.4
−40 to +85
max min. max. min.
4.5
3.98 4.32
LOW level output voltage
LD, PCnOUT
0
VOL
LOW level output voltage
LD, PCnOUT
0.15 0.26
±II
input leakage current
SIGIN, COMPIN
30
±IOZ
3-state
OFF-state current
PC2OUT
0.5
RI
input resistance
SIGIN, COMPIN
UNIT
VCC
(V)
VI
OTHER
max.
1.35
VOL
December 1990
−40 to +125
V
4.5
V
4.5
4.4
4.4
V
4.5
VIH
or
VIL
−IO = 20 µA
3.84
3.7
V
4.5
VIH
or
VIL
−IO = 4.0 mA
0.1
0.1
0.1
V
4.5
VIH
or
VIL
IO = 20 µA
0.33
0.4
V
4.5
VIH
or
VIL
IO = 4.0 mA
38
45
µA
5.5
VCC
or
GND
5.0
250
10.0
µA
kΩ
16
5.5
VIH
or
VIL
4.5
VI at self-bias
operating point;
∆VI = 0.5 V; see Figs
10, 11 and 12
VO = VCC
or GND
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
DC CHARACTERISTICS FOR 74HCT
VCO section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
VIH
HIGH level input
voltage
INH
2.0
1.6
VIL
LOW level input
voltage
INH
VOH
HIGH level output
voltage
VCOOUT
4.4
4.5
4.4
VOH
HIGH level output
voltage
VCOOUT
3.98
4.32
3.84
VOL
LOW level output
voltage
VCOOUT
0
VOL
LOW level output
voltage
VCOOUT
VOL
±II
1.2
2.0
VI
OTHER
max.
2.0
0.8
UNIT V
CC
(V)
V
4.5
to
5.5
V
4.5
to
5.5
4.4
V
4.5
VIH
or
VIL
−IO = 20 µA
3.7
V
4.5
VIH
or
VIL
−IO = 4.0 mA
0.8
0.8
0.1
0.1
V
4.5
VIH
or
VIL
IO = 20 µA
0.15 0.26
0.33
0.4
V
4.5
VIH
or
VIL
IO = 4.0 mA
LOW level output
voltage C1A, C1B
(test purposes only)
0.40
0.47
0.54
V
4.5
VIH
or
VIL
IO = 4.0 mA
input leakage
current
INH, VCOIN
0.1
1.0
1.0
µA
5.5
VCC
0.1
or
GND
R1
resistor range
3.0
300
kΩ
4.5
note 1
R2
resistor range
3.0
300
kΩ
4.5
note 1
C1
capacitor range
40
no
limit
pF
4.5
VVCOIN
operating voltage
range at VCOIN
1.1
3.4
V
4.5
over the range
specified for
R1;
for linearity see
Figs 18 and 19.
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.
December 1990
17
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Demodulator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
+25
min.
RS
resistor range
VOFF
offset voltage
VCOIN to VDEMOUT
RD
dynamic output
−40 to +85
−40 to +125
UNIT V
CC
(V)
OTHER
typ. max. min. max. min. max.
kΩ
4.5
at RS > 300 kΩ the
leakage current can
influence VDEMOUT
±20
mV
4.5
VI = VVCOIN = 1/2
VCC; values taken
over RS range;
see Fig.13
25
Ω
4.5
VDEMOUT = 1/2 VCC
50
300
resistance at DEMOUT
AC CHARACTERISTICS FOR 74HCT
Phase comparator section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
SYMBOL
TEST
CONDITIONS
74HCT
PARAMETER
+25
min. typ.
−40 to +85
max.
min. max.
UNIT
VCC
(V)
−40 to +125
min.
OTHER
max.
tPHL/ tPLH
propagation delay
SIGIN, COMPIN
to PC1OUT
21
40
50
60
ns
4.5
Fig.14
tPZH/ tPZL
3-state output enable
time SIGIN, COMPIN
to PC2OUT
27
56
70
84
ns
4.5
Fig.15
tPHZ/ tPLZ
3-state output disable
time SIGIN, COMPIN
to PC2OUT
35
65
81
98
ns
4.5
Fig.15
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.14
VI(p-p)
AC coupled input sensitivity
(peak-to-peak value) at
SIGIN or COMPIN
15
mV
4.5
fi =
1 MHz
December 1990
18
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
VCO section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25
min. typ.
∆f/T
frequency stability
with temperature
change
fo
VCO centre frequency 11.0
(duty factor = 50%)
∆fVCO
VCO frequency
−40 to +85
max.
typ.
−40 to +125
UNIT V
CC
(V)
max. min. max.
%/K
4.5
VI = VCOIN within
recommended
range;
R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pf;
see Fig.16b
17.0
MHz
4.5
VVCOIN = 1/2 VCC;
R1 = 3 kΩ; R2 = ∞;
C1 = 40 pF;
see Fig.17
0.4
%
4.5
R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pF; see
Figs 18 and 19
50
%
4.5
0.15
linearity
δVCO
duty factor at VCOOUT
December 1990
OTHER
19
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
FIGURE REFERENCES FOR DC CHARACTERISTICS
Fig.11 Input resistance at SIGIN, COMPIN with
∆VI = 0.5 V at self-bias point.
Fig.10 Typical input resistance curve at SIGIN,
COMPIN.
____ RS = 50 kΩ
- - - - RS = 300 kΩ
Fig.12 Input current at SIGIN, COMPIN with
∆VI = 0.5 V at self-bias point.
December 1990
Fig.13 Offset voltage at demodulator output as a
function of VCOIN and RS.
20
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.
Fig.14 Waveforms showing input (SIGIN, COMPIN) to output (PC1OUT) propagation delays and the output
transition times.
(1) HC : VM = 50%; VI = GND to VCC.
Fig.15 Waveforms showing the 3-state enable and disable times for PC2OUT.
December 1990
21
∆f
(%)
20
VCC =
VCC =
∆f
(%)
20
15
MSB712
25
handbook, halfpage
3V
20
5V
6V
15
6V
3V
5V
10
10
3V
VCC =
3V
5V
A
6V
5V
3V
5V
6V
15
10
6V
22
5
3V
5
5
0
4.5 V
5V
6V
0
0
−5
5
5
−10
10
10
−15
15
15
−20
20
20
−25
−50
0
50
(a)
100
150
Tamb (oC)
25
50
0
50
(b)
100
150
Tamb ( o C)
25
50
0
50
Philips Semiconductors
25
handbook, halfpage
∆f
(%)
Phase-locked-loop with lock detector
December 1990
MSB711
MSB710
25
handbook, halfpage
100
150
Tamb ( o C)
(c)
Product specification
74HC/HCT7046A
Fig.16 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
without offset (R2 = ∞): (a) R1 = 3 kΩ; (b) R1 = 10 kΩ; (c) R1 = 300 kΩ.
- - - - with offset (R1 = ∞): (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ.
In (b), the frequency stability for R1 = R2 = 10 kΩ at 5 V is also given (curve A). This curve is set by the total VCO bias current, and is
not simply the addition of the two 10 kΩ stability curves. C1 = 100 pF; VVCO IN = 0.5 VCC.
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
AC WAVEFORMS
To obtain optimum temperature stability, C1 must be a small as possible, but larger than 100 pF.
Fig.16 Continued.
December 1990
23
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.17 Graphs showing VCO frequency (fVCO) as a function of the VCO input voltage (VVCOIN).
December 1990
24
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.18 Definition of VCO frequency linearity:
∆V = 0.5 V over the VCC range:
for VCO linearity
f1 + f2
f′ 0 = -------------2
Fig.19 Frequency linearity as a function of R1, C1
and VCC: R2 = ∞ and ∆V = 0.5 V.
f′ 0 – f 0
linearity = ---------------- × 100 %
f′ 0
December 1990
25
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
____ C1 = 40 pF
- - - - C1 = 1 µF
____ C1 = 40 pF
- - - - C1 = 1 µF
Fig.20 Power dissipation versus the value of R1:
CL = 50 pF; R2 = ∞; VVCOIN = 1/2 VCC;
Tamb = 25 °C.
Fig.21 Power dissipation versus the value of R2:
CL = 50 pF; R1 = ∞; VVCOIN = GND = 0 V;
Tamb = 25 °C.
Fig.22 Typical dc power dissipation of demodulator
section as a function of RS: R1 = R2 = ∞;
Tamb = 25 °C; VVCOIN = 1/2 VCC.
December 1990
26
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
APPLICATION INFORMATION
This information is a guide for the approximation of values of external components to be used with the 74HC/HCT7046
in a phase-lock-loop system.
References should be made to Figs 27, 28 and 29 as indicated in the table.
Values of the selected components should be within the following ranges:
R1
between 3 kΩ and 300 kΩ;
R2
between 3 kΩ and 300 kΩ;
R1 + R2
parallel value > 2.7 kΩ;
C1
greater than 40 pF.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
VCO frequency characteristic
VCO frequency
without extra
offset
PC1, PC2
With R2 = ∞ and R1 within the range 3 kΩ < R1 < 300 kΩ, the characteristics
of the VCO operation will be as shown in Fig. 23.
(Due to R1, C1 time constant a small offset remains when R2 = ∞.)
Fig. 23 Frequency characteristic of VCO operating without offset:
fo = centre frequency; 2fL = frequency lock range.
Selection of R1 and C1
December 1990
PC1
Given fo, determine the values of R1 and C1 using Fig.27.
PC2
Given fmax and fo, determine the values of R1 and C1 using Fig.27,
use Fig.29 to obtain 2fL and then use this to calculate fmin.
27
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
SUBJECT
PHASE
COMPARATOR
74HC/HCT7046A
DESIGN CONSIDERATIONS
VCO frequency characteristic
VCO frequency
with extra
offset
PC1, PC2
With R1 and R2 within the ranges 3 kΩ < R1 < 300 kΩ, 3 kΩ < R2 < 300 kΩ,
the characteristics of the VCO operation will be as shown in Fig. 24.
Fig. 24 Frequency characteristic of VCO operating with offset:
fo = centre frequency; 2fL = frequency lock range.
Selection of R1, R2 and C1
PC1, PC2
December 1990
Given f0 and fL, determine the value of product R1C1 by using Fig.29.
Calculate foff from the equation foff = fo − 1.6fL.
Obtain the values of C1 and R2 by using Fig.28.
Calculate the value of R1 from the value of C1 and the product R1C1.
28
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
PLL conditions
with no signal at
the SIGIN input
PC1
VCO adjusts to fo with φDEMOUT = 90° and VVCOIN = 1/2 VCC (see Fig.6).
PC2
VCO adjusts to fo with φDEMOUT = −360° and VVCOIN = min. (see Fig.8).
PLL frequency
capture range
PC1, PC2
Loop filter component selection
SUBJECT
(a) τ = R3 x C2
(b) amplitude characteristic
(c) pole-zero diagram
Fig. 25 Simple loop filter for PLL without offset; R3 ≥ 500 Ω.
(a) τ1 = R3 x C2;
(b) amplitude characteristic
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
(c) pole-zero diagram
Fig. 26 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω.
PLL locks on
PC1
harmonics at
centre frequency PC2
yes
noise rejection at
signal input
PC1
high
PC2
low
AC ripple content PC1
when PLL is
PC2
locked
December 1990
no
fr = 2fi, large ripple content at φDEMOUT = 90°
fr = fi, small ripple content at φDEMOUT = 0°
29
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
(2) Interpolation for various values of R1 can be easily calculated because a constant R1C1 product will produce
almost the same VCO output frequency.
Fig.27 Typical value of VCO centre frequency (fo) as a function of C1: R2 = ∞; VVCOIN = 1/2 VCC; INH = GND;
Tamb = 25 °C.
December 1990
30
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
APPLICATION INFORMATION
(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
(2) Interpolation for various values of R2 can be easily calculated because a constant R2C2 product will produce
almost the same VCO output frequency.
Fig.28 Typical value of frequency offset as a function of C1: R1 = ∞; VVCOIN = 1/2 VCC; INH = GND; Tamb = 25 °C.
December 1990
31
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.29 Typical frequency lock range (2fL) versus the product R1C1: VVCOIN range = 0.9 to (VCC − 0.9) V;
R2 = ∞; VCO gain:
2f L
K V = ------------------------------------- 2π (r/s/V).
V VCOIN range
December 1990
32
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
on the application, the phase error can be defined as the
limit, a phase error of greater magnitude would be
considered out-of-lock. An example of an in-lock detection
circuit using the “7046A” is shown in Fig.30.
APPLICATION INFORMATION
Lock-detection circuit
The built-in lock-detection circuit will only work when used
in conjunction with the phase comparator PC2. The
lock-indication is derived from the phase error between
SIGIN and COMPIN. The PC2 has a typical phase error of
zero degrees over the entire VCO operating range.
However, to remain in-lock the circuit requires some small
adjustments. The variation is dependent on the loop
parameters and back-lash time (typically 5 ns). Depending
If the PLL is in-lock, only very small pulses will come from
the “up” or “down” connections of PC2. These pulses are
filtered out by a RC network. A Schmitt trigger produces a
steady state level, a HIGH level indicates an in-lock
condition and a pulsed output indicates an out-of-lock
condition as shown in Fig.31.
See Fig.31 for input waveform.
Fig.30 An example of an in-lock detection circuit using the “7046A”.
(a)
(b)
Fig.31 Waveforms showing the lock detection process; (a) in-lock; (b) out-of-lock.
December 1990
33
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
CLD
=
capacitor connected to pin 15
(includes the parasitic input capacitance of the IC, approximately 3.5 pF).
tLD
=
phase difference between SIGIN and COMPIN (positive-going edges).
Fig.32 CLD capacitor value versus typical tLD.
December 1990
34
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
The maximum permitted phase error
must be defined, before tLD can be
defined using the following formula:
φ max 1
t LD = ------------ × ------ .
360 f IN
Using this calculated value in Fig.32,
it is possible to define the value of
CLD, e.g. assuming the phase error is
36° and fIN = 2 MHz:
36°
1
t LD = ---------- × ----------------- = 50 ns,
360 2 MHz
and using Fig.32, it can be seen that
CLD is 26 pF.
With the addition of one retriggerable
monostable (e.g. “123”, “423” or
“4538”) a steady state LOW and
HIGH indication can be obtained, as
shown in Fig.33.
December 1990
Fig.33 Steady state signal for lock indication.
35
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PLL design example
The characteristics equation is:
The frequency synthesizer, used in the design example
shown in Fig.34, has the following parameters:
1 + H (s) × G (s) = 0.
This results in:
Kp × Kv × Kn
2 1 + Kp × Kv × Kn × τ2
s + ----------------------------------------------------- s + -------------------------------- = 0.
( τ1 + τ2)
( τ1 + τ2)
Output frequency: 2 MHz to 3 MHz
frequency steps : 100 kHz
settling time
: 1 ms
overshoot
: < 20%
The natural frequency ωn is defined as follows:
˙
Kp × Kv × Kn
ω n = -------------------------------- .
( τ1 + τ2)
The open-loop gain is H (s) x G (s) = Kp × Kf × Ko × Kn.
Where:
Kp
=
phase comparator gain
Kf
=
low-pass filter transfer gain
Ko
=
Kv/s VCO gain
Kn
=
1/n divider ratio
and the damping value ζ is defined as follows:
1 + Kp × Kv × Kn × τ2
1
ζ = ---------- × ----------------------------------------------------- .
2ω n
τ1 + τ2
The overshoot and settling time percentages are now used
to determine ωn. From Fig.35 it can be seen that the
damping ratio ζ = 0.8 will produce an overshoot of less
than 20% and settle to within 5% at ωnt = 4.5. The required
settling time is 1 ms. This results in:
3
5
5
ω n = --- = --------------- = 5 × 10 r/s.
t
0.001
The programmable counter ratio Kn can be found as
follows:
f out
2 MHz
N min. = ---------- = ---------------------- = 20
f step
100 kHz
f out
3 MHz
N max. = ---------- = ---------------------- = 30
f step
100 kHz
Rewriting the equation for natural frequency results in:
Kp × Kv × Kn
( τ 1 + τ 2 ) = -------------------------------.
2
ωn
The VCO is set by the values of R1, R2 and C1,
R2 = 10 kΩ (adjustable). The values can be determined
using the information in the section “DESIGN
CONSIDERATIONS”.
With fo = 2.5 MHz and fL = 500 kHz this gives the following
values (VCC = 5.0 V):
R1 = 10 kΩ
R2 = 10 kΩ
C1 = 500 pF
The maximum overshoot occurs at Nmax.:
6
0.4 × 2 × 10
( τ 1 + τ 2 ) = -------------------------------- = 0.0011 s.
2
5000 × 30
When C2 = 470 nF, then
( τ1 + τ2) × 2 × ωn × ζ – 1
R4 = ---------------------------------------------------------------- = 790 Ω.
Kp × Kv × Kn
The VCO gain is:
2f L × 2 × π
6
1 MHz
K V = --------------------------------------------- = = ----------------- × 2π ≈ 2 × 10 r/s/v
3.2
0.9 – ( V CC – 0.9 )
R3 is calculated using the damping ratio equation:
τ1
R3 = ------- – R4 = 2 kΩ.
C2
The gain of the phase comparator is:
V CC
= 0.4 V/r.
K p = -----------4×π
The transfer gain of the filter is given by:
1 + τ2 s
K f = -----------------------------------1 + ( τ1 + τ2) s
Where:
τ 1 = R3C2 and τ 2 = R4C2.
December 1990
36
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.34 Frequency synthesizer.
Note
For an extensive description and application example please refer to application note ordering number
9398 649 90011.
Also available a computer design program for PLL’s ordering number 9398 961 10061.
MGA959
1.6
∆ ω e (t)
∆ ω e /ω n
−0.6
ζ = 0.3
1.4
−0.4
0.5
0.707
1.0
−0.2
1.2
∆ Φe (t)
∆ Φe /ω n
ζ = 5.0
1.0
0
ζ = 2.0
0.8
0.2
0.6
0.4
0.4
0.6
0.2
0.8
0
0
1
2
3
4
5
6
7
ω nt
8
1.0
Fig.35 Type 1, second order frequency step response.
Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with
an oscilloscope by monitoring pin 9 of the VCO. The average frequency response, as calculated by the Laplace method,
is found experimentally by smoothing this voltage at pin 9 with a simple RC filter, whose time constant is long compared
to the phase detector sampling rate but short compared to the PLL response time.
December 1990
37
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.36 Frequency compared to the time response.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
38
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