74LVC2G34GN

74LVC2G34 Dual buffer gate Rev. 5 — 2 September 2010 Product data sheet 1. General description The 74LVC2G34 provides two buffers. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C. NXP Semiconductors 74LVC2G34 Dual buffer gate 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC2G34GW 74LVC2G34GV 74LVC2G34GM 74LVC2G34GF 74LVC2G34GN 74LVC2G34GS −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name SC-88 TSOP6 XSON6 XSON6 XSON6 XSON6 Description plastic surface-mounted package; 6 leads plastic surface-mounted package (TSOP6); 6 leads Version SOT363 SOT457 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm SOT1115 SOT1202 4. Marking Table 2. Marking Marking code[1] YA Y34 YA YA YA YA Type number 74LVC2G34GW 74LVC2G34GV 74LVC2G34GM 74LVC2G34GF 74LVC2G34GN 74LVC2G34GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 6 1 1 6 3 2A 2Y 4 3 1 4 mnb064 A Y 001aac536 mnb063 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 2 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 6. Pinning information 6.1 Pinning 74LVC2G34 74LVC2G34 1A GND 1 2 6 5 1Y GND VCC 2A 2A 3 001aab676 1A 1 6 1Y 1A GND 74LVC2G34 1 2 3 6 5 4 1Y VCC 2Y 2 5 VCC 3 4 2Y 2A 4 2Y 001aab677 001aag030 Transparent top view Transparent top view Fig 4. Pin configuration SOT363 and SOT457 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Symbol 1A GND 2A 2Y VCC 1Y Pin description Pin 1 2 3 4 5 6 Description data input ground (0 V) data input data output supply voltage data output 7. Functional description Table 4. Input nA L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output nY L H 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 3 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Ptot Tstg [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current total power dissipation storage temperature Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [1][2] [1][2] Max +6.5 +6.5 ±50 VCC + 0.5 +6.5 ±50 100 250 +150 Unit V mA V mA V V mA mA mA mW °C VO > VCC or VO < 0 V Active mode Power-down mode VO = 0 V to VCC −0.5 −0.5 −100 Tamb = −40 °C to +125 °C [3] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For SC-88 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Active mode Power-down mode; VCC = 0 V Conditions Min 1.65 0 0 0 −40 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V °C ns/V ns/V 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 4 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −100 μA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 100 μA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF input leakage current power-off leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VCC = 0 V; VI or VO = 5.5 V −40 °C to +85 °C Min 0.65VCC 1.7 2.0 0.7VCC VCC − 0.1 1.2 1.9 2.2 2.3 3.8 Typ[1] ±0.1 ±0.1 Max 0.35VCC 0.7 0.8 0.3VCC 0.10 0.45 0.30 0.40 0.55 0.55 ±5 ±10 −40 °C to +125 °C Min 0.65VCC 1.7 2.0 0.7VCC VCC − 0.1 0.95 1.7 1.9 2.0 3.4 Max 0.7 0.8 0.3VCC 0.10 0.70 0.45 0.60 0.80 0.80 ±20 ±20 V V V V V V V V V V V V V V V V V V V μA μA Unit 0.35VCC V ICC ΔICC CI supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V additional per pin; VCC = 2.3 V to 5.5 V; supply current VI = VCC − 0.6 V; IO = 0 A input capacitance VCC = 3.3 V; VI = GND to VCC - 0.1 5 2.5 10 500 - - 40 5000 - μA μA pF [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 5 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 3.8 2.4 2.5 2.2 1.9 20 Max 8.6 4.4 5.0 4.1 3.2 - −40 °C to +125 °C Min 1.0 0.5 0.5 0.5 0.5 Max 10.8 5.5 6.3 5.1 4.0 - Unit propagation delay nA to nY; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 0.5 0.5 0.5 0.5 [3] ns ns ns ns ns pF CPD power dissipation capacitance VI = GND to VCC; VCC = 3.3 V - [1] [2] [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI nA input GND tPLH VOH nY output VOL mnb072 VM VM tPHL VM VM Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The data input (nA) to output (nY) propagation delays 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 6 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate Table 9. VCC Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 10. VCC Test circuit for measuring switching times Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 7 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 13. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 9. 74LVC2G34 Package outline SOT363 (SC-88) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 8 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate Plastic surface-mounted package (TSOP6); 6 leads SOT457 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 c 1 2 3 Lp e bp wM B detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT457 REFERENCES IEC JEDEC JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 10. Package outline SOT457 (TSOP6) 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 9 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 11. Package outline SOT886 (XSON6) 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 10 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 12. Package outline SOT891 (XSON6) 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 11 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115 1 2 b 3 (4×)(2) L1 e L 6 e1 5 e1 4 (6×)(2) A1 A D E terminal 1 index area 0 Dimensions Unit mm A(1) A1 b D E e e1 0.3 L L1 0.5 scale 1 mm max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1115 References IEC JEDEC JEITA European projection sot1115_po Issue date 10-04-02 10-04-07 Fig 13. Package outline SOT1115 (XSON6) 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 12 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202 1 2 b 3 (4×)(2) L L1 e 6 e1 5 e1 4 (6×)(2) A1 A D E terminal 1 index area 0 Dimensions Unit mm A(1) A1 b D E e e1 L L1 0.5 scale 1 mm max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1202 References IEC JEDEC JEITA European projection sot1202_po Issue date 10-04-02 10-04-06 Fig 14. Package outline SOT1202 (XSON6) 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 13 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 14. Abbreviations Table 11. Acronym DUT ESD HBM MM TTL Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 12. Revision history Release date 20100902 Data sheet status Product data sheet Change notice Supersedes 74LVC2G34 v.4 Document ID 74LVC2G34 v.5 Modifications: 74LVC2G34 v.4 74LVC2G34 v.3 74LVC2G34 v.2 74LVC2G34 v.1 • • Added type number 74LVC2G34GN (SOT1115/XSON6 package). Added type number 74LVC2G34GS (SOT1202/XSON6 package). Product data sheet Product data sheet Product specification Product specification 74LVC2G34 v.3 74LVC2G34 v.2 74LVC2G34 v.1 - 20070720 20070321 20040910 20030725 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 14 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 15 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 2 September 2010 16 of 17 NXP Semiconductors 74LVC2G34 Dual buffer gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 September 2010 Document identifier: 74LVC2G34