74LVC544APW,118

74LVC544A Octal D-type registered transceiver; inverting; 3-state Rev. 4 — 18 December 2012 Product data sheet 1. General description The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch enable inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for each register to permit independent control of input and output in either direction of the data flow. The 74LVC544A contains eight D-type latches, with separate inputs and controls for each set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display the data present at the outputs of the A latches. 2. Features and benefits         5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction Supports partial power-down applications; inputs/outputs are high-impedance when VCC = 0 V  Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V)  JESD8-C/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Specified from 40 C to +85 C and 40 C to +125 C 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC544AD 40 C to +125 C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74LVC544ADB 40 C to +125 C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74LVC544APW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 4. Functional diagram 2 23 1 13 11 14 3 A0 B0 22 4 A1 B1 21 5 A2 B2 20 6 A3 B3 19 7 A4 B4 18 8 A5 B5 17 9 A6 B6 16 10 A7 B7 15 2 OEBA 13 OEAB 11 EAB 23 EBA 14 LEAB 1 LEBA 3 1EN3 G1 1C5 2EN4 G2 2C6 3 6D Logic symbol 74LVC544A Product data sheet 22 4 4 21 5 20 6 19 7 18 8 17 9 16 10 15 001aaa783 001aaa782 Fig 1. 5D Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 2 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state OEBA EBA LEBA OEAB EAB LEAB LE D An Bn LE D 8 identical channels 001aaa784 To 7 other channels Fig 3. Logic diagram 5. Pinning information 5.1 Pinning LEBA 1 24 VCC OEBA 2 23 EBA A0 3 22 B0 A1 4 21 B1 A2 5 20 B2 A3 6 A4 7 A5 8 17 B5 A6 9 16 B6 A7 10 15 B7 19 B3 544 18 B4 14 LEAB EAB 11 13 OEAB GND 12 001aaa780 Fig 4. Pin configuration for SO24 and (T)SSOP24 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 3 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description LEBA 1 B to A latch enable input (active LOW) OEBA 2 B to A output enable input (active LOW) A0 3 A data input or output A1 4 A data input or output A2 5 A data input or output A3 6 A data input or output A4 7 A data input or output A5 8 A data input or output A6 9 A data input or output A7 10 A data input or output EAB 11 A to B enable input (active LOW) GND 12 ground (0 V) OEAB 13 A to B output enable input (active LOW) LEAB 14 A to B latch enable input (active LOW) B7 15 B data output or input B6 16 B data output or input B5 17 B data output or input B4 18 B data output or input B3 19 B data output or input B2 20 B data output or input B1 21 B data output or input B0 22 B data output or input EBA 23 B to A enable input (active LOW) VCC 24 supply voltage 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 4 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 6. Functional description Table 3. Function table[1] Operating mode Input Output OEAB, OEBA EAB, EBA LEAB, LEBA An, Bn Bn, An Disabled H X X X Z X H X X Z Disabled plus latch L  L h Z L  L l Z Latch plus display L L  h L L L  l H Transparent L L L H L L L L L H L L H X NC Hold (do nothing) [1] XX = AB for A to B direction and BA for B to A direction H = HIGH voltage level L = LOW voltage level h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB and EBA l = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB and EBA X = don’t care  = LOW to HIGH level transition NC = no change Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V VI input voltage IOK output clamping current VO > VCC or VO < 0 V - 50 mA VO output voltage output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA IO output current ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot VO = 0 V to VCC Tamb = 40 C to +125 C [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO24 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. [3] For (T)SSOP24 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 5 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions functional VI input voltage VO output voltage Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 40 C to +85 C Conditions VCC = 1.2 V Product data sheet Min Max Min Max Unit 1.08 - - 1.08 - V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V 0.12 V VCC = 1.65 V to 1.95 V VCC = 1.2 V - - 0.12 - VCC = 1.65 V to 1.95 V - - 0.35  VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC  0.2 - - VCC  0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V 0.35  VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A input leakage VCC = 3.6 V; current VI = 5.5 V or GND 74LVC544A 40 C to +125 C Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 6 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions [2] 40 C to +125 C Unit Min Typ[1] Max Min Max - 0.1 10 - 20 A IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND; IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF CI/O input/output capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 4.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] For I/O ports the parameter IOZ includes the input leakage current. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tpd 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max - 17 - - - ns VCC = 1.65 V to 1.95 V 1.0 7.4 14.9 1.0 17.1 ns VCC = 2.3 V to 2.7 V 1.0 3.9 7.8 1.0 9.0 ns VCC = 2.7 V 1.5 3.9 7.5 1.5 9.5 ns VCC = 3.0 V to 3.6 V 1.0 3.3 6.5 1.0 8.5 ns - 19 - - - ns VCC = 1.65 V to 1.95 V 1.5 7.5 17.5 1.5 20.2 ns VCC = 2.3 V to 2.7 V 1.0 3.9 9.0 1.0 10.4 ns propagation An to Bn; Bn to An; see Figure 5 delay VCC = 1.2 V [2] LEBA to An; LEAB to Bn; see Figure 6 VCC = 1.2 V 74LVC544A Product data sheet VCC = 2.7 V 1.5 4.3 8.5 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.0 3.3 7.5 1.0 9.5 ns All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 7 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter 40 C to +85 C Conditions Min ten enable time OEBA to An; OEAB to Bn; see Figure 8 Typ[1] Max 40 C to +125 C Unit Min Max [2] - 18 - - - ns VCC = 1.65 V to 1.95 V VCC = 1.2 V 1.7 7.5 19.4 1.7 22.4 ns VCC = 2.3 V to 2.7 V 1.5 4.2 10.7 1.5 12.3 ns VCC = 2.7 V 1.5 4.3 9.5 1.5 12.0 ns VCC = 3.0 V to 3.6 V 1.0 3.4 8.5 1.0 11.0 ns - 20 - - - ns VCC = 1.65 V to 1.95 V 1.9 8.1 20.4 1.9 23.5 ns VCC = 2.3 V to 2.7 V 1.5 4.5 11.2 1.5 12.9 ns VCC = 2.7 V 1.5 4.6 9.9 1.5 12.5 ns 1.0 3.6 8.9 1.0 11.5 ns EBA to An; EAB to Bn; see Figure 8 VCC = 1.2 V VCC = 3.0 V to 3.6 V tdis disable time OEBA to An; OEAB to Bn; see Figure 8 VCC = 1.2 V [2] - 8.0 - - - ns VCC = 1.65 V to 1.95 V 2.8 5.0 11.2 2.8 13.0 ns VCC = 2.3 V to 2.7 V 1.0 2.8 6.4 1.0 7.4 ns VCC = 2.7 V 1.5 3.6 7.5 1.5 9.5 ns VCC = 3.0 V to 3.6 V 1.0 3.3 6.5 1.0 8.5 ns - 9.0 - - - ns 3.0 5.1 12.0 3.0 13.8 ns EBA to An; EAB to Bn; see Figure 8 VCC = 1.2 V VCC = 1.65 V to 1.95 V tW tsu th pulse width set-up time hold time 74LVC544A Product data sheet VCC = 2.3 V to 2.7 V 1.0 2.9 6.8 1.0 7.9 ns VCC = 2.7 V 1.5 3.7 7.9 1.5 10.0 ns VCC = 3.0 V to 3.6 V 1.0 3.4 6.9 1.0 9.0 ns LEXX LOW; see Figure 6 VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 3.0 - - 3.0 - ns VCC = 2.7 V 2.0 - - 2.0 - ns VCC = 3.0 V to 3.6 V 2.0 0.9 - 2.0 - ns VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 2.0 - - 2.0 - ns VCC = 3.0 V to 3.6 V 2.0 0.5 - 2.0 - ns VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns An, Bn to LEXX, EXX; see Figure 7 An, Bn to LEXX, EXX; see Figure 7 VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V 3.0 1.5 - 3.0 - ns All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 8 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter 40 C to +85 C Conditions tsk(o) output skew VCC = 3.0 V to 3.6 V time [3] CPD power VI = GND to VCC dissipation VCC = 1.65 V to 1.95 V capacitance VCC = 2.3 V to 2.7 V [4] VCC = 3.0 V to 3.6 V 40 C to +125 C Unit Min Typ[1] Max Min Max - - 1.0 - 1.5 ns - 8.1 - - - pF - 11.8 - - - pF - 15.1 - - - pF [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 11. Waveforms VI An, Bn input VM GND tPHL tPLH VOH Bn, An output VM VOL 001aaa785 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Input (An, Bn) to output (Bn, An) propagation delays 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 9 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state VI LEXX input VM GND tW tPHL tPLH VOH An, Bn output VM VOL 001aaa786 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Latch enable input (LEXX) pulse width and latch enable input to output (An, Bn) propagation delays VI VM An, Bn input GND th th tsu tsu VI LEXX, EXX input VM GND 001aaa787 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance Fig 7. Data set-up and hold times for the inputs (An, Bn) to LEXX and EXX inputs 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 10 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state VI OEXX, EXX input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aaa788 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 8. 3-state enable and disable times Measurement points Supply voltage Input VCC VI VM VM VX VY 1.2 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 1.65 V to 1.95 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 2.3 V to 2.7 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 74LVC544A Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 11 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 9. Load circuitry for switching times Test data Supply voltage Input VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC  2 ns 30 pF 1 k open 2  VCC GND 1.65 V to 1.95 V VCC  2 ns 30 pF 1 k open 2  VCC GND 2.3 V to 2.7 V VCC  2 ns 30 pF 500  open 2  VCC GND 2.7 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 74LVC544A Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 12 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT137-1 (SO24) 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 13 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT340-1 (SSOP24) 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 14 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT355-1 (TSSOP24) 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 15 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC544A v.4 20121218 Product data sheet - 74LVC544A v.3 Modifications: 74LVC544A v.3 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7,Table 8 and Table 9: values added for lower voltage ranges. 20040511 Product specification - 74LVC544A v.2 74LVC544A v.2 19980729 Product specification - 74LVC544A v.1 74LVC544A v.1 19981110 Product specification - - 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 16 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC544A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 17 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC544A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 18 of 19 74LVC544A NXP Semiconductors Octal D-type registered transceiver; inverting; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 December 2012 Document identifier: 74LVC544A