74LVC573APW,118

INTEGRATED CIRCUITS 74LVC573A Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) Product specification
     1998 Jul 29 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC573A The 74LVC573A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface with TTL levels • High impedance when VCC = 0V • Flow-through pin-out architecture The ’573A’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one setup time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. DESCRIPTION The ’573A’ is functionally identical to the ’373A’, but the ’373A’ has a different pin arrangement. The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. QUICK REFERENCE DATA SYMBOL tPHL/tPLH PARAMETER CONDITIONS Propagation delay Dn to Qn; LE to Qn CL = 50pF VCC = 3.3V CI Input capacitance CPD Power dissipation capacitance per latch TYPICAL 4.3 4.6 Notes 1 and 2 UNIT ns 5.0 pF 20 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi +
(CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V;
(CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC573A D 74LVC573A D SOT163-1 20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC573A DB 74LVC573A DB SOT339-1 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC573A PW 7LVC573APW DH SOT360-1 PACKAGES 1998 Jul 29 2 853-1862 19804 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) PIN DESCRIPTION 74LVC573A LOGIC SYMBOL (IEEE/IEC) PIN NUMBER SYMBOL 1 OE FUNCTION 11 Output enable input (active-Low) C1 2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs 1 19, 18, 17, 16, 15, 14, 13, 12 Q0-Q7 Data outputs 2 10 GND Ground (0V) 3 18 11 LE Latch enable input (active-High) 4 17 20 VCC Positive supply voltage 5 16 6 15 7 14 8 13 9 12 PIN CONFIGURATION 1D 19 OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 2 D0 D4 6 15 Q4 3 D1 Q1 18 D5 7 14 Q5 4 D2 Q2 17 D6 8 13 Q6 5 D3 D7 9 12 Q7 6 D4 11 LE 7 D5 8 GND 10 SA00397 FUNCTIONAL DIAGRAM SA00395 LOGIC SYMBOL 2 D0 3 4 OE Q0 19 D1 Q1 18 D2 Q2 17 5 D3 Q3 16 6 D4 Q4 15 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LE Q0 19 Q3 16 Q4 15 Q5 14 D6 Q6 13 9 D7 Q7 12 11 LE 1 OE LATCH 1 to 8 3-State OUTPUTS SA00398 1 11 SA00396 1998 Jul 29 EN1 3 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC573A LOGIC DIAGRAM D1 D0 D D2 D Q D3 D Q D4 D Q D5 D Q D6 D Q D7 D Q D Q Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SA00399 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES H h L l X Z INTERNAL LATCHES OE LE Dn Enable and read register (transparent mode) L L H H L H L H L H Latch and read register L L L L l h L H L H Latch register and disable outputs H H L L l h L H Z Z = HIGH voltage level = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition = Don’t care = High impedance OFF-state 1998 Jul 29 4 Q0 to Q7 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC573A RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VI VO PARAMETER CONDITIONS UNIT MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC Input voltage range 0 5.5 DC output voltage range; output HIGH or LOW state 0 VCC DC output voltage range; output 3-State 0 5.5 –40 +85 °C 0 0 20 10 ns/V V Tamb Operating ambient temperature range in free-air tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC CONDITIONS UNIT –0.5 to +6.5 V IIK DC input diode current VI 0 –50 mA VI DC input voltage Note 2 –0.5 to +6.5 V IOK DC output diode current VO VCC or VO  0
50 mA DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5 DC output voltage; output 3-State Note 2 –0.5 to 6.5 DC output source or sink current VO = 0 to VCC VO IO IGND, ICC Tstg PTOT DC supply voltage RATING DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K V
50 mA
100 mA –65 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jul 29 5 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC573A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 V VCC = 1.2V GND V VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*0.8 VCC V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA II Input leakage current2 UNIT MAX V 0.55 VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND "0 1 "0.1 "5 µA IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND 0.1 "10 µA Ioff Power off leakage supply VCC = 0.0V; VI or VO = 5.5V 0.1 "10 µA ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA ∆ICC NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state. AC CHARACTERISTICS GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ tW tSU th PARAMETER Propagation delay Dn to Qn Propagation delay LE to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn LE pulse width HIGH Setup time Dn to LE Hold time Dn to LE WAVEFORM VCC = 3.3V ±0.3V VCC = 1.2V UNIT TYP1 MAX MIN MAX TYP 1, 5 1.5 4.3 6.2 1.5 7.2 19 ns 2, 5 1.5 4.6 6.5 1.5 7.5 21 ns 2, 5 1.5 3.8 7.5 1.5 8.5 17 ns 3, 5 1.5 3.5 6.0 1.5 6.5 15 ns 2 3.2 1.6 – 3.2 – – ns 4 1.7 0.3 – 1.7 – – ns 4 1.4 0.2 – 1.5 – – ns NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Jul 29 VCC = 2.7V MIN 6 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC573A ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ AC WAVEFORMS VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V VI Dn INPUT VM GND th th tSU tSU VI VI INPUT LE INPUT VM VM GND GND tPHL VOH tPLH OUTPUT NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM SW00073 Waveform 4. Data setup and hold times for the Dn input to the LE input. VOL SY00041 Waveform 1. Input (Dn) to output (Qn) propagation delays. TEST CIRCUIT S1 VCC VI 2