ADC0801S040

ADC0801S040 Single 8 bits ADC, up to 40 MHz Rev. 02 — 18 August 2008 Product data sheet 1. General description The ADC0801S040 is an 8-bit universal analog-to-digital converter (ADC) for video and general purpose applications. It converts the analog input signal from 2.7 V to 5.5 V into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are CMOS/Transistor-Transistor Logic (TTL) compatible. A sleep mode allows reduction of the device power consumption to 4 mW. 2. Features I I I I I I I I I I I 8-bit resolution Operation between 2.7 V and 5.5 V Sampling rate up to 40 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) CMOS/TTL compatible digital inputs and outputs External reference voltage regulator Power dissipation only 30 mW (typical value) Low analog input capacitance, no buffer amplifier required Sleep mode (4 mW) No sample-and-hold circuit required 3. Applications I I I I I Video data digitizing Camera Camcorder Radio communication Car alarm system NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 4. Quick reference data Table 1. Quick reference data VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol VDDA VDDD VDDO ∆VDD IDDA IDDD IDDO INL DNL fclk(max) Parameter analog supply voltage digital supply voltage output supply voltage supply voltage VDDA − VDDD difference VDDD − VDDO analog supply current digital supply current output supply current integral non-linearity differential non-linearity maximum clock frequency total power dissipation VDDA = VDDD = VDDO = 3.3 V fclk = 40 MHz; ramp input; CL = 20 pF ramp input; see Figure 6 ramp input; see Figure 7 Conditions Min 2.7 2.7 2.5 −0.2 −0.2 40 Typ 3.3 3.3 3.3 4 5 1 ±0.5 ±0.25 Max 5.5 5.5 5.5 +0.2 +2.25 6 8 2 ±0.75 ±0.5 Unit V V V V V mA mA mA LSB LSB MHz Ptot - 30 53 mW 5. Ordering information Table 2. Ordering information Package Name ADC0801S040TS SSOP20 Description plastic shrink small outline package; 20 leads; body width 4.4 mm Version SOT266-1 Type number ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 2 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 6. Block diagram VDDA 5 CLK 1 VDDD 3 CLOCK DRIVER RT 10 2 SLEEP ADC0801S040 19 D7 MSB 18 D6 17 D5 Rlad 16 D4 analog voltage input VI 9 ANALOG - TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS 15 D3 14 D2 13 D1 12 D0 20 LSB data outputs RM 8 RB 7 VDDO 6 VSSA analog ground 11 VSSO output ground 4 VSSD digital ground 014aaa495 Fig 1. Block diagram ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 3 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 7. Pinning information 7.1 Pinning CLK SLEEP VDDD VSSD VDDA VSSA RB RM VI 1 2 3 4 5 6 7 8 9 20 VDDO 19 D7 18 D6 17 D5 16 D4 ADC0801S 15 D3 040TS 14 D2 13 D1 12 D0 11 VSSO 014aaa494 RT 10 Fig 2. Pin configuration 7.2 Pin description Table 3. Symbol CLK SLEEP VDDD VSSD VDDA VSSA RB RM VI RT VSSO D0 D1 D2 D3 D4 D5 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description clock input sleep mode input digital supply voltage (2.7 V to 5.5 V) digital ground analog supply voltage (2.7 V to 5.5 V) analog ground reference voltage BOTTOM input reference voltage MIDDLE analog input voltage reference voltage TOP input output stage ground data output; bit 0 (Least Significant Bit (LSB)) data output; bit 1 data output; bit 2 data output; bit 3 data output; bit 4 data output; bit 5 ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 4 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz Pin description …continued Pin 18 19 20 Description data output; bit 6 data output; bit 7 (Most Significant Bit (MSB)) positive supply voltage for output stage (2.7 V to 5.5 V) Table 3. Symbol D6 D7 VDDO 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA VDDD VDDO ∆VDD Parameter analog supply voltage digital supply voltage output supply voltage supply voltage difference VDDA − VDDD; VDDD − VDDO; VDDA − VDDO referenced to VSSA Conditions [1] [1] [1] Min −0.3 −0.3 −0.3 −0.1 Max +7.0 +7.0 +7.0 +4.0 Unit V V V V VI Vi(clk)(p-p) IO Tstg Tamb Tj [1] input voltage −0.3 −55 −20 - +7.0 VDDD 10 +150 +75 150 V V mA °C °C °C peak-to-peak clock input voltage referenced to VSSD output current storage temperature ambient temperature junction temperature The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply voltage ∆VDD remains as indicated. 9. Thermal characteristics Table 5. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Condition in free air Value 120 Unit K/W 10. Characteristics Table 6. Characteristics VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol Supplies VDDA VDDD VDDO ADC0801S040_2 Parameter analog supply voltage digital supply voltage output supply voltage Conditions Min 2.7 2.7 2.5 Typ 3.3 3.3 3.3 Max 5.5 5.5 5.5 Unit V V © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 5 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz Table 6. Characteristics …continued VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol ∆VDD IDDA IDDD IDDO Ptot Inputs Clock input CLK (Referenced to VSSD)[1] VIL VIH IIL IIH Zi Ci VIL VIH IIL IIH IIL IIH Zi Ci VRB VRT Vref(dif) Iref Rlad TCRlad Voffset Vi(a)(p-p) LOW-level input voltage HIGH-level input voltage VDDD ≤ 3.6 V VDDD > 3.6 V LOW-level input current input impedance input capacitance LOW-level input voltage HIGH-level input voltage VDDD ≤ 3.6 V VDDD > 3.6 V LOW-level input current VIL = 0.3 VDDD HIGH-level input current VIH = 0.7 VDDD LOW-level input current input impedance input capacitance voltage on pin RB voltage on pin RT differential reference voltage reference current ladder resistance ladder resistor temperature coefficient offset voltage peak-to-peak analog input voltage BOTTOM TOP [2] [2] [3] Parameter Conditions VDDD − VDDO Min −0.2 −0.2 - Typ 4 5 1 30 Max +0.2 +2.25 6 8 2 53 Unit V V mA mA mA mW supply voltage difference VDDA − VDDD analog supply current digital supply current output supply current total power dissipation fclk = 40 MHz; ramp input; CL = 20 pF VDDA = VDDD = VDDO = 3.3 V - 0 0.6 VDDD 0.7 VDDD −1 0 0.6 VDDD 0.7 VDDD −1 1.1 VRT ≤ VDDA VRT − VRB 2.7 1.5 1.4 0 4 3 0 9 20 2 1.2 3.3 2.1 0.95 2.2 4092 170 170 1.76 0.3 VDDD VDDD VDDD +1 5 0.3 VDDD VDDD VDDD +1 VDDA 2.7 2.4 V V V µA µA kΩ pF V V V µA µA µA µA kΩ pF V V V mA kΩ mΩ/K mV mV V Vclk = 0.3 VDDD fclk = 40 MHz fclk = 40 MHz HIGH-level input current Vclk = 0.7 VDDD Input SLEEP (Referenced to VSSD); see Table 8 Analog input VI (Referenced to VSSA) VI = VRB fi = 1 MHz fi = 1 MHz HIGH-level input current VI = VRT Reference voltages for the resistor ladder; see Table 7 ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 6 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz Table 6. Characteristics …continued VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol VOL VOH IOZ fclk(max) tw(clk)H tw(clk)L Linearity INL DNL Bandwidth B bandwidth full-scale sine wave 75 % full-scale sine wave 50 % full-scale sine wave small signal at mid scale; Vi = ±10 LSB at code 128 Input set response; see Figure 8[5] ts(LH) ts(HL) LOW to HIGH settling time HIGH to LOW settling time full-scale square wave full-scale square wave 3 3 5 5 ns ns [4] Parameter LOW-level output voltage HIGH-level output voltage Conditions IO = 1 mA IO = −1 mA Min 0 VDDO − 0.5 −20 40 9 9 Typ - Max 0.5 VDDO +20 - Unit V V µA MHz ns ns Digital outputs D7 to D0 and IR (Referenced to VSSD) OFF-state output current 0.4 V < VO < VDDO maximum clock frequency HIGH clock pulse width LOW clock pulse width Clock input CLK; see Figure 4[1] Analog signal processing (fclk = 40 MHz) integral non-linearity differential non-linearity ramp input; see Figure 6 ramp input; see Figure 7 ±0.5 ±0.25 10 13 20 350 ±0.75 ±0.5 LSB LSB MHz MHz MHz MHz Harmonics; see Figure 9[6] THD S/N total harmonic distortion fi = 4.43 MHz 9[6] without harmonics; fi= 4.43 MHz fi = 300 MHz fi = 4.43 MHz Differential gain[7] Gdif differential gain PAL modulated ramp 1.5 % 47 dB signal-to-noise ratio −50 dB Signal-to-Noise ratio; see Figure Effective bits; see Figure 9[6] ENOB effective number of bits 7.8 7.3 bits bits ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 7 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz Table 6. Characteristics …continued VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol Differential ϕdif td(s) th(o) td(o) Parameter phase[7] differential phase sampling delay time output hold time output delay time VDDO = 4.75 V VDDO = 3.15 V VDDO = 2.7 V 3-state output delay times; see Figure 5 tdHZ tdZL tdZH tdLZ active HIGH to float delay time float to active LOW delay time float to active HIGH delay time active LOW to float delay time 14 16 16 14 18 20 20 18 ns ns ns ns PAL modulated ramp 5 8 8 8 0.25 12 17 18 5 15 20 21 deg ns ns ns ns ns Conditions Min Typ Max Unit Timing (fclk = 40 MHz; CL = 20 pF); see Figure 4[8] [1] [2] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. Analog input voltages producing code 0 up to and including code 255: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 °C. b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 255 at Tamb = 25 °C. To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. a) The current flowing into the resistor ladder is I = --------------------------------------- and the full-scale input range at the converter, to cover code 0 - [3] V RT – V RB R OB + R L + R OT to 255 is V I = R L × I L = --------------------------------------- × ( V RT + V RB ) = 0.838 × ( V RT – V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio --------------------------------------will be kept reasonably constant from device to device. Consequently variation of the output codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] [5] [6] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSB, nor any significant attenuation is observed in the reconstructed signal. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise ratio: S/N = ENOB × 6.02 + 1.76 dB. Measurement carried out using video analyzer VM700A, where video analog signal is reconstructed through a DAC. Output data acquisition: the output data is available after the maximum delay time of td(o). © NXP B.V. 2008. All rights reserved. RL RL R OB + R L + R OT [7] [8] ADC0801S040_2 Product data sheet Rev. 02 — 18 August 2008 8 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz RT 9 ROT code 255 RL RL RM 7 RL IL Rlad RL code 0 ROB RB 6 014aaa504 Fig 3. Explanation of Table 6 Table note 3 11. Additional information relating to Table 6 Table 7. Code Underflow 0 1 ↓ 254 255 Overflow Table 8. SLEEP 1 0 Output coding and input voltage (typical values; referenced to VSSA) Vi(a)(p-p) (V) < 1.37 1.37 3.13 > 3.13 Mode selection D7 to D0 high impedance active IDDA + IDDD (typ) 1.2 mA 9 mA Binary outputs D7 to D0 00 0000 00 00 0000 00 00 0000 01 ↓ 11 11 11 10 11 11 11 11 11 11 11 11 ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 9 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz sample N sample N + 1 tw(clk)L sample N + 2 tw(clk)H CLK 50 % sample N sample N + 1 sample N + 2 VI td(s) th(o) VDDO DATA D0 to D7 DATA N−2 DATA N−1 td(o) DATA N DATA N+1 50 % 0V 014aaa508 Fig 4. Timing diagram ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 10 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz VDDD SLEEP 50 % tdHZ HIGH 90 % output data tdLZ HIGH output data LOW 10 % tdZL tdZH 50 % LOW 50 % TEST VDDD 3.3 kΩ S1 VDDD VDDD GND GND tdLZ tdZL tdHZ tdZH ADC0801S040 20 pF S1 SLEEP 014aaa496 frequency on pin SLEEP = 100 kHz. Fig 5. Timing diagram and test conditions of 3-state output delay time 0.291 A (LSB) 0.178 014aaa501 0.065 −0.047 −0.160 −0.272 0 68 136 204 codes 272 Fig 6. Typical Integral Non-Linearity (INL) performance ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 11 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 0.150 A (LSB) 0.091 014aaa502 0.032 −0.025 −0.84 −0.143 0 68 136 204 codes 272 Fig 7. Typical Differential Non-Linearity (DNL) performance ts(LH) code 255 VI code 0 5 ns 50 % ts(HL) 50 % 5 ns CLK 50 % 50 % 2 ns 2 ns 014aaa497 Fig 8. Analog input settling-time diagram ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 12 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 0 A (dB) −40 014aaa503 −80 −120 0 5.0 10.0 15.0 f (MHz) 20.0 Effective bits: 7.32; THD = −51.08 dB. Harmonic levels (dB): 2nd = −68.99; 3rd = −51.62; 4th = −66.05; 5th = −63.23; 6th = −72.79. Fig 9. Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz) VDDA VDDO D7 to D0 VI VSSO 014aaa498 VSSA 014aaa505 Fig 10. CMOS data outputs Fig 11. VI analog input VDDA VDDO RT RL RL SLEEP RM RL RL RB VSSO VSSA 014aaa499 014aaa506 Fig 12. SLEEP 3-state input ADC0801S040_2 Fig 13. RB, RM and RT inputs © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 13 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz VDDD CLK 1/ V 2 DDD VSSD 014aaa507 Fig 14. CLK input ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 14 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 12. Application information 12.1 Application diagrams CLK SLEEP VDDD VSSD VDDA VSSA RB(1) 100 nF 1 2 3 4 5 20 19 18 17 16 VDDO D7 D6 D5 D4 ADC0801S040 6 15 D3 7 8 9 10 14 13 12 11 D2 D1 D0 VSSO RM(1) 100 nF VSSA VI VSSA RT(1) 100 nF VSSA 014aaa500 The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling capacitor. (1) RB, RM, RT are decoupled to VSSA. Fig 15. Application diagram ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 15 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 13. Package outline SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 D E A X c y HE vM A Z 20 11 Q A2 pin 1 index A1 (A 3) θ Lp L A 1 e bp 10 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 θ 10 o 0 o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC MO-152 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT266-1 (SSOP20) ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 16 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 14. Revision history Table 9. Revision history Release date 20080818 Data sheet status Product data sheet Change notice Supersedes ADC0801S040_1 Document ID ADC0801S040_2 Modifications: • • • • • Corrections made to table notes in Figure 1. Corrections made to Table 3. Corrections made to symbol in Table 4. Corrections made to Table 6. Corrections made to Figure 13 Product data sheet - ADC0801S040_1 20080612 ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 17 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC0801S040_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 18 August 2008 18 of 19 NXP Semiconductors ADC0801S040 Single 8 bits ADC, up to 40 MHz 17. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional information relating to Table 6 . . . . 9 Application information. . . . . . . . . . . . . . . . . . 15 Application diagrams . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 August 2008 Document identifier: ADC0801S040_2