ADC1412D

ADC1412D series Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 03 — 6 August 2010 Preliminary data sheet 1. General description The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1412D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in Complementary Metal Oxide Semiconductor (CMOS) mode because of a separate digital output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes an SPI programmable full-scale to allow a flexible input voltage range of 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 72 dBFS SFDR, 86 dBc Sample rate up to 125 Msps Clock input divider by 2 for less jitter contribution Single 3 V supply Flexible input voltage range: 1 V to 2 V (p-p) CMOS or LVDS DDR digital outputs Pin and software compatible with ADC1212D series HVQFN64 package Input bandwidth, 600 MHz Power dissipation, 855 mW at 80 Msps Serial Peripheral Interface (SPI) Duty cycle stabilizer Fast OuT-of-Range (OTR) detection INL ± 1 LSB, DNL ± 0.5 LSB Offset binary, two’s complement, gray code Power-down and Sleep modes 3. Applications Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software defined radio NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information fs (Msps) Package Name ADC1412D125HN/C1 125 ADC1412D105HN/C1 105 ADC1412D080HN/C1 80 ADC1412D065HN/C1 65 Description Version SOT804-3 SOT804-3 SOT804-3 SOT804-3 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 × 9 × 0.85 mm HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 × 9 × 0.85 mm HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 × 9 × 0.85 mm HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 × 9 × 0.85 mm Type number 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1412D ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE OTRA INAP T/H INPUT STAGE INAM ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS CMOS: DA13 to DA0 or LVDS/DDR: DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M CMOS: DAV or LVDS/DDR: DAVP DAVM CMOS: DB13 to DB0 or LVDS/DDR: DB12_DB13_P to DB0_DB1_P DB12_DB13_M to DB0_DB1_M OTRB CLKP CLKM CLOCK INPUT STAGE AND DUTY CYCLE CONTROL OUTPUT DRIVERS INBP T/H INPUT STAGE INBM ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS ERROR CORRECTION AND DIGITAL PROCESSING SYSTEM REFERENCE AND POWER MANAGEMENT CTRL REFBT REFBB VCMB VCMA SENSE VREF REFAB REFAT 005aaa096 Fig 1. Block diagram ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 2 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 6. Pinning information 6.1 CMOS outputs selected 6.1.1 Pinning 62 SENSE 50 VDDO terminal 1 index area INAP INAM AGND VCMA REFAT REFAB AGND CLKP CLKM 1 2 3 4 5 6 7 8 9 49 VDDO 48 DA5 47 DA4 46 DA3 45 DA2 44 DA1 43 DA0 42 DAV 41 n.c. 40 DB0 39 DB1 38 DB2 37 DB3 36 DB4 35 DB5 34 DB6 33 DB7 VDDO 32 005aaa097 64 VDDA 61 VDDA 60 DECA 59 OTRA 63 VREF 58 DA13 57 DA12 56 DA11 55 DA10 54 DA9 53 DA8 DB10 28 52 DA7 DB9 29 ADC1412D HVQFN64 AGND 10 REFBB 11 REFBT 12 VCMB 13 AGND 14 INBM 15 INBP 16 VDDA 17 VDDA 18 SCLK/DFS 19 SDIO/ODS 20 CS 21 CTRL 22 DECB 23 OTRB 24 DB13 25 DB12 26 DB11 27 DB8 30 VDDO 31 Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected 6.1.2 Pin description Table 2. Symbol INAP INAM AGND VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT ADC1412D_SER Pin description (CMOS digital outputs) Pin 1 2 3 4 5 6 7 8 9 10 11 12 Type [1] I I G O O O G I I G O O Description analog input; channel A complementary analog input; channel A analog ground common-mode output voltage; channel A top reference; channel A bottom reference; channel A analog ground clock input complementary clock input analog ground bottom reference; channel B top reference; channel B © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 03 — 6 August 2010 51 DA6 3 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Pin description (CMOS digital outputs) …continued Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Type [1] O G I I P P I I/O I I O O O O O O O O P P O O O O O O O O O O O O O O O P P O O O O O O Description common-mode output voltage; channel B analog ground complementary analog input; channel B analog input; channel B analog power supply analog power supply SPI clock/data format select SPI data IO/output data standard SPI chip select control mode select regulator decoupling node; channel B out of range; channel B data output bit 13 (Most Significant Bit (MSB)); channel B data output bit 12; channel B data output bit 11; channel B data output bit 10; channel B data output bit 9; channel B data output bit 8; channel B output power supply output power supply data output bit 7; channel B data output bit 6; channel B data output bit 5; channel B data output bit 4; channel B data output bit 3; channel B data output bit 2; channel B data output bit 1; channel B data output bit 0 (Least Significant Bit (LSB)); channel B not connected data valid output clock data output bit 0 (LSB); channel A data output bit 1; channel A data output bit 2; channel A data output bit 3; channel A data output bit 4; channel A data output bit 5; channel A output power supply output power supply data output bit 6; channel A data output bit 7; channel A data output bit 8; channel A data output bit 9; channel A data output bit 10; channel A data output bit 11; channel A © NXP B.V. 2010. All rights reserved. Table 2. Symbol VCMB AGND INBM INBP VDDA VDDA SCLK/DFS SDIO/ODS CS CTRL DECB OTRB DB13 DB12 DB11 DB10 DB9 DB8 VDDO VDDO DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 n.c. DAV DA0 DA1 DA2 DA3 DA4 DA5 VDDO VDDO DA6 DA7 DA8 DA9 DA10 DA11 ADC1412D_SER All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 03 — 6 August 2010 4 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Pin description (CMOS digital outputs) …continued Pin 57 58 59 60 61 62 63 64 Type [1] O O O O P I I/O P Description data output bit 12; channel A data output bit 13 (MSB); channel A out-of-range; channel A regulator decoupling node; channel A analog power supply reference programming pin voltage reference input/output analog power supply Table 2. Symbol DA12 DA13 OTRA DECA VDDA SENSE VREF VDDA [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. 6.2 LVDS/DDR outputs selected 6.2.1 Pinning 58 DA12_DA13_M 56 DA10_DA11_M 57 DA12_DA13_P 55 DA10_DA11_P 54 DA8_DA9_M 52 DA6_DA7_M 53 DA8_DA9_P 51 DA6_DA7_P 62 SENSE 50 VDDO terminal 1 index area INAP INAM AGND VCMA REFAT REFAB AGND CLKP CLKM 1 2 3 4 5 6 7 8 9 49 VDDO 48 DA4_DA5_M 47 DA4_DA5_P 46 DA2_DA3_M 45 DA2_DA3_P 44 DA0_DA1_ M 43 DA0_DA1_P 42 DAVP 41 DAVM 40 DB0_DB1_P 39 DB0_DB1_M 38 DB2_DB3_P 37 DB2_DB3_M 36 DB4_DB5_P 35 DB4_DB5_M 34 DB6_DB7_P 33 DB6_DB7_M VDDO 32 005aaa098 64 VDDA 61 VDDA 60 DECA CS 21 59 OTRA CTRL 22 63 VREF ADC1412D HVQFN64 AGND 10 REFBB 11 REFBT 12 VCMB 13 AGND 14 INBM 15 INBP 16 VDDA 17 VDDA 18 SCLK/DFS 19 SDIO/ODS 20 DECB 23 OTRB 24 DB12_DB13_M 25 DB12_DB13_P 26 DB10_DB11_M 27 DB10_DB11_P 28 DB8_DB9_M 29 DB8_DB9_P 30 VDDO 31 Transparent top view Fig 3. Pin configuration with LVDS/DDR digital outputs selected ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 5 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 6.2.2 Pin description Table 3. Symbol Pin description (LVDS/DDR) digital outputs) Pin Type [2] O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Description differential output data DB12 and DB13 multiplexed, complement differential output data DB12 and DB13 multiplexed, true differential output data DB10 and DB11 multiplexed, complement differential output data DB10 and DB11 multiplexed, true differential output data DB8 and DB9 multiplexed, complement differential output data DB8 and DB9 multiplexed, true differential output data DB6 and DB7 multiplexed, complement differential output data DB6 and DB7 multiplexed, true differential output data DB4 and DB5 multiplexed, complement differential output data DB4 and DB5 multiplexed, true differential output data DB2 and DB3 multiplexed, complement differential output data DB2 and DB3 multiplexed, true differential output data DB0 and DB1 multiplexed, complement differential output data DB0 and DB1 multiplexed, true data valid output clock, complement data valid output clock, true differential output data DA0 and DA1 multiplexed, true differential output data DA0 and DA1 multiplexed, complement differential output data DA2 and DA3 multiplexed, true differential output data DA2 and DA3 multiplexed, complement differential output data DA4 and DA5 multiplexed, true differential output data DA4 and DA5 multiplexed, complement differential output data DA6 and DA7 multiplexed, true differential output data DA6 and DA7 multiplexed, complement differential output data DA8 and DA9 multiplexed, true differential output data DA8 and DA9 multiplexed, complement differential output data DA10 and DA11 multiplexed, true differential output data DA10 and DA11 multiplexed, complement differential output data DA12 and DA13 multiplexed, true differential output data DA12 and DA13 multiplexed, complement [1] DB12_DB13_M 25 DB12_DB13_P 26 DB10_DB11_M 27 DB10_DB11_P DB8_DB9_M DB8_DB9_P DB6_DB7_M DB6_DB7_P DB4_DB5_M DB4_DB5_P DB2_DB3_M DB2_DB3_P DB0_DB1_M DB0_DB1_P DAVM DAVP DA0_DA1_P DA0_DA1_M DA2_DA3_P DA2_DA3_M DA4_DA5_P DA4_DA5_M DA6_DA7_P DA6_DA7_M DA8_DA9_P DA8_DA9_M DA10_DA11_P 28 29 30 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 51 52 53 54 55 DA10_DA11_M 56 DA12_DA13_P 57 DA12_DA13_M 58 [1] [2] Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs (see Table 2). P: power supply; G: ground; I: input; O: output; I/O: input/output. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 6 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VO output voltage Conditions pins DA13 to DA0 and DB13 to DB0 or pins DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M, DB12_DB13_P to DB0_DB1_P and DB12_DB13_M to DB0_DB1_M Min −0.4 Max +3.9 Unit V VDDA VDDO Tstg Tamb Tj analog supply voltage output supply voltage storage temperature ambient temperature junction temperature −0.4 −0.4 −55 −40 - +3.9 +3.9 +125 +85 125 V V °C °C °C 8. Thermal characteristics Table 5. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions [1] [1] Typ 15.6 6.3 Unit K/W K/W Value for six layers board in still air with a minimum of 64 thermal via. 9. Static characteristics Table 6. Symbol Supplies VDDA VDDO IDDA IDDO analog supply voltage output supply voltage analog supply current output supply current CMOS mode LVDS DDR mode fclk = 125 Msps; fi = 70 MHz CMOS mode; fclk = 125 Msps; fi = 70 MHz LVDS DDR mode: fclk = 125 Msps; fi = 70 MHz 2.85 1.65 2.85 3.0 1.8 3.0 400 23 90 3.4 3.6 3.6 V V V mA mA mA Static characteristics[1] Parameter Conditions Min Typ Max Unit ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 7 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Table 6. Symbol P Static characteristics[1] …continued Parameter power dissipation Conditions ADC1412D125; analog supply only ADC1412D105; analog supply only ADC1412D080; analog supply only ADC1412D065; analog supply only Power-down mode Sleep mode Min Typ 1200 1100 855 795 25 80 Max Unit mW mW mW mW mW mW Clock inputs: pins CLKP and CLKM LVPECL Vi(clk)dif LVDS Vi(clk)dif SINE Vi(clk)dif LVCMOS VIL VIH VIL LOW-level input voltage HIGH-level input voltage LOW-level input voltage LOW-medium level medium-HIGH level VIH IIL IIH VIL VIH IIL IIH CI HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance 0.7VDDA −10 0 0.7VDDA −10 −50 0 0.3VDDA 0.6VDDA VDDA 4 0.3VDDA V +10 V V V V V μA μA differential clock input voltage peak-to-peak ±0.8 ±3.0 V differential clock input voltage peak-to-peak ±0.70 V differential clock input voltage peak-to-peak ±1.6 V Logic input: pin CTRL Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS 0.3VDDA V VDDA +10 +50 V μA μA pF Digital outputs, CMOS mode: pins DA13 to DA0, DB13 to DB0, OTRA, OTRB and DAV Output levels, VDDO = 3 V VOL VOH IOL IOH CO VOL ADC1412D_SER LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current output capacitance LOW-level output voltage IOL = IOH = 3-state; output level = 0 V 3-state; output level = VDDA high impedance; see Table 10 IOL = All information provided in this document is subject to legal disclaimers. OGND 0.8VDDO OGND 3 - 0.2VDDO V VDDO V μA μA pF Output levels, VDDO = 1.8 V 0.2VDDO V © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 8 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Table 6. Symbol VOH Static characteristics[1] …continued Parameter HIGH-level output voltage Conditions IOH = Min 0.8VDDO Typ Max VDDO Unit V Digital outputs, LVDS DDR mode: pins DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M, DB12_DB13_P to DB0_DB1_P, DB12_DB13_M to DB0_DB1_M, DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100 Ω VO(offset) VO(dif) CO II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) VVREF Accuracy INL DNL Eoffset EG MG(CTC) Supply PSRR [1] output offset voltage differential output voltage output capacitance input current input resistance input capacitance common-mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current voltage on pin VREF output buffer current set to 3.5 mA output buffer current set to 3.5 mA −5 - 1.2 350 5 1.5 600 0.5VDDA 0.5 to 1 ±1 ±0.5 ±2 ±0.5 +5 2 2 1 +5 +0.95 - V mV pF μA Ω pF V MHz V V μA V V LSB LSB mV % % Analog inputs: pins INAP, INAM, INBP and INBM VINAP = VINAM; VINBP = VINBM peak-to-peak 0.9 1 - Common mode output voltage: pins VCMA and VCMB I/O reference voltage: pin VREF output input integral non-linearity differential non-linearity offset error gain error channel-to-channel gain matching power supply rejection ratio 100 mV (p-p) on VDDA full scale guaranteed no missing codes 0.5 −5 −0.95 - - 35 - dBc Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 9 of 40 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Symbol Dynamic characteristics[1] Parameter Conditions ADC1412D065 Min Analog signal processing α2H second harmonic fi = 3 MHz level fi = 30 MHz fi = 70 MHz fi = 170 MHz α3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-to-noise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 87 86 85 82 86 85 84 81 85 84 83 80 11.7 11.6 11.5 11.4 72.1 71.3 70.7 70.2 86 85 84 81 87 86 85 82 86 85 84 81 85 84 83 80 11.7 11.5 11.5 11.4 72.0 71.2 70.7 70.1 86 85 84 81 86 86 84 81 85 85 83 80 84 84 82 79 11.6 11.5 11.4 11.3 71.8 71.2 70.6 70.0 85 85 83 80 88 87 85 83 87 86 84 82 86 85 83 81 11.6 11.5 11.4 11.3 71.4 71.1 70.5 69.9 87 86 84 82 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bit bit bit bit dBFS dBFS dBFS dBFS dBc dBc dBc dBc Typ Max ADC1412D080 Min Typ Max ADC1412D105 Min Typ Max ADC1412D125 Min Typ Max Unit Preliminary data sheet Rev. 03 — 6 August 2010 10 of 40 ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors CMOS or LVDS DDR digital outputs ADC1412D series SFDR spurious-free dynamic range fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 7. Symbol IMD Dynamic characteristics[1] …continued Parameter Intermodulation distortion Conditions fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz αct(ch) [1] Preliminary data sheet Rev. 03 — 6 August 2010 11 of 40 ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1412D065 Min Typ 89 88 87 84 100 Max - ADC1412D080 Min Typ 89 88 87 85 100 Max - ADC1412D105 Min Typ 88 88 86 83 100 Max - ADC1412D125 Min Typ 89 88 86 84 100 Max Unit dBc dBc dBc dBc dBc channel crosstalk fi = 70 MHz Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. 10.2 Clock and digital output timing Table 8. Symbol Clock and digital output timing characteristics[1] Parameter Conditions ADC1412D065 Min Clock timing input: pins CLKP and CLKM fclk tlat(data) δclk td(s) twake tPD tsu th tr tf clock frequency data latency time clock duty cycle DCS_EN = 1 DCS_EN = 0 sampling delay time wake-up time propagation delay set-up time hold time rise time fall time DATA DAV DATA [2] [2] ADC1412D080 Min 60 30 45 0.5 0.5 0.5 14 50 50 0.8 tbd 3.9 4.2 7.4 3.4 Typ Max 80 70 55 2.4 2.4 2.4 ADC1412D105 Min 75 30 45 0.5 0.5 0.5 14 50 50 0.8 tbd 3.9 4.2 6.1 1.8 Typ Max 105 70 55 2.4 2.4 2.4 ADC1412D125 Min 100 30 45 0.5 0.5 0.5 14 50 50 0.8 tbd 3.9 4.2 5.7 1.4 Typ Max 125 70 55 2.4 2.4 2.4 Unit Typ 14 50 50 0.8 tbd 3.9 4.2 8.6 4.8 - Max 65 70 55 2.4 2.4 2.4 20 30 45 DATA DAV 0.5 0.5 0.5 MHz clock cycles % % ns CMOS or LVDS DDR digital outputs ADC1412D series ns ns ns ns ns ns ns ns CMOS mode timing: pins DA13 to DA0, DB13 to DB0 and DAV xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 8. Symbol Clock and digital output timing characteristics[1] …continued Parameter Conditions ADC1412D065 Min Typ Max ADC1412D080 Min Typ Max ADC1412D105 Min Typ Max ADC1412D125 Min Typ Max Unit Preliminary data sheet Rev. 03 — 6 August 2010 12 of 40 ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors LVDS DDR mode timing: pins DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M, DB12_DB13_P to DB0_DB1_P, DB12_DB13_M to DB0_DB1_M, DAVP and DAVM tPD tsu th tr tf propagation delay set-up time hold time rise time fall time DATA DAV DATA DAV [1] [2] [3] [3] [3] DATA DAV 50 50 50 50 3.9 4.2 5.1 2.0 100 100 100 100 200 200 200 200 50 50 50 50 3.9 4.2 3.5 2.0 100 100 100 100 200 200 200 200 50 50 50 50 3.9 4.2 2.1 2.0 100 100 100 100 200 200 200 200 50 50 50 50 3.9 4.2 1.4 2.0 100 100 100 100 200 200 200 200 ns ns ns ns ps ps ps ps Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; unless otherwise specified. Measured between 20 % to 80 % of VDDO. Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. CMOS or LVDS DDR digital outputs ADC1412D series NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs N N+1 td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tPD tsu DAV th tclk 005aaa060 Fig 4. CMOS mode timing N N+1 td(s) N+2 tclk CLKP CLKM tPD DAx_DAx + 1_P/ DBx_DBx + 1_P DAx_DAx + 1_M/ DBx_DBx + 1_M (N − 14) (N − 13) (N − 12) (N − 11) DAx/ DBx DAx+1/ DBx+1 DAx/ DBx tsu th DAx+1/ DBx+1 tsu th DAx/ DBx DAx+1/ DBx+1 DAx/ DBx DAx+1/ DBx+1 DAx/ DBx DAx+1/ DBx+1 tPD DAVP DAVM tclk 005aaa114 Fig 5. LVDS DDR mode timing ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 13 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9. Symbol tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max) [1] Characteristics Parameter SCLK pulse width SCLK HIGH pulse width SCLK LOW pulse width set-up time hold time maximum clock frequency data to SCLK HIGH CS to SCLK HIGH data to SCLK HIGH CS to SCLK HIGH Conditions Min 40 16 16 5 5 2 2 Typ Max 25 Unit ns ns ns ns ns ns ns MHz SPI timings Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V tsu CS tsu th tw(SCLKL) tw(SCLK) tw(SCLKH) th SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. SPI timing ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 14 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11. Application information 11.1 Device control The ADC1412D can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device remains in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 7. CS Pin control mode Data format offset binary SPI control mode SCLK/DFS Data format two's complement LVDS DDR SDIO/ODS CMOS R/W W1 W0 A12 005aaa039 Fig 7. Control mode selection When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1412D operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 21) or by using pin CTRL in Pin control mode, as described in Table 10. Table 10. Pin CTRL 0 0.3VDDA 0.6VDDA VDDA Operating mode selection via pin CTRL Operating mode Power-down Sleep Power-up Power-up Output high-Z yes yes yes no 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 24) or by using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 15 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 24) or by using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1412D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INAP, INAM, INBP and INBM set to 0.5VDDA. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 23). The equivalent circuit of the sample and hold input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8. Package ESD Parasitics Switch Ron = 14 Ω 4 pF INAP/INBP internal clock Sampling capacitor Ron = 14 Ω Switch 4 pF INAM/INBM internal clock Sampling capacitor 005aaa092 Fig 8. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (RC filter in Figure 9) is needed to counteract the effects of charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 16 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs R INAP/INBP C R INAM/INBM 005aaa093 Fig 9. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. 3 70 170 RC coupling versus input frequency, typical values R (Ω) 25 12 12 C (pF) 12 8 8 Input frequency (MHz) 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 10 would be suitable for a baseband application. ADT1-1WT 100 nF Analog input 100 nF 25 Ω 25 Ω INAP/INBP 12 pF 100 nF 25 Ω 25 Ω 100 nF INAM/INBM VCMA/VCMB 100 nF 100 nF 005aaa094 Fig 10. Single transformer configuration suitable for baseband applications The configuration shown in Figure 11 is recommended for high frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 17 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs ADT1-1WT 100 nF 50 Ω ADT1-1WT 50 Ω 12 Ω INAP/INBP Analog input 8.2 pF 50 Ω 50 Ω 12 Ω INAM/INBM VCMA/VCMB 100 nF 100 nF 100 nF 005aaa095 Fig 11. Dual transformer configuration suitable for high intermediate frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1412D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF when bit INTREF_EN = logic 1; see Table 23). See Figure 13 to Figure 16. The equivalent reference circuit is shown in Figure 12. External reference is also possible by providing a voltage on pin VREF as described in Figure 15. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 18 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs REFAT/ REFBT REFERENCE AMP REFAB/ REFBB VREF EXT_ref BUFFER EXT_ref BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 12. Reference equivalent schematic If bit INTREF_EN is set to 0, the reference voltage is determined either internally or externally as detailed in Table 12. Table 12. Selection internal (Figure 13) internal (Figure 14) external (Figure 15) internal via SPI (Figure 16) [1] Reference selection SPI bit INTREF_EN 0 0 0 1 SENSE pin AGND VREF pin 330 pF capacitor to AGND Full-scale (p-p) 2V 1V 1 V to 2 V 1 V to 2 V pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND VDDA external voltage between 0.5 V and 1 V[1] pin VREF connected to pin SENSE and via 330 pF capacitor to AGND The voltage on pin VREF is doubled internally to generate the internal reference voltage. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 19 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs VREF 330 pF VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 13. Internal reference, 2 V (p-p) full scale Fig 14. Internal reference, 1 V (p-p) full scale VREF 0.1 μF VREF V 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE REFERENCE EQUIVALENT SCHEMATIC SENSE VDDA 005aaa119 005aaa118 Fig 15. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 16. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 20 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11.3.2 Reference gain control The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see Table 23). The corresponding full-scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 13. Table 13. INTREF 000 001 010 011 100 101 110 111 Reference SPI gain control Gain 0 dB −1 dB −2 dB −3 dB −4 dB −5 dB −6 dB reserved Full-scale (p-p) 2V 1.78 V 1.59 V 1.42 V 1.26 V 1.12 V 1V x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 μF filter capacitor should be connected between pin VCMA/VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCMA/VCMB can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. Package ESD Parasitics COMMON MODE REFERENCE VCMA/VCMB 1.5 V 0.1 μF ADC CORE 005aaa099 Fig 17. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INAP/INBP and INAM/INBM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 21 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11.4 Clock input 11.4.1 Drive modes The ADC1412D can be driven differentially (SINE, LVPECL or LVDS) with little or no degradation on dynamic performance. It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or CLKM (pin CLKP should be connected to ground via a capacitor). A differential clock is preferred for optimal performance. An LVPECL clock is recommended. LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input CLKM 005aaa174 005aaa053 a. Rising edge LVCMOS Fig 18. LVCMOS single-ended clock input b. Falling edge LVCMOS CLKP Sine clock input Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVDS clock input LVPECL clock input CLKM CLKP CLKM 005aaa055 005aaa172 c. LVDS clock input Fig 19. Differential clock input d. LVPECL clock input ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 22 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 20. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. Package ESD Parasitics CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Vcm(clk) = common-mode voltage of the differential input stage Fig 20. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 22). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = logic 1; see Table 22), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and 55 %. 11.4.4 Clock input divider The ADC1412D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see Table 22). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 23 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic 0 (see Table 24). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 21. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO Parasitics ESD Package LOGIC DRIVER 50 Ω Dx OGND 005aaa057 Fig 21. CMOS digital output buffer The output resistance is 50 Ω and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 31). ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 24 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic 1 (see Table 24). VDDO 3.5 mA typ − + DAn_DAn + 1_P; DBn_DBn + 1_P 100 Ω RECEIVER DAn_DAn + 1_M; DBn_DBn + 1_M − OGND 005aaa112 + Fig 22. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 22) or internally via SPI control bits LVDS_INT_TER (see Figure 23 and Table 33). VDDO 3.5 mA typ − + DAn_DAn + 1_P; DBn_DBn + 1_P 100 Ω 100 Ω RECEIVER DAn_DAn + 1_M; DBn_DBn + 1_M + − OGND 005aaa113 Fig 23. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI and DATAI; see Table 32) in order to adjust the output logic voltage levels. Table 14. 000 001 010 011 100 ADC1412D_SER LVDS DDR output register 2 Resistor value no internal termination 300 Ω 180 Ω 110 Ω 150 Ω All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. LVDS_INT_TER[2:0] Preliminary data sheet Rev. 03 — 6 August 2010 25 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs LVDS DDR output register 2 …continued Resistor value 100 Ω 81 Ω 60 Ω Table 14. 101 110 111 LVDS_INT_TER[2:0] 11.5.3 DAta Valid (DAV) output clock A DAta Valid (DAV) output clock signal is provided that can be used to capture the data delivered by the ADC1412D. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively. In LVDS DDR mode, it is highly recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100; see Table 25). 11.5.4 OuT-of-Range (OTR) An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for ADC channel B. The latency of OTRA/B is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 30). In this mode, the latency of OTRA/B is reduced to only four clock cycles (separately for each ADC channel). The Fast OTR detection threshold (below full-scale) can be programmed via bits FASTOTR_DET. Table 15. 000 001 010 011 100 101 110 111 Fast OTR register Detection level −20.56 dB −16.12 dB −11.02 dB −7.82 dB −5.49 dB −3.66 dB −2.14 dB −0.86 dB FASTOTR_DET[2:0] 11.5.5 Digital offset By default, the ADC1412D delivers output code that corresponds to the analog input. However, it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET; see Table 26). 11.5.6 Test patterns For test purposes, the ADC1412D can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL; see Table 27). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 28 and Table 29) and is selected when TESTPAT_SEL = 101. The selected test pattern is transmitted regardless of the analog input. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 26 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 11.5.7 Output codes versus input voltage Table 16. Output codes Two’s complement 10 0000 0000 0000 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 10 0000 0000 0011 10 0000 0000 0100 .... 11 1111 1111 1110 11 1111 1111 1111 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 .... 01 1111 1111 1011 01 1111 1111 1100 01 1111 1111 1101 01 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 OTRA/OTRB pin 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VINAP − VINAM/ Offset binary VINBP − VINBM < −1 −1 −0.9998779 −0.9997559 −0.9996338 −0.9995117 .... −0.0002441 −0.0001221 +0 +0.0001221 +0.0002441 .... +0.9995117 +0.9996338 +0.9997559 +0.9998779 +1 > +1 00 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 00 0000 0000 0011 00 0000 0000 0100 .... 01 1111 1111 1110 01 1111 1111 1111 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 .... 11 1111 1111 1011 11 1111 1111 1100 11 1111 1111 1101 11 1111 1111 1110 11 1111 1111 1111 11 1111 1111 1111 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1412D serial interface is a synchronous serial communications port that allows easy interfacing with many commonly used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin). Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 18). Table 17. Bit Description Instruction bytes for the SPI MSB 7 R/W[1] A7 [1] [2] ADC1412D_SER LSB 6 W1[2] A6 5 W0[2] A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0 Bit R/W indicates whether it is a read (1) or a write (0) operation. Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18). All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 27 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Number of data bytes to be transferred after the instruction bytes W0 0 1 0 1 Number of bytes transmitted 1 byte 2 bytes 3 bytes 4 bytes or more Table 18. W1 0 0 1 1 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps for a data transfer: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end of data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction bytes Register N (data) Register N + 1 (data) 005aaa062 Fig 24. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS triggers a transition to SPI control mode. When the ADC1412D enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 25). Once in SPI control mode, the output data standard can be changed via bit LVDS_CMOS in Table 24. When the ADC1412D enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT in Table 24. ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 28 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 25. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 26. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 29 of 40 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 11.6.3 Register allocation map Table 19. Addr (Hex) 0003 0005 0006 0008 0011 0012 0013 0014 0015 0016 0017 0020 0021 0022 Register allocation map Register name Channel index Reset and operating mode Clock Output data standard Output clock Offset Test pattern 1 Test pattern 2 Test pattern 3 Fast OTR CMOS output R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESERVED DAVI[1:0] BIT_BYTE_WISE SW_ RST TESTPAT_USER[5:0] FASTOTR DAV_DRV[1:0] RESERVED Bit definition Bit 7 Bit 6 Bit 5 Bit 4 RESERVED[5:0] RESERVED[2:0] SE_SEL LVDS_CMOS DIFF_SE INTREF_EN OUTBUF DAVINV DIG_OFFSET[5:0] TESTPAT_USER[13:6] FASTOTR_DET[2:0] DATA_DRV[1:0] DATAI[1:0] LVDS_INT_TER[2:0] TESTPAT_SEL[2:0] OUTBUS_SWAP Bit 3 Bit 2 Bit 1 ADCB Bit 0 ADCA Default (Bin) 11111 1111 0000 0000 Preliminary data sheet Rev. 03 — 6 August 2010 30 of 40 ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors OP_MODE[1:0] CLKDIV INTREF[2:0] DATA_FORMAT[1:0] DCS_EN 0000 0001 0000 0000 0000 0000 0000 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 0000 0000 0000 0000 Internal reference R/W DAVPHASE[2:0] LVDS DDR O/P 1 R/W LVDS DDR O/P 2 R/W CMOS or LVDS DDR digital outputs ADC1412D series NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Table 20. Channel index control register (address 0003h) bit description Default values ae highlighted. Bit 7 to 2 1 Symbol RESERVED[5:0] ADCB R/W 0 1 0 ADCA R/W 0 1 Access Value 111111 Description reserved next SPI command for ADC B ADC B not selected ADC B selected next SPI command for ADC A ADC A not selected ADC A selected Table 21. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit 7 Symbol SW_RST Access R/W 0 1 6 to 4 3 to 2 1 to 0 RESERVED[2:0] OP_MODE[1:0] R/W 00 01 10 11 Table 22. Clock control register (address 0006h) bit description Default values are highlighted. Bit 7 to 5 4 Symbol SE_SEL R/W 0 1 3 DIFF_SE R/W 0 1 2 1 RESERVED CLKDIV R/W 0 1 0 DCS_EN R/W 0 1 0 Access Value 000 Description not used single-ended clock input pin select CLKM CLKP differential/single-ended clock input select fully differential single-ended reserved clock input divide by 2 disabled enabled duty cycle stabilizer disabled enabled 000 00 Value Description reset digital section no reset performs a reset on SPI registers reserved not used operating mode normal (Power-up) Power-down Sleep normal (Power-up) ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 31 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Table 23. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol INTREF_EN R/W 0 1 2 to 0 INTREF[2:0] R/W 000 001 010 011 100 101 110 111 Access Value 0000 Description not used programmable internal reference enable disable active programmable internal reference 0 dB (FS = 2 V) −1 dB (FS = 1.78 V) −2 dB (FS = 1.59 V) −3 dB (FS = 1.42 V) −4 dB (FS = 1.26 V) −5 dB (FS = 1.12 V) −6 dB (FS = 1 V) reserved Table 24. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit 7 to 5 4 Symbol LVDS_CMOS R/W 0 1 3 OUTBUF R/W 0 1 2 OUTBUS_SWAP R/W 0 1 1 to 0 DATA_FORMAT[1:0] R/W 00 01 10 11 Access Value 000 Description not used output data standard: LVDS DDR or CMOS CMOS LVDS DDR output buffers enable output enabled output disabled (high Z) output bus swap no swapping output bus is swapped (MSB becomes LSB, vice versa) output data format offset binary two’s complement gray code offset binary ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 32 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Table 25. Output clock register (address 0012h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol DAVINV R/W 0 1 2 to 0 DAVPHASE[2:0] R/W 000 001 010 011 100 101 110 111 Table 26. Offset register (address 0013h) bit description Default values are highlighted. Bit 7 to 6 5 to 0 Symbol DIG_OFFSET[5:0] R/W 011111 ... 000000 ... 100000 Table 27. Test pattern 1 register (address 0014h) bit description Default values are highlighted. Bit 7 to 3 2 to 0 Symbol TESTPAT_SEL[2:0] R/W 000 001 010 011 100 101 110 111 Access Value 00000 Description not used digital test pattern select off mid scale −FS +FS toggle ‘1111..1111’/’0000..0000’ custom test pattern ‘0101..0101’ ‘1010..1010.’ Access Value 00 Description not used digital offset adjustment +31 LSB ... 0 ... −32 LSB Access Value 0000 Description not used output clock data valid (DAV) polarity normal inverted DAV phase select output clock shifted (ahead) by 3 ns output clock shifted (ahead) by 2.5 ns output clock shifted (ahead) by 2 ns output clock shifted (ahead) by 1.5 ns output clock shifted (ahead) by 1 ns output clock shifted (ahead) by 0.5 ns default value as defined in timing section output clock shifted (delayed) by 0.5 ns ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 33 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Table 28. Test pattern 2 register (address 0015h) bit description Default values are highlighted. Bit 7 to 0 Symbol TESTPAT_USER[13:6] Access R/W Value 0000 0000 Description custom digital test pattern (bits 13 to 6) Table 29. Test pattern 3 register (address 0016h) bit description Default values are highlighted. Bit 7 to 2 1 to 0 Symbol TESTPAT_USER[5:0] Access R/W Value 000000 00 Description custom digital test pattern (bits 5 to 0) not used Table 30. Fast OTR register (address 0017h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol FASTOTR R/W 0 1 2 to 0 FASTOTR_DET[2:0] R/W 000 001 010 011 100 101 110 111 Table 31. CMOS output register (address 0020h) bit description Default values are highlighted. Bit 7 to 4 3 to 2 Symbol DAV_DRV[1:0] R/W 00 01 10 11 1 to 0 DATA_DRV[1:0] R/W 00 01 10 11 Access Value 0000 Description not used drive strength for DAV CMOS output buffer low medium high very high drive strength for data CMOS output buffer low medium high very high Access Value 0000 Description not used fast OuT-of-Range (OTR) detection disabled enabled set fast OTR detect level −20.56 dB −16.12 dB −11.02 dB −7.82 dB −5.49 dB −3.66 dB −2.14 dB −0.86 dB ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 34 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs Table 32. LVDS DDR 1 output register (address 0021h) bit description Default values are highlighted. Bit 7 to 6 5 4 to 3 Symbol RESERVED DAVI[1:0] R/W R/W 00 01 10 11 2 1 to 0 RESERVED DATAI[1:0] R/W 00 01 10 11 0 Access Value 000 0 Description not used reserved LVDS current for DAV LVDS buffer 3.5 mA 4.5 mA 1.25 mA 2.5 mA reserved LVDS current for data LVDS buffer 3.5 mA 4.5 mA 1.25 mA 2.5 mA Table 33. LVDS DDR 2 output register (address 0022h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol BIT_BYTE_WISE R/W 0 1 2 to 0 LVDS_INT_TER[2:0] R/W 000 001 010 011 100 101 110 111 Access Value 0000 Description not used DDR mode for LVDS output bit wise (even data bits output on DAV rising edge/odd data bits output on DAV falling edge) byte wise (MSB data bits output on DAV rising edge/LSB data bits output on DAV falling edge) internal termination for LVDS buffer (DAV and data) no internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 35 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 12. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-3 D B A terminal 1 index area E A A1 c detail X e1 1/2 e L 17 16 e b 32 33 v w CAB C y1 C C y e Eh 1/2 e e2 1 terminal 1 index area 64 Dh 49 48 X 0 Dimensions Unit mm A A1 b c 0.2 D(1) 9.1 9.0 8.9 Dh 7.25 7.10 6.95 E(1) 9.1 9.0 8.9 Eh 7.25 7.10 6.95 e 0.5 2.5 scale e1 7.5 e2 7.5 5 mm L 0.5 0.4 0.3 v 0.1 w y y1 0.1 max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT804-3 References IEC --JEDEC --JEITA --European projection sot804-3_po Issue date 09-02-24 10-08-06 Fig 27. Package outline SOT804-3 (HVQFN64) ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 36 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 13. Revision history Table 34. Revision history Release date 20100806 Data sheet status Change notice Supersedes ADC1412D065_080_105_125_2 Document ID ADC1412D_SER v.3 Modifications: Preliminary data sheet - • • • Template upgraded to Rev 2.12.0 including revised legal information. Figure 12 “Reference equivalent schematic” has been updated Dynamic characteristics table (Table 7) has been updated. Objective data sheet Objective data sheet ADC1412D065_080_105_125_1 - ADC1412D065_080_105_125_2 20090604 ADC1412D065_080_105_125_1 20090528 ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 37 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 14. Legal information 14.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2010. All rights reserved. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ADC1412D_SER All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 03 — 6 August 2010 38 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1412D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 03 — 6 August 2010 39 of 40 NXP Semiconductors ADC1412D series CMOS or LVDS DDR digital outputs 16. Contents 1 2 3 4 5 6 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 CMOS outputs selected . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 LVDS/DDR outputs selected. . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics . . . . . . . . . . . . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Clock and digital output timing . . . . . . . . . . . . 11 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 15 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI and Pin control modes . . . . . . . . . . . . . . . 15 Operating mode selection. . . . . . . . . . . . . . . . 15 Selecting the output data standard . . . . . . . . . 15 Selecting the output data format. . . . . . . . . . . 16 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 16 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System reference and power management . . 18 Internal/external references . . . . . . . . . . . . . . 18 Reference gain control . . . . . . . . . . . . . . . . . . 21 Common-mode output voltage (VO(cm)) . . . . . 21 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 22 Equivalent input circuit . . . . . . . . . . . . . . . . . . 23 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 23 Clock input divider . . . . . . . . . . . . . . . . . . . . . 23 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital output buffers: CMOS mode . . . . . . . . 24 Digital output buffers: LVDS DDR mode . . . . . 25 DAta Valid (DAV) output clock . . . . . . . . . . . . 26 OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 26 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.5.7 11.6 11.6.1 11.6.2 11.6.3 12 13 14 14.1 14.2 14.3 14.4 15 16 Output codes versus input voltage. . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Default modes at start-up. . . . . . . . . . . . . . . . Register allocation map . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 28 30 36 37 38 38 38 38 39 39 40 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 August 2010 Document identifier: ADC1412D_SER