ADC1412D105HN/C1:5

ADC1412D series Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 05 — 2 July 2012 Product data sheet 1. General description The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1412D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in Complementary Metal Oxide Semiconductor (CMOS) mode because of a separate digital output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes an programmable full-scale SPI to allow a flexible input voltage range of 1 V (p-p) to 2 V (p-p). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D is ideal for use in communications, imaging and medical applications. 2. Features and benefits         SNR, 72.1 dBFS SFDR, 86 dBc Sample rate up to 125 Msps Clock input divided by 2 to reduce jitter contribution Single 3 V supply Flexible input voltage range: 1 V to 2 V (p-p) CMOS or LVDS DDR digital outputs Pin and software compatible with ADC1212D series and ADC1112D125     Input bandwidth, 600 MHz Power dissipation, 855 mW at 80 Msps Serial Peripheral Interface (SPI) Duty cycle stabilizer  Fast OuT-of-Range (OTR) detection  Offset binary, two’s complement, gray code  Power-down and Sleep modes  HVQFN64 package 3. Applications  Wireless and wired broadband communications  Spectral analysis  Ultrasound equipment  Portable instrumentation  Imaging systems  Software defined radio ® ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description Version ADC1412D125HN-C1 125 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9  9  0.85 mm SOT804-3 ADC1412D105HN-C1 105 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9  9  0.85 mm SOT804-3 ADC1412D080HN-C1 80 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9  9  0.85 mm SOT804-3 ADC1412D065HN-C1 65 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9  9  0.85 mm SOT804-3 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1412D ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE OTRA CMOS: DA13 to DA0 or LVDS/DDR: DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M INAP T/H INPUT STAGE ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS INAM CLKP CLKM CLOCK INPUT STAGE AND DUTY CYCLE CONTROL CMOS: DAV or LVDS/DDR: DAVP DAVM OUTPUT DRIVERS CMOS: DB13 to DB0 or LVDS/DDR: DB12_DB13_P to DB0_DB1_P DB12_DB13_M to DB0_DB1_M INBP T/H INPUT STAGE ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS INBM OTRB SYSTEM REFERENCE AND POWER MANAGEMENT ERROR CORRECTION AND DIGITAL PROCESSING REFBT CTRL REFAB REFBB REFAT VCMB VCMA SENSE VREF 005aaa096 Fig 1. Block diagram ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 2 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 6. Pinning information 6.1 CMOS outputs selected 49 VDDO 50 VDDO 51 DA6 52 DA7 53 DA8 54 DA9 55 DA10 56 DA11 57 DA12 58 DA13 59 OTRA 60 DECA 61 VDDA INAP 1 48 DA5 INAM 2 47 DA4 AGND 3 46 DA3 VCMA 4 45 DA2 REFAT 5 44 DA1 REFAB 6 43 DA0 AGND 7 42 DAV CLKP 8 CLKM 9 41 n.c. ADC1412D HVQFN64 40 DB0 VDDO 32 VDDO 31 DB8 30 DB9 29 DB10 28 DB11 27 DB12 26 DB13 25 33 DB7 OTRB 24 34 DB6 INBP 16 DECB 23 35 DB5 INBM 15 CTRL 22 36 DB4 AGND 14 CS 21 37 DB3 VCMB 13 SDIO/ODS 20 38 DB2 REFBT 12 SCLK/DFS 19 39 DB1 REFBB 11 VDDA 18 AGND 10 VDDA 17 Fig 2. 62 SENSE terminal 1 index area 63 VREF 64 VDDA 6.1.1 Pinning 005aaa097 Transparent top view Pin configuration with CMOS digital outputs selected 6.1.2 Pin description Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [1] Description INAP 1 I analog input; channel A INAM 2 I complementary analog input; channel A AGND 3 G analog ground VCMA 4 O common-mode output voltage; channel A REFAT 5 O top reference; channel A REFAB 6 O bottom reference; channel A AGND 7 G analog ground CLKP 8 I clock input CLKM 9 I complementary clock input AGND 10 G analog ground REFBB 11 O bottom reference; channel B REFBT 12 O top reference; channel B ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 3 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 2. Symbol Pin description (CMOS digital outputs) …continued Pin Type [1] Description VCMB 13 O common-mode output voltage; channel B AGND 14 G analog ground INBM 15 I complementary analog input; channel B INBP 16 I analog input; channel B VDDA 17 P analog power supply VDDA 18 P analog power supply SCLK/DFS 19 I SPI clock/data format select SDIO/ODS 20 I/O SPI data input/output/output data standard CS 21 I SPI chip select, active LOW CTRL 22 I control mode select DECB 23 O regulator decoupling node; channel B OTRB 24 O out of range; channel B DB13 25 O data output bit 13 (Most Significant Bit (MSB)); channel B DB12 26 O data output bit 12; channel B DB11 27 O data output bit 11; channel B DB10 28 O data output bit 10; channel B DB9 29 O data output bit 9; channel B DB8 30 O data output bit 8; channel B VDDO 31 P output power supply VDDO 32 P output power supply DB7 33 O data output bit 7; channel B DB6 34 O data output bit 6; channel B DB5 35 O data output bit 5; channel B DB4 36 O data output bit 4; channel B DB3 37 O data output bit 3; channel B DB2 38 O data output bit 2; channel B DB1 39 O data output bit 1; channel B DB0 40 O data output bit 0 (Least Significant Bit (LSB)); channel B n.c. 41 - not connected DAV 42 O data valid output clock DA0 43 O data output bit 0 (LSB); channel A DA1 44 O data output bit 1; channel A DA2 45 O data output bit 2; channel A DA3 46 O data output bit 3; channel A DA4 47 O data output bit 4; channel A DA5 48 O data output bit 5; channel A VDDO 49 P output power supply VDDO 50 P output power supply DA6 51 O data output bit 6; channel A DA7 52 O data output bit 7; channel A DA8 53 O data output bit 8; channel A DA9 54 O data output bit 9; channel A DA10 55 O data output bit 10; channel A DA11 56 O data output bit 11; channel A ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 4 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 2. Pin description (CMOS digital outputs) …continued Symbol Pin Type [1] Description DA12 57 O data output bit 12; channel A DA13 58 O data output bit 13 (MSB); channel A OTRA 59 O out-of-range; channel A DECA 60 O regulator decoupling node; channel A VDDA 61 P analog power supply SENSE 62 I reference programming pin VREF 63 I/O voltage reference input/output VDDA 64 P analog power supply [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. 6.2 LVDS DDR outputs selected 49 VDDO 50 VDDO 51 DA6_DA7_P 52 DA6_DA7_M 53 DA8_DA9_P 54 DA8_DA9_M 55 DA10_DA11_P 56 DA10_DA11_M 57 DA12_DA13_P 58 DA12_DA13_M 59 OTRA 60 DECA 61 VDDA 62 SENSE terminal 1 index area 63 VREF 64 VDDA 6.2.1 Pinning INAP 1 48 DA4_DA5_M INAM 2 47 DA4_DA5_P AGND 3 46 DA2_DA3_M VCMA 4 45 DA2_DA3_P REFAT 5 44 DA0_DA1_ M REFAB 6 43 DA0_DA1_P AGND 7 42 DAVP CLKP 8 CLKM 9 41 DAVM ADC1412D HVQFN64 40 DB0_DB1_P VDDO 32 VDDO 31 DB8_DB9_P 30 DB8_DB9_M 29 DB10_DB11_P 28 DB10_DB11_M 27 DB12_DB13_P 26 DB12_DB13_M 25 OTRB 24 33 DB6_DB7_M DECB 23 34 DB6_DB7_P INBP 16 CTRL 22 35 DB4_DB5_M INBM 15 CS 21 36 DB4_DB5_P AGND 14 SDIO/ODS 20 37 DB2_DB3_M VCMB 13 SCLK/DFS 19 38 DB2_DB3_P REFBT 12 VDDA 18 39 DB0_DB1_M REFBB 11 VDDA 17 AGND 10 005aaa098 Transparent top view Fig 3. Pin configuration with LVDS DDR digital outputs selected ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 5 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 6.2.2 Pin description Table 3. Pin description (LVDS DDR) digital outputs) Description DB12_DB13_M 25 O differential output data DB12 and DB13 multiplexed, complement DB12_DB13_P Symbol Pin 26 O differential output data DB12 and DB13 multiplexed, true DB10_DB11_M 27 O differential output data DB10 and DB11 multiplexed, complement DB10_DB11_P 28 O differential output data DB10 and DB11 multiplexed, true DB8_DB9_M 29 O differential output data DB8 and DB9 multiplexed, complement DB8_DB9_P 30 O differential output data DB8 and DB9 multiplexed, true DB6_DB7_M 33 O differential output data DB6 and DB7 multiplexed, complement DB6_DB7_P 34 O differential output data DB6 and DB7 multiplexed, true DB4_DB5_M 35 O differential output data DB4 and DB5 multiplexed, complement DB4_DB5_P 36 O differential output data DB4 and DB5 multiplexed, true DB2_DB3_M 37 O differential output data DB2 and DB3 multiplexed, complement DB2_DB3_P 38 O differential output data DB2 and DB3 multiplexed, true DB0_DB1_M 39 O differential output data DB0 and DB1 multiplexed, complement DB0_DB1_P 40 O differential output data DB0 and DB1 multiplexed, true DAVM 41 O data valid output clock, complement DAVP 42 O data valid output clock, true DA0_DA1_P 43 O differential output data DA0 and DA1 multiplexed, true DA0_DA1_M 44 O differential output data DA0 and DA1 multiplexed, complement DA2_DA3_P 45 O differential output data DA2 and DA3 multiplexed, true DA2_DA3_M 46 O differential output data DA2 and DA3 multiplexed, complement DA4_DA5_P 47 O differential output data DA4 and DA5 multiplexed, true DA4_DA5_M 48 O differential output data DA4 and DA5 multiplexed, complement DA6_DA7_P 51 O differential output data DA6 and DA7 multiplexed, true DA6_DA7_M 52 O differential output data DA6 and DA7 multiplexed, complement DA8_DA9_P 53 O differential output data DA8 and DA9 multiplexed, true DA8_DA9_M 54 O differential output data DA8 and DA9 multiplexed, complement DA10_DA11_P 55 O differential output data DA10 and DA11 multiplexed, true DA10_DA11_M 56 O differential output data DA10 and DA11 multiplexed, complement DA12_DA13_P 57 O differential output data DA12 and DA13 multiplexed, true DA12_DA13_M 58 O differential output data DA12 and DA13 multiplexed, complement [1] Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs (see Table 2). [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. ADC1412D_SER 5 Product data sheet [1] Type [2] © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 6 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit pins DA13 to DA0 and DB13 to DB0 or pins DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M, DB12_DB13_P to DB0_DB1_P and DB12_DB13_M to DB0_DB1_M 0.4 +3.9 V VO output voltage VDDA analog supply voltage 0.4 +3.9 V VDDO output supply voltage 0.4 +3.9 V Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C Tj junction temperature - 125 C 8. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-a) thermal resistance from junction to ambient thermal resistance from junction to case Rth(j-c) [1] Conditions Typ Unit [1] 15.6 K/W [1] 6.3 K/W Value for six layers board in still air with a minimum of 64 thermal vias. 9. Static characteristics Table 6. Symbol Static characteristics[1] Parameter Conditions Min Typ Max Unit 2.85 3.0 3.4 V Supplies VDDA analog supply voltage VDDO output supply voltage CMOS mode 1.65 1.8 3.6 V LVDS DDR mode 2.85 3.0 3.6 V IDDA analog supply current fclk = 125 Msps; fi = 70 MHz - 400 - mA IDDO output supply current CMOS mode; fclk = 125 Msps; fi = 70 MHz - 18 - mA LVDS DDR mode: fclk = 125 Msps; fi = 70 MHz - 92 - mA ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 7 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 6. Static characteristics[1] …continued Symbol Parameter Conditions Min Typ Max Unit P power dissipation ADC1412D125; analog supply only - 1230 - mW ADC1412D105; analog supply only - 1130 - mW ADC1412D080; analog supply only - 855 - mW ADC1412D065; analog supply only - 780 - mW Power-down mode - 24 - mW Sleep mode - 80 - mW differential clock input voltage peak-to-peak - 1.6 - V differential clock input voltage peak-to-peak 0.8 3.0 - V Clock inputs: pins CLKP and CLKM LVPECL Vi(clk)dif Sine Vi(clk)dif LVCMOS VIL LOW-level input voltage - - 0.3VDDA V VIH HIGH-level input voltage 0.7VDDA - - V - 0 - V LOW-medium level - 0.3VDDA - V medium-HIGH level - 0.6VDDA - V Logic input: pin CTRL VIL LOW-level input voltage VIH HIGH-level input voltage - VDDA - V IIL LOW-level input current 10 - +10 A IIH HIGH-level input current 10 - +10 A Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS VIL LOW-level input voltage 0 - 0.3VDDA V VIH HIGH-level input voltage 0.7VDDA - VDDA V IIL LOW-level input current 10 - +10 A IIH HIGH-level input current 50 - +50 A CI input capacitance - 4 - pF - 0.2VDDO V Digital outputs, CMOS mode: pins DA13 to DA0, DB13 to DB0, OTRA, OTRB and DAV Output levels, VDDO = 3 V VOL LOW-level output voltage VOH HIGH-level output voltage CO output capacitance AGND high impedance; see Table 10 0.8VDDO - VDDO V - 3 - pF Output levels, VDDO = 1.8 V VOL LOW-level output voltage AGND - 0.2VDDO V VOH HIGH-level output voltage 0.8VDDO - VDDO ADC1412D_SER 5 Product data sheet V © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 8 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 6. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit Digital outputs, LVDS DDR mode: pins DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M, DB12_DB13_P to DB0_DB1_P, DB12_DB13_M to DB0_DB1_M, DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100  VO(offset) output offset voltage output buffer current set to 3.5 mA - 1.2 - V VO(dif) differential output voltage output buffer current set to 3.5 mA - 350 - mV CO output capacitance - 3 - pF +5 A Analog inputs: pins INAP, INAM, INBP and INBM II input current 5 - RI input resistance - 19.8 - k CI input capacitance - 2.8 - pF VI(cm) common-mode input voltage 0.9 1.5 2 V Bi input bandwidth - 600 - MHz VI(dif) differential input voltage 1 - 2 V VINAP = VINAM; VINBP = VINBM peak-to-peak Common-mode output voltage: pins VCMA and VCMB VO(cm) common-mode output voltage - 0.5VDDA - V IO(cm) common-mode output current - 4 - A output - 0.5 to 1 - V input 0.5 - 1 V 5 1 +5 LSB 0.95 0.5 +0.95 LSB - 2 - mV - 0.5 - % - 1.1 - % - 37 - dB I/O reference voltage: pin VREF VVREF voltage on pin VREF Accuracy INL integral non-linearity DNL differential non-linearity Eoffset offset error EG gain error MG(CTC) channel-to-channel gain matching guaranteed no missing codes full-scale Supply PSRR [1] power supply rejection ratio 200 mV (p-p) on pin VDDA; fi = DC Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINAP  VINAM = 1 dBFS; VINBP  VINBM = 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 9 of 41 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Integrated Device Technology ADC1412D_SER 5 Product data sheet 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Dynamic characteristics[1] Symbol Parameter Conditions ADC1412D065 ADC1412D080 ADC1412D105 ADC1412D125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max - 87 - - 87 - - 86 - - 88 - dBc - 86 - - 86 - - 86 - - 87 - dBc Analog signal processing 2H 3H ENOB 10 of 41 © IDT 2012. All rights reserved. SFDR total harmonic distortion effective number of bits signal-to-noise ratio spurious-free dynamic range - 85 - - 85 - - 84 - - 85 - dBc fi = 170 MHz - 82 - - 82 - - 81 - - 83 - dBc fi = 3 MHz - 86 - - 86 - - 85 - - 87 - dBc fi = 30 MHz - 85 - - 85 - - 85 - - 86 - dBc fi = 70 MHz - 84 - - 84 - - 83 - - 84 - dBc fi = 170 MHz - 81 - - 81 - - 80 - - 82 - dBc fi = 3 MHz - 83 - - 83 - - 82 - - 84 - dBc fi = 30 MHz - 82 - - 82 - - 82 - - 83 - dBc fi = 70 MHz - 81 - - 81 - - 80 - - 81 - dBc fi = 170 MHz - 78 - - 78 - - 77 - - 79 - dBc fi = 3 MHz - 11.7 - - 11.7 - - 11.6 - - 11.6 - bit fi = 30 MHz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bit fi = 70 MHz - 11.5 - - 11.5 - - 11.4 - - 11.4 - bit fi = 170 MHz - 11.4 - - 11.4 - - 11.3 - - 11.3 - bit fi = 3 MHz - 72.1 - - 72.0 - - 71.8 - - 71.4 - dBFS fi = 30 MHz - 71.3 - - 71.2 - - 71.2 - - 71.1 - dBFS fi = 70 MHz - 70.7 - - 70.7 - - 70.6 - - 70.5 - dBFS fi = 170 MHz - 70.2 - - 70.1 - - 70.0 - - 69.9 - dBFS fi = 3 MHz - 86 - - 86 - - 85 - - 87 - dBc fi = 30 MHz - 85 - - 85 - - 85 - - 86 - dBc fi = 70 MHz - 84 - - 84 - - 83 - - 84 - dBc fi = 170 MHz - 81 - - 81 - - 80 - - 82 - dBc ADC1412D series SNR third harmonic level fi = 70 MHz Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Rev. 05 — 2 July 2012 THD second harmonic fi = 3 MHz level fi = 30 MHz Symbol IMD ct(ch) [1] Dynamic characteristics[1] …continued Parameter Intermodulation distortion Conditions ADC1412D065 ADC1412D080 ADC1412D105 ADC1412D125 Unit Min Typ Max Min Typ Max Min Typ Max Min fi = 3 MHz - 89 - - 89 - - 88 - - 89 - dBc fi = 30 MHz - 88 - - 88 - - 88 - - 88 - dBc fi = 70 MHz - 87 - - 87 - - 86 - - 86 - dBc fi = 170 MHz - 84 - - 85 - - 83 - - 84 - dBc - 100 - - 100 - - 100 - - 100 - dBc channel crosstalk fi = 70 MHz Typ Integrated Device Technology ADC1412D_SER 5 Product data sheet Table 7. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Max Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINAP  VINAM = 1 dBFS; VINBP  VINBM = 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. 10.2 Clock and digital output timing Table 8. Rev. 05 — 2 July 2012 Symbol Clock and digital output timing characteristics[1] Parameter Conditions ADC1412D065 Min ADC1412D080 Typ Max Min 20 - 65 - 14 - 50 ADC1412D105 Typ Max Min 60 - 80 - 14 - 70 30 50 ADC1412D125 Typ Max Min 75 - 105 - 14 - 70 30 50 Unit Typ Max 100 - 125 - 14 - 70 30 50 70 % Clock timing input: pins CLKP and CLKM data latency time MHz clk clock duty cycle DCS_EN = 1 30 DCS_EN = 0 45 50 55 45 50 55 45 50 55 45 50 55 % td(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns twake wake-up time - 76 - - 76 - - 76 - - 76 - s clock cycles CMOS mode timing: pins DA13 to DA0, DB13 to DB0 and DAV tPD propagation delay 11 of 41 © IDT 2012. All rights reserved. tsu set-up time th hold time tr rise time DATA - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns DAV - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns - 8.6 - - 7.4 - - 6.1 - - 5.7 - ns DATA [2] DAV tf fall time DATA [2] - 4.8 - - 3.4 - - 1.8 - - 1.4 - ns 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns ADC1412D series clock frequency tlat(data) Dual 14-bit ADC: CMOS or LVDS DDR digital outputs fclk Symbol Clock and digital output timing characteristics[1] …continued Parameter Conditions ADC1412D065 Min Typ ADC1412D080 Max Min Typ ADC1412D105 Max Min Typ ADC1412D125 Max Min Typ Integrated Device Technology ADC1412D_SER 5 Product data sheet Table 8. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Unit Max LVDS DDR mode timing: pins DA12_DA13_P to DA0_DA1_P, DA12_DA13_M to DA0_DA1_M, DB12_DB13_P to DB0_DB1_P, DB12_DB13_M to DB0_DB1_M, DAVP and DAVM tPD propagation delay tsu set-up time th hold time tr rise time DATA - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns DAV - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns - 5.1 - - 3.5 - - 2.1 - - 1.4 - ns DATA [3] DAV tf fall time DATA DAV [3] - 2.0 - - 2.0 - - 2.0 - - 2.0 - ns 50 100 200 50 100 200 50 100 200 50 100 200 ps 50 100 200 50 100 200 50 100 200 50 100 200 ps 50 100 200 50 100 200 50 100 200 50 100 200 ps 50 100 200 50 100 200 50 100 200 50 100 200 ps Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINAP  VINAM = 1 dBFS; VINBP  VINBM = 1 dBFS; unless otherwise specified. [2] Measured between 20 % to 80 % of VDDO. [3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV. ADC1412D series 12 of 41 © IDT 2012. All rights reserved. Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Rev. 05 — 2 July 2012 [1] ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 tclk = 1 / fclk Fig 4. CMOS mode timing N+1 N td(s) N+2 tclk CLKP CLKM tPD DAx_DAx + 1_P/ DBx_DBx + 1_P DAx_DAx + 1_M/ DBx_DBx + 1_M DAx/ DBx DAx+1/ DBx+1 (N − 14) DAx/ DBx tsu th (N − 13) DAx+1/ DBx+1 tsu DAx/ DBx th DAx+1/ DBx+1 (N − 12) DAx/ DBx (N − 11) DAx+1/ DBx+1 DAx/ DBx DAx+1/ DBx+1 tPD DAVP DAVM tclk 005aaa114 tclk = 1 / fclk Fig 5. LVDS DDR mode timing ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 13 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9. Characteristics Symbol Parameter Conditions Min Typ Max Unit SPI timings tw(SCLK) SCLK pulse width - 40 - ns tw(SCLKH) SCLK HIGH pulse width - 16 - ns tw(SCLKL) SCLK LOW pulse width - 16 - ns tsu set-up time data to SCLK HIGH - 5 - ns CS to SCLK HIGH - 5 - ns th hold time data to SCLK HIGH - 2 - ns CS to SCLK HIGH - 2 - ns - 25 - MHz fclk(max) [1] maximum clock frequency Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V. tsu tsu th CS tw(SCLKL) th tw(SCLKH) tw(SCLK) SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. SPI timing ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 14 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 10.4 Typical characteristics 001aam619 3.2 001aam614 16 C (pF) R (kΩ) 3.0 12 2.8 8 2.6 4 2.4 0 50 Fig 7. 150 250 350 450 550 f (MHz) Capacitance as a function of frequency 001aam616 100 SFDR (dBc) 50 Fig 8. 150 250 350 450 550 f (MHz) Resistance as a function of frequency 001aam615 80 (1) SNR (dBFS) (1) 80 60 60 (2) (2) 40 40 20 20 0 0 10 30 50 70 δ (%) 90 10 T = 25 C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off (2) DCS off SFDR as a function of duty cycle () 70 δ (%) 90 Fig 10. SNR as a function of duty cycle () ADC1412D_SER 5 Product data sheet 50 T = 25 C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on Fig 9. 30 © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 15 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 001aam617 92 SFDR (dBc) 88 001aam618 80 (1) SNR (dBFS) (2) 60 (1) (2) (3) (3) 84 40 80 20 10 30 50 70 δ (%) 90 (1) Tamb = 40 C/typical supply voltages 10 30 50 70 δ (%) (1) Tamb = 40 C/typical supply voltages (2) Tamb = +25 C/typical supply voltages (2) Tamb = +25 C/typical supply voltages (3) Tamb = +90 C/typical supply voltages (3) Tamb = +90 C/typical supply voltages Fig 11. SFDR as a function of duty cycle () Fig 12. SNR as a function of duty cycle () 001aam659 90 90 001aam660 75 SFDR (dBc) SNR (dBFS) 86 73 82 71 78 69 74 67 70 65 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 VI(cm) (V) Fig 13. SFDR as a function of common-mode input voltage (VI(cm)) 1.0 1.5 2.0 2.5 3.0 3.5 VI(cm) (V) Fig 14. SNR as a function of common-mode input voltage (VI(cm)) ADC1412D_SER 5 Product data sheet 0.5 © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 16 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 11. Application information 11.1 Device control The ADC1412D can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device remains in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 15. CS SCLK/DFS SDIO/ODS Pin control mode Data format two's complement SPI control mode Data format offset binary LVDS DDR CMOS R/W W1 W0 A12 005aaa039 Fig 15. Control mode selection When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1412D operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 21) or by using pin CTRL in Pin control mode, as described in Table 10. Table 10. Operating mode selection via pin CTRL Pin CTRL Operating mode Output high-Z 0 Power-down yes 0.3VDDA Sleep yes 0.6VDDA Power-up yes VDDA Power-up no 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 24) or by using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 17 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 24) or by using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1412D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INAP, INAM, INBP and INBM set to 0.5VDDA. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 23). The equivalent circuit of the sample-and-hold input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 16. Package ESD Parasitics Switch Ron = 14 Ω 4 pF INAP/INBP internal clock Sampling capacitor Switch Ron = 14 Ω 4 pF INAM/INBM internal clock Sampling capacitor 005aaa092 Fig 16. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (RC filter in Figure 17) is needed to counteract the effects of charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 18 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs INAP/ INBP R C INAM/ INBM R 001aan679 Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency, typical values Input frequency (MHz) R () C (pF) 3 25 12 70 12 8 170 12 8 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 18 would be suitable for a baseband application. ADT1-1WT 100 nF Analog input 25 Ω 100 nF INAP/INBP 25 Ω 12 pF 100 nF 100 nF 25 Ω 25 Ω INAM/INBM VCMA/VCMB 100 nF 100 nF 005aaa094 Fig 18. Single transformer configuration suitable for baseband applications The configuration shown in Figure 19 is recommended for high frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 19 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs ADT1-1WT Analog input 100 nF ADT1-1WT 50 Ω 12 Ω INAP/INBP 50 Ω 8.2 pF 50 Ω 100 nF 50 Ω 12 Ω INAM/INBM VCMA/VCMB 100 nF 100 nF 005aaa095 Fig 19. Dual transformer configuration suitable for high intermediate frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1412D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and 6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1; see Table 23). See Figure 21 to Figure 24. The equivalent reference circuit is shown in Figure 20. External reference is also possible by providing a voltage on pin VREF as described in Figure 23. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 20 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs REFAT/ REFBT REFAB/ REFBB REFERENCE AMP VREF EXT_ref BUFFER EXT_ref BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 001aan670 Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Table 12. Reference selection Selection SPI bit INTREF_EN SENSE pin VREF pin Full-scale (V (p-p)) Internal (Figure 21) 0 AGND 330 pF capacitor to AGND 2V Internal (Figure 22) 0 pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND External (Figure 23) 0 VDDA external voltage between 0.5 V and 1 V[1] 1 V to 2 V Internal via SPI (Figure 24) 1 pin VREF connected to pin SENSE and via 330 pF capacitor to AGND 1 V to 2 V [1] The voltage on pin VREF is doubled internally to generate the internal reference voltage. ADC1412D_SER 5 Product data sheet 1V © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 21 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 21. Internal reference, 2 V (p-p) full scale Fig 22. Internal reference, 1 V (p-p) full scale VREF VREF V 0.1 μF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa119 005aaa118 Fig 23. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 24. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale Figure 21 to Figure 24 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. 11.3.2 Programmable full-scale The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 13). Table 13. Programmable full-scale INTREF Level (dB) Full-scale (V (p-p)) 000 0 2 001 1 1.78 010 2 1.59 011 3 1.42 100 4 1.26 101 5 1.12 110 6 1 111 reserved x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 F filter capacitor should be connected between pin VCMA/VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCMA/VCMB can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 22 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Package ESD Parasitics COMMON MODE REFERENCE VCMA/VCMB 1.5 V 0.1 μF ADC CORE 005aaa099 Fig 25. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INAP/INBP and INAM/INBM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V (see Table 6). 11.4 Clock input 11.4.1 Drive modes The ADC1412D can be driven differentially (LVPECL). It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a capacitor). LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input 005aaa174 a. Rising edge LVCMOS CLKM 005aaa053 b. Falling edge LVCMOS Fig 26. LVCMOS single-ended clock input ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 23 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs CLKP Sine clock input CLKP Sine clock input CLKM CLKM 005aaa054 005aaa173 a. Sine clock input b. Sine clock input (with transformer) CLKP CLKP LVPECL clock input LVDS clock input CLKM CLKM 005aaa055 c. LVDS clock input 005aaa172 d. LVPECL clock input Fig 27. Differential clock input ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 24 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode voltage of the differential input stage is set via internal 5 k resistors. Package ESD Parasitics CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Vcm(clk) = common-mode voltage of the differential input stage Fig 28. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 22). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = logic 1; see Table 22), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and 55 %. 11.4.4 Clock input divider The ADC1412D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see Table 22). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 25 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic 0 (see Table 24). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 29. The buffer is powered by a separate AGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO Parasitics ESD Package 50 Ω LOGIC DRIVER Dx AGND 005aaa057 Fig 29. CMOS digital output buffer The output resistance is 50  and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 31). ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 26 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic 1 (see Table 24). VDDO 3.5 mA typical + - DAn_DAn + 1_P; DBn_DBn + 1_P 100 Ω RECEIVER DAn_DAn + 1_M; DBn_DBn + 1_M - + AGND 005aaa112 Fig 30. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100  resistor (typical) at the receiver side (Figure 30) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and Table 33). VDDO 3.5 mA typical - + DAn_DAn + 1_P; DBn_DBn + 1_P 100 Ω 100 Ω RECEIVER DAn_DAn + 1_M; DBn_DBn + 1_M + AGND 005aaa113 Fig 31. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 32) in order to adjust the output logic voltage levels. ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 27 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 14. LVDS DDR output register 2 LVDS_INT_TER[2:0] Resistor value () 000 no internal termination 001 300 010 180 011 110 100 150 101 10 110 81 111 60 11.5.3 DAta Valid (DAV) output clock A DAta Valid (DAV) output clock signal is provided that can be used to capture the data delivered by the ADC1412D. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively. In LVDS DDR mode, it is highly recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100; see Table 25). 11.5.4 OuT-of-Range (OTR) An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for ADC channel B. The latency of OTRA/B is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 30). In this mode, the latency of OTRA/B is reduced to only four clock cycles (separately for each ADC channel). The Fast OTR detection threshold (below full-scale) can be programmed via bits FASTOTR_DET[2:0]. Table 15. Fast OTR register FASTOTR_DET[2:0] Detection level (dB) 000 20.56 001 16.12 010 11.02 011 7.82 100 5.49 101 3.66 110 2.14 111 0.86 11.5.5 Digital offset By default, the ADC1412D delivers output code that corresponds to the analog input. However, it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 26). ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 28 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 11.5.6 Test patterns For test purposes, the ADC1412D can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 27). A custom test pattern can be defined by the user (TESTPAT_USER[13:6]; see Table 28 and TESTPAT_USER[5:0]; see Table 29) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the analog input. 11.5.7 Output codes versus input voltage Table 16. Output codes VINAP  VINAM/ Offset binary VINBP  VINBM Two’s complement OTRA/OTRB pin < 1 00 0000 0000 0000 10 0000 0000 0000 1 1 00 0000 0000 0000 10 0000 0000 0000 0 0.9998779 00 0000 0000 0001 10 0000 0000 0001 0 0.9997559 00 0000 0000 0010 10 0000 0000 0010 0 0.9996338 00 0000 0000 0011 10 0000 0000 0011 0 0.9995117 00 0000 0000 0100 10 0000 0000 0100 0 .... .... .... 0 0.0002441 01 1111 1111 1110 11 1111 1111 1110 0 0.0001221 01 1111 1111 1111 11 1111 1111 1111 0 +0 10 0000 0000 0000 00 0000 0000 0000 0 +0.0001221 10 0000 0000 0001 00 0000 0000 0001 0 +0.0002441 10 0000 0000 0010 00 0000 0000 0010 0 .... .... .... 0 +0.9995117 11 1111 1111 1011 01 1111 1111 1011 0 +0.9996338 11 1111 1111 1100 01 1111 1111 1100 0 +0.9997559 11 1111 1111 1101 01 1111 1111 1101 0 +0.9998779 11 1111 1111 1110 01 1111 1111 1110 0 +1 11 1111 1111 1111 01 1111 1111 1111 0 > +1 11 1111 1111 1111 01 1111 1111 1111 1 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1412D serial interface is a synchronous serial communications port that allows easy interfacing with many commonly used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin). Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 18). ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 29 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 17. Instruction bytes for the SPI MSB LSB Bit 7 6 5 4 3 2 1 0 Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 [1] Bit R/W indicates whether it is a read (1) or a write (0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred (see Table 18). Table 18. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps for a data transfer: 1. A falling edge on pin CS in combination with a rising edge on pin SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on pin CS indicates the end of data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 Instruction bytes D4 D3 D2 Register N (data) D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register N + 1 (data) 005aaa086 Fig 32. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on pin CS triggers a transition to SPI control mode. When the ADC1412D enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 33). Once in SPI control mode, the output data standard can be changed via bit LVDS_CMOS (see Table 24). ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 30 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs When the ADC1412D enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] (see Table 24). CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 31 of 41 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 19. Integrated Device Technology ADC1412D_SER 5 Product data sheet 11.6.3 Register allocation map Register allocation map Access Bit definition 0003 Channel index R/W 0005 Reset and operating mode R/W SW_ RST 0006 Clock R/W - - - 0008 Internal reference R/W - - 0011 Output data standard - 0012 Output clock R/W 0013 Offset R/W 0014 Test pattern 1 R/W - - 0015 Test pattern 2 R/W Bit 7 R/W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RESERVED[5:0] RESERVED[2:0] - - SE_SEL DIFF_SE - - - INTREF_EN - - LVDS_CMOS OUTBUF - - - - DAVINV - - Bit 1 Bit 0 ADCB ADCA OP_MODE[1:0] CLKDIV - DATA_FORMAT[1:0] DAVPHASE[2:0] - Test pattern 3 R/W 0017 Fast OTR R/W - - - - 0020 CMOS output R/W - - - - 0021 LVDS DDR O/P 1 R/W - - RESERVED 0000 1110 TESTPAT_SEL[2:0] 0000 0000 0022 LVDS DDR O/P 2 R/W - - - 0000 0000 TESTPAT_USER[5:0] - FASTOTR - BIT_BYTE_WISE - FASTOTR_DET[2:0] DAV_DRV[1:0] DAVI[1:0] 0000 0000 0000 0000 TESTPAT_USER[13:6] 0016 0000 0000 0000 0000 DIG_OFFSET[5:0] - 11111 1111 DCS_EN 0000 0001 INTREF[2:0] OUTBUS_SWAP Default (bin) RESERVED 0000 0000 0000 0000 DATA_DRV[1:0] 0000 1110 DATAI[1:0] 0000 0000 LVDS_INT_TER[2:0] 0000 0000 ADC1412D series 32 of 41 © IDT 2012. All rights reserved. Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Rev. 05 — 2 July 2012 Address Register name (hex) ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 20. Channel index control register (address 0003h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 2 RESERVED[5:0] - 111111 reserved 1 ADCB R/W next SPI command for ADC B 0 ADC B not selected 1 0 ADCA R/W ADC B selected next SPI command for ADC A 0 ADC A not selected 1 ADC A selected Table 21. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit Symbol Access 7 SW_RST R/W Value Description reset digital section 0 no reset 1 performs a reset on SPI registers 6 to 4 RESERVED[2:0] - 000 reserved 3 to 2 - - 00 not used 1 to 0 OP_MODE[1:0] R/W operating mode 00 normal (Power-up) 01 Power-down 10 Sleep 11 normal (Power-up) Table 22. Clock control register (address 0006h) bit description Default values are highlighted. Bit Symbol 7 to 5 4 3 Access Value - - 000 SE_SEL R/W DIFF_SE RESERVED - 1 CLKDIV R/W 0 DCS_EN not used single-ended clock input pin select 0 CLKM 1 CLKP R/W 2 Description differential/single-ended clock input select 0 fully differential 1 single-ended 0 reserved clock input divide by 2 0 disabled 1 enabled R/W duty cycle stabilizer 0 disabled 1 enabled ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 33 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 23. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 INTREF_EN R/W programmable internal reference enable 0 disable 1 2 to 0 INTREF[2:0] R/W active programmable internal reference 000 0 dB (FS = 2 V) 001 1 dB (FS = 1.78 V) 010 2 dB (FS = 1.59 V) 011 3 dB (FS = 1.42 V) 100 4 dB (FS = 1.26 V) 101 5 dB (FS = 1.12 V) 110 6 dB (FS = 1 V) 111 reserved Table 24. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 5 - - 000 not used 4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS 0 CMOS 1 3 2 1 to 0 OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] R/W LVDS DDR output buffers enable 0 output enabled 1 output disabled (high Z) R/W output bus swap 0 no swapping 1 output bus is swapped (MSB becomes LSB, vice versa) R/W output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 34 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 25. Output clock register (address 0012h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 DAVINV R/W output clock data valid (DAV) polarity 0 normal 1 2 to 0 [1] DAVPHASE[2:0] R/W inverted DAV phase select 000 output clock shifted (ahead) by 6/16  tclk[1] 001 output clock shifted (ahead) by 5/16  tclk[1] 010 output clock shifted (ahead) by 4/16  tclk[1] 011 output clock shifted (ahead) by 3/16  tclk[1] 100 output clock shifted (ahead) by 2/16  tclk[1] 101 output clock shifted (ahead) by 1/16  tclk[1] 110 default value as defined in timing section 111 output clock shifted (delayed) by 1/16  tclk[1] tclk = 1 / fclk Table 26. Offset register (address 0013h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 6 - - 00 not used 5 to 0 DIG_OFFSET[5:0] R/W digital offset adjustment 011111 +31 LSB ... ... 000000 0 ... ... 100000 32 LSB Table 27. Test pattern 1 register (address 0014h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 3 - - 00000 not used 2 to 0 TESTPAT_SEL[2:0] R/W digital test pattern select 000 off 001 mid scale 010 FS 011 +FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern 110 ‘0101..0101’ 111 ‘1010..1010.’ ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 35 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 28. Test pattern 2 register (address 0015h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 0 TESTPAT_USER[13:6] R/W 0000 0000 custom digital test pattern (bits 13 to 6) Table 29. Test pattern 3 register (address 0016h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 2 TESTPAT_USER[5:0] R/W 000000 custom digital test pattern (bits 5 to 0) 1 to 0 - - 00 not used Table 30. Fast OTR register (address 0017h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 FASTOTR R/W 2 to 0 FASTOTR_DET[2:0] fast OuT-of-Range (OTR) detection 0 disabled 1 enabled R/W set fast OTR detection level 000 20.56 dB 001 16.12 dB 010 11.02 dB 011 7.82 dB 100 5.49 dB 101 3.66 dB 110 2.14 dB 111 0.86 dB Table 31. CMOS output register (address 0020h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 to 2 DAV_DRV[1:0] R/W drive strength for DAV CMOS output buffer 00 low 01 medium 10 high 11 1 to 0 DATA_DRV[1:0] R/W very high drive strength for data CMOS output buffer 00 low 01 medium 10 high 11 very high ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 36 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs Table 32. LVDS DDR 1 output register (address 0021h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 6 - - 00 not used 5 RESERVED - 0 reserved 4 to 3 DAVI[1:0] R/W 2 RESERVED - 1 to 0 DATAI[1:0] R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA 0 reserved LVDS current for data LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA Table 33. LVDS DDR 2 output register (address 0022h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 BIT_BYTE_WISE R/W 2 to 0 LVDS_INT_TER[2:0] DDR mode for LVDS output 0 bit wise (even data bits output on DAV rising edge/odd data bits output on DAV falling edge) 1 byte wise (MSB data bits output on DAV rising edge/LSB data bits output on DAV falling edge) R/W internal termination for LVDS buffer (DAV and data) 000 no internal termination 001 300  010 180  011 110  100 150  101 100  110 81  111 60  ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 37 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 12. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm A B D SOT804-3 terminal 1 index area E A A1 c detail X e1 1/2 e e L 17 32 C C A B C v w b y1 C y 33 16 e e2 Eh 1/2 e 1 terminal 1 index area 48 64 49 X Dh 0 2.5 Dimensions Unit mm 5 mm scale A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 e2 L v 0.2 9.1 9.0 8.9 7.25 7.10 6.95 9.1 9.0 8.9 7.25 7.10 6.95 0.5 7.5 7.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT804-3 --- --- --- sot804-3_po European projection Issue date 09-02-24 10-08-06 Fig 35. Package outline SOT804-3 (HVQFN64) ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 38 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 13. Abbreviations Table 34. Abbreviations Acronym Description ADC Analog-to-Digital Converter CMOS Complementary Metal Oxide Semiconductor DAV DAta Valid DCS Duty Cycle Stabilizer DFS Data Format Select ESD ElectroStatic Discharge IMD InterModulation Distortion FS Full-Scale LSB Least Significant Bit LVCMOS Low Voltage Complementary Metal Oxide Semiconductor LVDS DDR Low Voltage Differential Signalling Double Data Rate LVPECL Low-Voltage Positive Emitter-Coupled Logic MSB Most Significant Bit OTR OuT-of-Range SFDR Spurious-Free Dynamic Range SNR Signal-to-Noise Ratio SPI Serial Peripheral Interface TX Transmitter ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 39 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 14. Revision history Table 35. Revision history Document ID Release date ADC1412D_SER v.5 20120702 Product data sheet - ADC1412D_SER v.4 ADC1412D_SER v.4 20110304 Product data sheet - ADC1412D_SER v.3 Modifications: • • • • Data sheet status Change Supersedes notice Data sheet status changed from Preliminary to Product. Text and drawings updated throughout entire data sheet. Section 10.4 “Typical characteristics” has been added to the data sheet. Section 13 “Abbreviations” has been added to the data sheet. ADC1412D_SER v.3 20100806 Preliminary data sheet - ADC1412D065_080_105_125 v.2 ADC1412D065_080_105_125 v.2 20090604 Objective data sheet - ADC1412D065_080_105_125 v.1 ADC1412D065_080_105_125 v.1 20090528 Objective data sheet - - 15. Contact information For more information or sales office addresses, please visit: http://www.idt.com ADC1412D_SER 5 Product data sheet © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 40 of 41 ADC1412D series Integrated Device Technology Dual 14-bit ADC: CMOS or LVDS DDR digital outputs 16. Contents 1 2 3 4 5 6 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 7 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 CMOS outputs selected . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 LVDS DDR outputs selected. . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics . . . . . . . . . . . . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Clock and digital output timing . . . . . . . . . . . . 11 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical characteristics . . . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 17 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI and Pin control modes . . . . . . . . . . . . . . . 17 Operating mode selection. . . . . . . . . . . . . . . . 17 Selecting the output data standard . . . . . . . . . 17 Selecting the output data format. . . . . . . . . . . 18 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 11.6.3 12 13 14 15 16 ADC1412D_SER 5 Product data sheet Anti-kickback circuitry . . . . . . . . . . . . . . . . . . Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . System reference and power management . . Internal/external references . . . . . . . . . . . . . . Programmable full-scale . . . . . . . . . . . . . . . . Common-mode output voltage (VO(cm)) . . . . . Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent input circuit . . . . . . . . . . . . . . . . . . Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . Clock input divider . . . . . . . . . . . . . . . . . . . . . Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . Digital output buffers: CMOS mode . . . . . . . . Digital output buffers: LVDS DDR mode . . . . DAta Valid (DAV) output clock . . . . . . . . . . . . OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . Output codes versus input voltage. . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Default modes at start-up. . . . . . . . . . . . . . . . Register allocation map . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 20 20 22 22 23 23 23 25 25 25 26 26 27 28 28 28 29 29 29 29 30 32 38 39 40 40 41 © IDT 2012. All rights reserved. Rev. 05 — 2 July 2012 41 of 41