BUK9880-55A

BUK9880-55A N-channel TrenchMOS logic level FET Rev. 02 — 12 April 2007 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package using NXP General Purpose Automotive (GPA) TrenchMOS technology. 1.2 Features I Very low on-state resistance I 150 °C rated I Q101 compliant I Logic level compatible 1.3 Applications I Automotive systems I Motors, lamps and solenoids I General purpose power switching I 12 V and 24 V loads 1.4 Quick reference data I EDS(AL)S ≤ 36 mJ I ID ≤ 7 A I RDSon = 68 mΩ (typ) I Ptot ≤ 8 W 2. Pinning information Table 1. Pin 1 2 3 4 Pinning Description gate (G) drain (D) source (S) solder point; connected to drain (D) 1 2 3 mbb076 Simplified outline 4 Symbol D G S SOT223 (SC-73) NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 3. Ordering information Table 2. Ordering information Package Name BUK9880-55A SC-73 Description plastic surface-mounted package with increased heatsink; 4 leads Version SOT223 Type number 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IDR IDRM EDS(AL)S EDS(AL)R Parameter drain-source voltage drain-gate voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature reverse drain current peak reverse drain current Tsp = 25 °C Tsp = 25 °C; pulsed; tp ≤ 10 µs Tsp = 25 °C; VGS = 5 V; see Figure 2 and 3 Tsp = 100 °C; VGS = 5 V; see Figure 2 Tsp = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 Tsp = 25 °C; see Figure 1 RGS = 20 kΩ Conditions Min Max 55 55 ±15 7 4 30 8 Unit V V V A A A W −55 +150 °C −55 +150 °C [1] Source-drain diode 7 30 36 A A mJ Avalanche ruggedness non-repetitive drain-source avalanche unclamped inductive load; ID = 6 A; VDS ≤ 55 V; energy RGS = 50 Ω; VGS = 5 V; starting at Tj = 25 °C repetitive drain-source avalanche energy - [1] Conditions: a) Maximum value not quoted. Repetitive rating defined in Figure 16. b) Single-pulse avalanche rating limited by Tj(max) of 150 °C. c) Repetitive avalanche rating limited by an average junction temperature of 145 °C. d) Refer to application note AN10273 for further information. BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 2 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 120 Pder (%) 80 03aa17 8 ID (A) 6 003aab787 4 40 2 0 0 50 100 150 Tsp (°C) 200 0 0 50 100 150 200 Tsp (°C) P tot P der = ----------------------- × 100 % P tot ( 25 ° C ) Fig 1. Normalized total power dissipation as a function of solder point temperature 103 ID (A) 102 RDSon = VDS / ID VGS ≥ 5 V Fig 2. Continuous drain current as a function of solder point temperature 03nc54 tp = 10 µs 10 100 µs 1 ms 1 P tp δ= T DC 10 ms 100 ms 10-1 tp T t 10-2 10-1 1 10 VDS (V) 102 Tsp = 25 °C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 3 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 4. Symbol Rth(j-a) Rth(j-sp) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to solder point Conditions Min Typ 70 Max 15 Unit K/W K/W 102 Zth(j-sp) (K/W) 10 δ = 0.5 03nc55 0.2 1 0.1 0.05 0.02 10-1 Single Shot 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 10 tp T t P δ= tp T tp (s) 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 4 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 6. Characteristics Table 5. Characteristics Tj = 25 °C unless otherwise specified. Symbol V(BR)DSS Parameter Conditions Min Typ Max Unit Static characteristics drain-source breakdown voltage ID = 250 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 °C Tj = 150 °C Tj = −55 °C IDSS drain leakage current VDS = 55 V; VGS = 0 V Tj = 25 °C Tj = 150 °C IGSS RDSon gate leakage current VGS = ±10 V; VDS = 0 V Tj = 25 °C Tj = 150 °C VGS = 4.5 V; ID = 8 A VGS = 10 V; ID = 8 A Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 15 A; VGS = 0 V; see Figure 15 IS = 20 A; dIS/dt = −100 A/µs; VGS = −10 V; VR = 30 V VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω VGS = 0 V; VDS = 25 V; f = 1 MHz; see Figure 12 ID = 10 A; VDD = 44 V; VGS = 5 V; see Figure 14 11 1.6 4.6 438 87 62 8 118 20 32 0.85 33 60 584 104 85 1.2 nC nC nC pF pF pF ns ns ns ns V ns nC drain-source on-state resistance VGS = 5 V; ID = 8 A; see Figure 7 and 8 68 62 80 147 89 73 mΩ mΩ mΩ mΩ 0.05 2 10 500 100 µA µA nA 1 0.6 1.5 2 2.3 V V V 55 50 V V Source-drain diode BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 5 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 60 ID (A) 40 03nc51 80 RDSon (mΩ) 03nc50 VGS (V) = 10 7 6 5 4 60 20 3.4 3 2.4 2.2 0 0 2 4 6 8 VDS (V) 10 40 2 4 6 8 VGS (V) 10 Tj = 25 °C Tj = 25 °C; ID = 10 A Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 180 RDSon (mΩ) 150 03nc52 Fig 6. Drain-source on-state resistance as a function of gate-source voltage; typical values 2 a 1.8 1.6 1.4 1.2 03nc24 3 3.2 3.4 3.6 3.8 4 VGS (V) = 5 120 90 1 0.8 60 0.6 0.4 0.2 30 0 0 10 20 30 ID (A) 40 0 -60 -20 20 60 100 140 180 Tj (°C) Tj = 25 °C R DSon a = ----------------------------R DSon ( 25 °C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 7. Drain-source on-state resistance as a function of drain current; typical values BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 6 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 2.5 VGS(th) (V) 2 max 03aa33 10-1 ID (A) 10-2 03aa36 1.5 typ 10-3 min typ max 1 min 10-4 0.5 10-5 0 -60 10-6 0 60 120 Tj (°C) 180 0 1 2 VGS (V) 3 ID = 1 mA; VDS = VGS Tj = 25 °C; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature 12 gfs (S) 10 03nc48 Fig 10. Sub-threshold drain current as a function of gate-source voltage 1200 C (pF) 1000 03nc53 8 800 Ciss 6 600 4 400 Coss 2 200 Crss 0 0 5 10 15 ID (A) 20 0 10-2 10-1 1 10 VDS (V) 102 Tj = 25 °C; VDS = 25 V VGS = 0 V; f = 1 MHz Fig 11. Forward transconductance as a function of drain current; typical values Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 7 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 15 ID (A) 03nc49 5 VGS (V) 4 03nc47 10 3 VDS = 14 V VDS = 44 V 2 5 Tj = 150 °C 1 Tj = 25 °C 0 0 1 2 3 VGS (V) 4 0 0 5 10 QG (nC) 15 VDS = 25 V Tj = 25 °C; ID = 10 A Fig 13. Transfer characteristics: drain current as a function of gate-source voltage; typical values 60 IS (A) 40 03nc46 Fig 14. Gate-source voltage as a function of gate charge; typical values 10 IAL (A) 003aab771 (1) 1 (2) (3) 20 Tj = 150 °C Tj = 25 °C 0 0.0 10-1 0.5 1.0 1.5 VSD (V) 2.0 10-2 10-3 10-2 10-1 1 tAL (ms) 10 VGS = 0 V See Table note 1 of Table 3 “Limiting values”. (1) Single-pulse; Tj = 25 °C. (2) Single-pulse; Tj = 125 °C. (3) Repetitive. Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values Fig 16. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 8 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 7. Package outline Plastic surface-mounted package with increased heatsink; 4 leads SOT223 D B E A X c y HE b1 vMA 4 Q A A1 1 e1 e 2 bp 3 wM B detail X Lp 0 2 scale 4 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.8 1.5 A1 0.10 0.01 bp 0.80 0.60 b1 3.1 2.9 c 0.32 0.22 D 6.7 6.3 E 3.7 3.3 e 4.6 e1 2.3 HE 7.3 6.7 Lp 1.1 0.7 Q 0.95 0.85 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT223 REFERENCES IEC JEDEC JEITA SC-73 EUROPEAN PROJECTION ISSUE DATE 04-11-10 06-03-16 Fig 17. Package outline SOT223 (SC-73) BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 9 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 8. Revision history Table 6. Revision history Release date 20070412 Data sheet status Product data sheet Change notice Supersedes BUK9880_55A-01 Document ID BUK9880-55A_2 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 4 “Limiting values”: corrected VGS value from ±10 V to ±15 V. Product specification - BUK9880_55A-01 (9397 750 07736) 20010207 BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 10 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com BUK9880-55A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 April 2007 11 of 12 NXP Semiconductors BUK9880-55A N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 April 2007 Document identifier: BUK9880-55A_2