BUK9775-55A

BUK9775-55A N-channel TrenchMOS™ logic level FET M3D308 Rev. 02 — 10 June 2004 Product data 1. Description N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™1 technology, featuring very low on-state resistance. Product availability: BUK9775-55A in SOT186A (TO-220F). 2. Features s s s s TrenchMOS™ technology Q101 compliant 150 °C rated Logic level compatible. 3. Applications s Automotive and general purpose power switching: x 12 V and 24 V loads x Motors, lamps and solenoids. 4. Pinning information Table 1: Pin 1 2 3 mb Pinning - SOT186A, simplified outline and symbol Description gate (g) mb Simplified outline Symbol drain (d) source (s) mounting base; isolated g mbb076 d s 123 MBK110 SOT186A (TO-220F) 1. TrenchMOS is a trademark of Koninklijke Philips Electronics N.V. Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 5. Quick reference data Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions Tmb = 25 °C; VGS = 5 V Tmb = 25 °C Tj = 25 °C; VGS = 5 V; ID = 10 A Tj = 25 °C; VGS = 4.5 V; ID = 10 A Typ 63 Max 55 11 18 150 75 84 Unit V A W °C mΩ mΩ drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS VGSM ID drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) non-repetitive gate-source voltage drain current (DC) tp ≤ 50 µs Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 IDM Ptot Tstg Tj IDR IDRM peak drain current total power dissipation storage temperature operating junction temperature reverse drain current (DC) peak reverse drain current Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 11 A; VDS ≤ 55 V; VGS = 5 V; RGS = 50 Ω; starting T j = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 [1] Conditions RGS = 20 kΩ Min −55 −55 - Max 55 55 ±10 ±15 11 8 46 18 +150 +150 11 46 50 Unit V V V V A A A W °C °C A A mJ Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive avalanche energy [1] IDM is limited by chip, not package. 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 2 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 120 Pder (%) 100 03ne36 120 Ider (%) 100 03ne37 80 80 60 60 40 40 20 20 0 0 25 50 75 100 125 150 175 Tmb (oC) 0 0 25 50 75 100 125 150 175 o Tmb ( C) P tot P der = ---------------------- × 100 % P ° tot ( 25 C ) VGS ≥ 5 V ID I der = ------------------ × 100 % I ° D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 102 ID (A) 03ne03 limit RDSon = VDS/ ID tp = 10 µs 10 100 µs 1 ms 1 DC 10 ms 100 ms 10-1 1 10 VDS (V) 102 Tamb = 25 °C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 3 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 7. Thermal characteristics Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Figure 4 Min Typ Max Unit 55 6.8 K/W K/W thermal resistance from junction to mounting base Symbol Parameter thermal resistance from junction to ambient vertical in still air 7.1 Transient thermal impedance 10 Zth(j-mb) (K/W) δ = 0.5 0.2 03ne02 1 0.1 0.05 0.02 10-1 P δ= tp T Single Shot tp T t 10-2 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 4 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 0.25 mA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 150 °C Tj = −55 °C IDSS drain-source leakage current VDS = 55 V; VGS = 0 V Tj = 25 °C Tj = 150 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±10 V; VDS = 0 V VGS = 5 V; ID = 10 A; Figure 7 and 8 Tj = 25 °C Tj = 150 °C VGS = 4.5 V; ID = 10 A VGS = 10 V; ID = 10 A Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf Ld Ls total gate charge gate-to-source charge gate-to-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time internal drain inductance internal source inductance from drain lead 6 mm from package to centre of die from source lead 6 mm from package to source bond pad IS = 10 A; VGS = 0 V; Figure 15 IS = 20 A; dIS/dt = −100 A/µs VGS = −10 V; VDS = 30 V VDD = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 12 VGS = 5 V; VDD = 44 V; ID = 10 A; Figure 14 10.5 1.6 4.6 440 90 60 10 47 28 33 4.5 7.5 630 110 94 nC nC nC pF pF pF ns ns ns ns nH nH 63 57 75 138 84 68 mΩ mΩ mΩ mΩ 0.05 2 10 500 100 µA µA nA 1 0.6 1.5 2 2.3 V V V 55 50 V V Min Typ Max Unit Static characteristics Source-drain diode VSD trr Qr 9397 750 13328 source-drain (diode forward) voltage reverse recovery time recovered charge - 0.85 33 60 1.2 - V ns nC © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 5 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 60 VGS (V) = 8 ID (A) 40 03nd43 120 RDSon 7 6 (mΩ) 100 03nd42 10 5 80 4 20 60 3 0 0 2 4 6 8 2.2 10 VDS (V) 40 2 4 6 8 VGS (V) 10 Tj = 25 °C Tj = 25 °C; ID = 10 A Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Drain-source on-state resistance as a function of gate-source voltage; typical values. 2.2 a 2 1.8 1.6 03nc24 180 RDSon (mΩ) 160 140 120 100 80 60 40 0 03nd44 3 3.2 3.4 3.6 3.8 4 VGS (V) = 5 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 10 20 30 40 ID (A) 50 -20 20 60 100 140 180 o Tj ( C) Tj = 25 °C R DSon a = --------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 6 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 2.5 VGS(th) (V) 2 max 03aa33 10-1 ID (A) 10-2 03aa36 1.5 typ 10-3 min typ max 1 min 10-4 0.5 10-5 0 -60 10-6 0 60 120 Tj (°C) 180 0 1 2 VGS (V) 3 ID = 1 mA; VDS = VGS Tj = 25 °C; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. 15 gfs (S) 10 03nd40 Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03nd45 1200 C (pF) 1000 Ciss Coss 800 Crss 600 5 400 200 0 0 5 10 15 20 ID (A) 25 0 10-2 10-1 1 10 102 VDS (V) Tj = 25 °C; VDS = 25 V VGS = 0 V; f = 1 MHz Fig 11. Forward transconductance as a function of drain current; typical values. Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 7 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 25 ID (A) 20 03ne12 5 VGS (V) 4 VDD = 44(V) 03nd39 15 3 VDD = 14(V) 10 2 5 Tj = 150 oC 0 0 1 2 3 4 VGS (V) 5 Tj = 25 oC 1 0 0 5 10 QG (nC) 15 VDS = 25 V Tj = 25 °C; ID = 10 A Fig 13. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 50 IS (A) 40 Fig 14. Gate-source voltage as a function of gate charge; typical values. 03ne13 30 Tj = 150 oC 20 Tj = 25 oC 10 0 0.0 0.5 1.0 VSD (V) 1.5 VGS = 0 V Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 8 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 9. Package outline Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 'full pack' SOT186A E P q D1 T mounting base A A1 D j L2 b1 L b2 L1 K Q 1 2 b e e1 3 wM c 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.6 4.0 A1 2.9 2.5 b 0.9 0.7 b1 1.1 0.9 b2 1.4 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.5 6.3 E 10.3 9.7 e 2.54 e1 5.08 j 2.7 1.7 K 0.6 0.4 L L1 L2 max. 3 (1) P 3.2 3.0 Q 2.6 2.3 q 3.0 2.6 T (2) w 0.4 14.4 3.30 13.5 2.79 2.5 Notes 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. 2. Both recesses are ∅ 2.5 × 0.8 max. depth OUTLINE VERSION SOT186A REFERENCES IEC JEDEC 3-lead TO-220F JEITA EUROPEAN PROJECTION ISSUE DATE 02-03-12 02-04-09 Fig 16. SOT186A. 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 9 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 10. Revision history Table 6: 02 Revision history CPCN Description Product data (9397 750 13328) Modifications: Rev Date 20040610 • 01 20010215 - Latest version of package outline imported into data sheet. Product specification (9397 750 07997) 9397 750 13328 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 10 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET 11. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 12. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 13. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 9397 750 13328 Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 — 10 June 2004 11 of 12 Philips Semiconductors BUK9775-55A N-channel TrenchMOS™ logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 10 June 2004 Document order number: 9397 750 13328