LH75411N0Q100C0

LH75401/LH75411 Preliminary data sheet DESCRIPTION The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices. • LH75401 — contains the superset of features. • LH75411 — similar to LH75401, without CAN 2.0B. System-on-Chip • JTAG Debug Interface and Boundary Scan • Single 3.3 V Supply • 5 V Tolerant Digital I/O – XTALIN and XTAL32IN inputs are 1.8 V ± 10 % • 144-pin LQFP Package • −40°C to +85°C Operating Temperature COMMON FEATURES • Highly Integrated System-on-Chip • ARM7TDMI-S™ Core • High Performance (84 MHz CPU Speed) – Internal PLL Driven or External Clock Driven – Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz • 32 kB On-chip SRAM – 16 kB Tightly Coupled Memory (TCM) SRAM – 16 kB Internal SRAM • Clock and Power Management – Low Power Modes: Standby, Sleep, Stop • Eight Channel, 10-bit Analog-to-Digital Converter • Integrated Touch Screen Controller • Serial interfaces – Two 16C550-type UARTs supporting baud rates up to 921,600 baud (requires crystal frequency of 14.756 MHz). – One 82510-type UART supporting baud rates up to 3,225,600 baud (requires a system clock of 70 MHz). • Synchronous Serial Port – Motorola SPI™ – National Semiconductor Microwire™ – Texas Instruments SSI • Real-Time Clock (RTC) • Three Counter/Timers – Capture/Compare/PWM Compatibility – Watchdog Timer (WDT) • Low-Voltage Detector Unique Features of the LH75401 • Color and Grayscale Liquid Crystal Display (LCD) Controller – 12-bit (4,096) Direct Mode Color, up to VGA – 8-bit (256) Direct or Palettized Color, up to SVGA – 4-bit (16) Direct Mode Color/Grayscale, up to XGA – 12-bit Video Bus – Supports STN, TFT, HR-TFT, and AD-TFT Displays. • CAN Controller that supports CAN version 2.0B. Unique Features of the LH75411 • Color and Grayscale LCD Controller (LCDC) – 12-bit (4,096) Direct Mode Color, up to VGA – 8-bit (256) Direct or Palettized Color, up to SVGA – 4-bit (16) Direct Mode Color/Grayscale, up to XGA – 12-bit Video Bus – Supports STN, TFT, HR-TFT, and AD-TFT Displays. Preliminary data sheet 1 LH75401/LH75411 NXP Semiconductors System-on-Chip ORDERING INFORMATION Table 1. Ordering information Package Type number Name LH75401N0Q100C0 LH75411N0Q100C0 LQFP144 LQFP144 Description plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 SOT486-1 Version 2 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 LH75401 BLOCK DIAGRAM LH75401 14 to 20 MHz 32.768 kHz OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL REAL TIME CLOCK INTERNAL 16KB SRAM 76-BIT GENERAL PURPOSE I/O ARM7TDMI-S AHB INTERFACE VECTORED INTERRUPT CONTROLLER I/O CONFIGURATION TCM 16KB SRAM SYNCHRONOUS SERIAL PORT 4 CHANNEL DMA CONTROLLER STATIC MEMORY CONTROLLER TIMER (3) ADVANCED PERIPHERAL BUS BRIDGE WATCHDOG TIMER BROWNOUT DETECTOR COLOR LCD CONTROLLER CAN 2.0B LINEAR REGULATOR ADVANCED LCD INTERFACE UART (3) 8 CHANNEL 10-BIT ADC TOUCH PANEL INTERFACE ADVANCED HIGH PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB) LH75401-1 Figure 1. LH75401 Block Diagram Preliminary data sheet Rev. 01 — 16 July 2007 3 LH75401/LH75411 NXP Semiconductors System-on-Chip LH75411 BLOCK DIAGRAM LH75411 14 to 20 MHz 32.768 kHz OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL REAL TIME CLOCK INTERNAL 16KB SRAM 76-BIT GENERAL PURPOSE I/O ARM 7TDMI-S AHB INTERFACE VECTORED INTERRUPT CONTROLLER I/O CONFIGURATION TCM 16KB SRAM SYNCHRONOUS SERIAL PORT 4 CHANNEL DMA CONTROLLER STATIC MEMORY CONTROLLER TIMER (3) ADVANCED PERIPHERAL BUS BRIDGE WATCHDOG TIMER BROWNOUT DETECTOR COLOR LCD CONTROLLER UART (3) LINEAR REGULATOR ADVANCED HIGH PERFORMANCE BUS (AHB) ADVANCED LCD INTERFACE 8 CHANNEL 10-BIT ADC TOUCH PANEL INTERFACE ADVANCED PERPHERAL BUS (APB) LH75411-1 Figure 2. LH75411 Block Diagram 4 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 PIN CONFIGURATION 144 1 109 108 LH75401/ LH75411 36 37 72 73 002aad207 Figure 3. LH75401/LH75411 pin configuration Preliminary data sheet Rev. 01 — 16 July 2007 5 LH75401/LH75411 NXP Semiconductors System-on-Chip LH75401 Numerical Pin Listing Table 2. LH75401 Numerical Pin List PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 FUNCTION AT RESET PA7 PA6 VDD PA5 PA4 PA3 PA2 VSS PA1 PA0 VDDC D7 D6 VSSC D5 D4 VDD D3 D2 D1 D0 nWE nOE PB5 PB4 VSS PB3 PB2 PB1 PB0 nCS0 PC7 PC6 VDD PC5 PC4 PC3 PC2 A21 A20 A19 A18 A23 A22 Power nBLE0 nCS3 nCS2 nCS1 nWAIT nBLE1 Ground D9 D8 D13 D12 D11 D10 FUNCTION 2 D15 D14 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE I/O I/O Power I/O I/O I/O I/O Ground I/O I/O Power I/O I/O Ground I/O I/O Power I/O I/O I/O I/O 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA Bidirectional Bidirectional Bidirectional Bidirectional Pull-down Pull-down Pull-down Pull-down BUFFER TYPE Bidirectional Bidirectional BEHAVIOR DURING RESET Pull-up Pull-up NOTES 1 1 Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-up Pull-up Pull-up 1 1 1 1 Bidirectional Bidirectional Pull-up Pull-up 1 1 Bidirectional Bidirectional Pull-up Pull-up Bidirectional Bidirectional Pull-up Pull-up Bidirectional Bidirectional Bidirectional Bidirectional Output Output Bidirectional Bidirectional Pull-up Pull-up Pull-up Pull-up HIGH HIGH Pull-up Pull-up 3 3 1, 3 1, 3 Bidirectional Bidirectional Bidirectional Bidirectional Output Bidirectional Bidirectional Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-down 1, 3 1, 3 1, 3 1, 3 3 1 1 1 1 1 1 6 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 2. LH75401 Numerical Pin List (Cont’d) PIN NO. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FUNCTION AT RESET PC1 PC0 VSS VDD A15 A14 A13 A12 A11 VSS A10 A9 A8 A7 A6 VDD A5 A4 A3 A2 VSS A1 A0 nRESETIN TEST2 TEST1 TMS RTCK TCK TDI TDO LINREGEN nRESETOUT PD6 PD5 PD4 VDDC PD3 PD2 PD1 PD0 VSSC INT3 INT2 INT1 INT0 Ground UARTTX1 INT6 INT5 INT4 DREQ DACK UARTRX1 Power Ground Power Ground FUNCTION 2 A17 A16 Ground Power FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE 8 mA 8 mA None None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None None None None 8 mA None None 4 mA None 8 mA 6 mA 6 mA 8 mA None 8 mA 2 mA 6 mA 2 mA None Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-up 1 1 1, 2 1 Output Output Input Input Input Input Output Input Input Output Input Output Bidirectional Bidirectional Bidirectional Pull-up Pull-down 5 3 1 1, 2 1 Pull-up 2 LOW LOW Pull-up Pull-up Pull-up Pull-up 2, 3 2 2 2 Output Output Output Output LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW BUFFER TYPE Bidirectional Bidirectional BEHAVIOR DURING RESET Pull-down Pull-down NOTES 1 1 Preliminary data sheet Rev. 01 — 16 July 2007 7 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 2. LH75401 Numerical Pin List (Cont’d) PIN NO. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 FUNCTION AT RESET nPOR XTAL32IN XTAL32OUT VSSA_PLL VDDA_PLL XTALIN XTALOUT VSSA_ADC AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) VDDA_ADC VDD PE7 PE6 PE5 PE4 PE3 PE2 PE1 VSS PE0 PF6 PF5 PF4 PF3 VDD PF2 PF1 PF0 PG7 PG6 PG5 VSS PG4 PG3 PG2 LCDVEEEN LCDVDDEN LCDDSPLEN LCDREV LCDMOD CTCAP0E CTCAP0D CTCAP0C CTCAP0B CTCAP0A CTCLK Ground CTCMP0B CTCMP0A UARTRX2 CTCAP2B CTCAP2A CTCAP1B CTCAP1A CTCMP2B CTCMP2A CACMP1B CTCMP1A Power SSPFRM SSPCLK SSPRX SSPTX CANTX CANRX UARTTX2 Ground UARTTX0 UARTRX0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Power Power Ground Ground Power FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE None None None None None None None None None None None None None None None None None None 4 mA 4 mA 4 mA 4 mA 8 mA 2 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA None 8 mA 8 mA 8 mA Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 2 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 Pull-up 1 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-down Pull-up Pull-down Pull-up Pull-up Pull-up 1 1 1 1 1 1 1 Input Input Input Input Input Input Input Input Input Output 4 BUFFER TYPE Input Input Output BEHAVIOR DURING RESET Pull-up NOTES 2, 3 4 8 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 2. LH75401 Numerical Pin List (Cont’d) PIN NO. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 NOTES: 1. 2. 3. 4. 5. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with ‘n’ are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) LINREGEN activation requires a 0 Ω pull-up to VDD. FUNCTION AT RESET PG1 PG0 PH7 VDD VSS PH6 PH5 PH4 PH3 PH2 PH1 VDD PH0 PI7 PI6 PI5 PI4 VSS PI3 PI2 PI1 PI0 FUNCTION 2 LCDCLS LCDPS LCDDCLK FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE 8 mA 8 mA 8 mA Power Ground None None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Power None 8 mA 8 mA 8 mA 8 mA 8 mA Ground None 8 mA 8 mA 8 mA 8 mA BUFFER TYPE Bidirectional Bidirectional Bidirectional BEHAVIOR DURING RESET NOTES LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 LCDHRLP LCDSPS LCDSPL Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Preliminary data sheet Rev. 01 — 16 July 2007 9 LH75401/LH75411 NXP Semiconductors System-on-Chip LH75401 Signal Descriptions Table 3. LH75401 Signal Descriptions PIN NO. 1 2 4 5 6 7 9 10 12 13 15 16 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 38 39 40 43 44 45 46 47 49 50 51 52 53 55 56 57 58 60 61 72 73 SIGNAL NAME TYPE DESCRIPTION MEMORY INTERFACE (MI) NOTES D[15:0] Input/Output Data Input/Output Signals 1 nWE nOE nWAIT nBLE1 nBLE0 nCS3 nCS2 nCS1 nCS0 Output Output Input Output Output Output Output Output Output Static Memory Controller Write Enable Static Memory Controller Output Enable Static Memory Controller External Wait Control Static Memory Controller Byte Lane Strobe Static Memory Controller Byte Lane Strobe Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select 2 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 2 A[23:0] Output Address Signals 1 DMA CONTROLLER (DMAC) DREQ DACK Input Output DMA Request DMA Acknowledge 1 1 10 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. 120 120 121 122 122 123 124 125 128 128 129 129 130 130 131 132 133 135 136 137 138 139 141 142 143 144 99 100 101 102 103 104 74 76 105 107 103 104 SIGNAL NAME LCDMOD LCDVEEEN LCDVDDEN LCDDSPLEN LCDREV LCDCLS LCDPS LCDDCLK LCDLP LCDHRLP LCDFP LCDSPS LCDEN LCDSPL TYPE Output Output Output Output Output Output Output Output Output Output Output Output Output Output DESCRIPTION COLOR LCD CONTROLLER (CLCDC) Signal Used by the Row Driver (AD-TFT, HR-TFT only) Analog Supply Enable (AC Bias SIgnal) Digital Supply Enable LCD Panel Power Enable Reverse Signal (AD-TFT, HR-TFT only) Clock to the Row Drivers (AD-TFT, HR-TFT only) Power Save (AD-TFT, HR-TFT only) LCD Panel Clock Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) Latch Pulse (AD-TFT, HR-TFT only) Frame Pulse (STN), Vertical Synchronization Pulse (TFT) Row Driver Counter Reset Signal (AD-TFT, HR-TFT only) LCD Data Enable Start Pulse Left (AD-TFT, HR-TFT only) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES LCDVD[11:0] Output LCD Panel Data bus 1 SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPCLK SSPRX SSPTX UARTTX0 UARTRX0 UARTRX1 UARTTX1 UARTTX2 UARTRX2 CANTX CANRX Output Output Input Output Output Input Input Output Output Input Output Input SSP Serial Frame SSP Clock SSP RXD SSP TXD UART0 (U0) UART0 Transmitted Serial Data Output UART0 Received Serial Data Input UART1 (U1) UART1 Received Serial Data Input UART1 Transmitted Serial Data Output UART2 (U2) UART2 Transmitted Serial Data Output UART2 Received Serial Data Input CONTROLLER AREA NETWORK (CAN) CAN Transmitted Serial Data Output CAN Received Serial Data Input 1 1 1 1 1 1 1 1 1 1 1 1 Preliminary data sheet Rev. 01 — 16 July 2007 11 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. 89 90 91 92 93 94 95 96 117 116 115 114 113 117 116 118 111 110 111 110 118 109 108 109 108 118 1 2 4 5 6 7 9 10 24 25 27 28 29 30 32 33 35 36 37 38 39 40 SIGNAL NAME AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) TYPE DESCRIPTION ANALOG-TO-DIGITAL CONVERTER (ADC) NOTES Input ADC Inputs 1 TIMER 0 CTCAP0[A:E] Input Timer 0 Capture Inputs 1 CTCMP0[A:B] CTCLK Output Input Timer 0 Compare Outputs Common External Clock TIMER 1 1 1 CTCAP1[A:B] CTCMP1[A:B] CTCLK Input Output Input Timer 1 Capture Inputs Timer 1 Compare Outputs Common External Clock TIMER 2 1 1 1 CTCAP2[A:B] CTCMP2[A:B] CTCLK PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input Input Input Timer 2 Capture Inputs Timer 2 Compare Outputs Common External Clock GENERAL PURPOSE INPUT/OUTPUT (GPIO) 1 1 1 Input/Output General Purpose I/O Signals - Port A 1 Input/Output General Purpose I/O Signals - Port B 1 Input/Output General Purpose I/O Signals - Port C 1 12 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. 72 73 74 76 77 78 79 89 90 91 92 93 94 95 96 99 100 101 102 103 104 105 107 108 109 110 111 113 114 115 116 117 118 120 121 122 123 124 125 128 129 130 131 132 133 135 136 137 138 139 141 142 143 144 62 71 72 SIGNAL NAME PD6 PD5 PD4 PD3 PD2 PD1 PD0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 nRESETIN nRESETOUT INT6 TYPE DESCRIPTION NOTES Input/Output General Purpose I/O Signals - Port D 1 Input General Purpose I/O Signals - Port J 1 Input/Output General Purpose I/O Signals - Port E 1 Input/Output General Purpose I/O Signals - Port F 1 Input/Output General Purpose I/O Signals - Port G 1 Input/Output General Purpose I/O Signals - Port H 1 Input/Output General Purpose I/O Signals - Port I 1 RESET, CLOCK, AND POWER CONTROLLER (RCPC) Input Output Input User Reset Input System Reset Output External Interrupt Input 6 2 2 1 Preliminary data sheet Rev. 01 — 16 July 2007 13 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 3. LH75401 Signal Descriptions (Cont’d) PIN NO. 73 74 76 77 78 79 81 82 83 86 87 63 64 65 66 67 68 69 3 17 34 42 54 98 112 126 134 8 26 41 48 59 106 119 127 140 11 75 14 80 70 84 85 88 97 SIGNAL NAME INT5 INT4 INT3 INT2 INT1 INT0 nPOR XTAL32IN XTAL32OUT XTALIN XTALOUT TEST2 TEST1 TMS RTCK TCK TDI TDO TYPE Input Input Input Input Input Input Input Input Output Input Output Input Input Input Output Input Input Output External Interrupt Input 5 External Interrupt Input 4 External Interrupt Input 3 External Interrupt Input 2 External Interrupt Input 1 External Interrupt Input 0 Power-on Reset Input 32.768 kHz Crystal Clock Input 32.768 kHz Crystal Clock Output Crystal Clock Input Crystal Clock Output TEST INTERFACE Test Mode Pin 2 Test Mode Pin 1 JTAG Test Mode Select Input Returned JTAG Test Clock Output JTAG Test Clock Input JTAG Test Serial Data Input JTAG Test Data Serial Output POWER AND GROUND (GND) DESCRIPTION NOTES 1 1 1 1 1 1 2 VDD Power I/O Ring VDD VSS Power I/O Ring VSS VDDC VSSC LINREGEN VSSA_PLL VDDA_PLL VSSA_ADC VDDA_ADC Power Power Input Power Power Power Power Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input) Core VSS Linear Regulator Enable PLL Analog VSS PLL Analog VDD Supply A-to-D converter Analog VSS A-to-D converter Analog VDD Supply NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded with ‘n’ are active LOW. 14 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 LH75411 Numerical Pin Listing Table 4. LH75411 Numerical Pin List PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 FUNCTION AT RESET PA7 PA6 VDD PA5 PA4 PA3 PA2 VSS PA1 PA0 VDDC D7 D6 VSSC D5 D4 VDD D3 D2 D1 D0 nWE nOE PB5 PB4 VSS PB3 PB2 PB1 PB0 nCS0 PC7 PC6 VDD PC5 PC4 PC3 PC2 PC1 PC0 VSS A21 A20 A19 A18 A17 A16 Ground A23 A22 Power nBLE0 nCS3 nCS2 nCS1 nWAIT nBLE1 Ground D9 D8 D13 D12 D11 D10 FUNCTION 2 D15 D14 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE I/O I/O Power I/O I/O I/O I/O Ground I/O I/O Power I/O I/O Ground I/O I/O Power I/O I/O I/O I/O 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down BUFFER TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Output Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Bidirectional Bidirectional BEHAVIOR DURING RESET Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up HIGH HIGH Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-down NOTES 1 1 1 1 1 1 1 1 3 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 3 1 1 1 1 1 1 1 1 Preliminary data sheet Rev. 01 — 16 July 2007 15 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 4. LH75411 Numerical Pin List (Cont’d) PIN NO. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 FUNCTION AT RESET VDD A15 A14 A13 A12 A11 VSS A10 A9 A8 A7 A6 VDD A5 A4 A3 A2 VSS A1 A0 nRESETIN TEST2 TEST1 TMS RTCK TCK TDI TDO LINREGEN nRESETOUT PD6 PD5 PD4 VDDC PD3 PD2 PD1 PD0 VSSC nPOR XTAL32IN XTAL32OUT INT3 INT2 INT1 INT0 Ground UARTTX1 INT6 INT5 INT4 DREQ DACK UARTRX1 Power Ground Power Ground FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Power None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None None None None 8 mA None None 4 mA None 8 mA 6 mA 6 mA 8 mA None 8 mA 2 mA 6 mA 2 mA None None None None Input Input Output Pull-up 2, 3 4 Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-up 1 1 1, 2 1 Output Output Input Input Input Input Output Input Input Output Input Output Bidirectional Bidirectional Bidirectional Pull-up Pull-down 5 3 1 1, 2 1 Pull-up 2 LOW LOW Pull-up Pull-up Pull-up Pull-up 2, 3 2 2 2 Output Output Output Output LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW BUFFER TYPE BEHAVIOR DURING RESET NOTES 16 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 4. LH75411 Numerical Pin List (Cont’d) PIN NO. 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 FUNCTION AT RESET VSSA_PLL VDDA_PLL XTALIN XTALOUT VSSA_ADC AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) VDDA_ADC VDD PE7 PE6 PE5 PE4 PE3 PE2 PE1 VSS PE0 PF6 PF5 PF4 PF3 VDD PF2 PF1 PF0 PG7 PG6 PG5 VSS PG4 PG3 PG2 PG1 PG0 PH7 LCDVEEEN LCDVDDEN LCDDSPLEN LCDCLS LCDPS LCDDCLK LCDREV LCDMOD CTCAP0E CTCAP0D CTCAP0C CTCAP0B CTCAP0A CTCLK Ground CTCMP0B CTCMP0A UARTRX2 CTCAP2B CTCAP2A CTCAP1B CTCAP1A CTCMP2B CTCMP2A CACMP1B CTCMP1A Power SSPFRM SSPCLK SSPRX SSPTX UARTTX0 UARTRX0 UARTTX2 Ground PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Power Power Ground FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Ground Power None None None None None None None None None None None None None None None 4 mA 4 mA 4 mA 4 mA 8 mA 2 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 2 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 Pull-up 1 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-down Pull-up Pull-down Pull-up Pull-up Pull-up 1 1 1 1 1 1 1 Input Input Input Input Input Input Input Input Input Output 4 BUFFER TYPE BEHAVIOR DURING RESET NOTES Preliminary data sheet Rev. 01 — 16 July 2007 17 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 4. LH75411 Numerical Pin List (Cont’d) PIN NO. 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 NOTES: 1. 2. 3. 4. 5. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with ‘n’ are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) LINREGEN activation requires a 0 Ω pull-up to VDD. FUNCTION AT RESET VDD VSS PH6 PH5 PH4 PH3 PH2 PH1 VDD PH0 PI7 PI6 PI5 PI4 VSS PI3 PI2 PI1 PI0 FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Power Ground None None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Power None 8 mA 8 mA 8 mA 8 mA 8 mA Ground None 8 mA 8 mA 8 mA 8 mA BUFFER TYPE BEHAVIOR DURING RESET NOTES LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 LCDHRLP LCDSPS LCDSPL Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 18 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 LH75411 Signal Descriptions Table 5. LH75411 Signal Descriptions PIN NO. 1 2 4 5 6 7 9 10 12 13 15 16 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 38 39 40 43 44 45 46 47 49 50 51 52 53 55 56 57 58 60 61 72 73 SIGNAL NAME TYPE DESCRIPTION MEMORY INTERFACE (MI) NOTES D[15:0] Input/Output Data Input/Output Signals 1 nWE nOE nWAIT nBLE1 nBLE0 nCS3 nCS2 nCS1 nCS0 Output Output Input Output Output Output Output Output Output Static Memory Controller Write Enable Static Memory Controller Output Enable Static Memory Controller External Wait Control Static Memory Controller Byte Lane Strobe Static Memory Controller Byte Lane Strobe Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select 2 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 2 A[23:0] Output Address Signals 1 DMA CONTROLLER (DMAC) DREQ DACK Input Output DMA Request DMA Acknowledge 1 1 Preliminary data sheet Rev. 01 — 16 July 2007 19 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. 120 120 121 122 122 123 124 125 128 128 129 129 130 130 131 132 133 135 136 137 138 139 141 142 143 144 99 100 101 102 104 103 74 76 105 107 89 90 91 92 93 94 95 96 SIGNAL NAME LCDMOD LCDVEEEN LCDVDDEN LCDDSPLEN LCDREV LCDCLS LCDPS LCDDCLK LCDLP LCDHRLP LCDFP LCDSPS LCDEN LCDSPL TYPE Output Output Output Output Output Output Output Output Output Output Output Output Output Output DESCRIPTION COLOR LCD CONTROLLER (CLCDC) Signal Used by the Row Driver (AD-TFT, HR-TFT only) Analog Supply Enable (AC Bias SIgnal) Digital Supply Enable LCD Panel Power Enable Reverse Signal (AD-TFT, HR-TFT only) Clock to the Row Drivers (AD-TFT, HR-TFT only) Power Save (AD-TFT, HR-TFT only) LCD Panel Clock Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) Latch Pulse (AD-TFT, HR-TFT only) Frame Pulse (STN), Vertical Synchronization Pulse (TFT) Row Driver Counter Reset Signal (AD-TFT, HR-TFT only) LCD Data Enable Start Pulse Left (AD-TFT, HR-TFT only) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES LCDVD[11:0] Output LCD Panel Data bus 1 SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPCLK SSPRX SSPTX UARTRX0 UARTTX0 UARTRX1 UARTTX1 UARTTX2 UARTRX2 AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) Output Output Input Output Input Output Input Output Output Input SSP Serial Frame SSP Clock SSP RXD SSP TXD UART0 (U0) UART0 Received Serial Data Input UART0 Transmitted Serial Data Output UART1 (U1) UART1 Received Serial Data Input UART1 Transmitted Serial Data Output UART2 (U2) UART2 Transmitted Serial Data Output UART2 Received Serial Data Input ANALOG-TO-DIGITAL CONVERTER (ADC) 1 1 1 1 1 1 1 1 1 1 Input ADC Inputs 1 20 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. 117 116 115 114 113 117 116 118 111 110 111 110 118 109 108 109 108 118 1 2 4 5 6 7 9 10 24 25 27 28 29 30 32 33 35 36 37 38 39 40 72 73 74 76 77 78 79 SIGNAL NAME TYPE TIMER 0 DESCRIPTION NOTES CTCAP0[A:E] Input Timer 0 Capture Inputs 1 CTCMP0[A:B] CTCLK Output Input Timer 0 Compare Outputs Common External Clock TIMER 1 1 1 CTCAP1[A:B] CTCMP1[A:B] CTCLK Input Output Input Timer 1 Capture Inputs Timer 1 Compare Outputs Common External Clock TIMER 2 1 1 1 CTCAP2[A:B] CTCMP2[A:B] CTCLK PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input Input Input Timer 2 Capture Inputs Timer 2 Compare Outputs Common External Clock GENERAL PURPOSE INPUT/OUTPUT (GPIO) 1 1 1 Input/Output General Purpose I/O Signals - Port A 1 Input/Output General Purpose I/O Signals - Port B 1 Input/Output General Purpose I/O Signals - Port C 1 Input/Output General Purpose I/O Signals - Port D 1 Preliminary data sheet Rev. 01 — 16 July 2007 21 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. 89 90 91 92 93 94 95 96 99 100 101 102 103 104 105 107 108 109 110 111 113 114 115 116 117 118 120 121 122 123 124 125 128 129 130 131 132 133 135 136 137 138 139 141 142 143 144 62 71 72 73 74 76 77 78 79 SIGNAL NAME PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 nRESETIN nRESETOUT INT6 INT5 INT4 INT3 INT2 INT1 INT0 TYPE DESCRIPTION NOTES Input General Purpose I/O Signals - Port J 1 Input/Output General Purpose I/O Signals - Port E 1 Input/Output General Purpose I/O Signals - Port F 1 Input/Output General Purpose I/O Signals - Port G 1 Input/Output General Purpose I/O Signals - Port H 1 Input/Output General Purpose I/O Signals - Port I 1 RESET, CLOCK, AND POWER CONTROLLER (RCPC) Input Output Input Input Input Input Input Input Input User Reset Input System Reset Output External Interrupt Input 6 External Interrupt Input 5 External Interrupt Input 4 External Interrupt Input 3 External Interrupt Input 2 External Interrupt Input 1 External Interrupt Input 0 2 2 1 1 1 1 1 1 1 22 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Table 5. LH75411 Signal Descriptions (Cont’d) PIN NO. 81 82 83 86 87 63 64 65 66 67 68 69 3 17 34 42 54 98 112 126 134 8 26 41 48 59 106 119 127 140 11 75 14 80 70 84 85 88 97 NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded with ‘n’ are active LOW. SIGNAL NAME nPOR XTAL32IN XTAL32OUT XTALIN XTALOUT TEST2 TEST1 TMS RTCK TCK TDI TDO TYPE Input Input Output Input Output Input Input Input Output Input Input Output Power-on Reset Input DESCRIPTION 32.768 kHz Crystal Clock Input 32.768 kHz Crystal Clock Output Crystal Clock Input Crystal Clock Output TEST INTERFACE Test Mode Pin 2 Test Mode Pin 1 JTAG Test Mode Select Input Returned JTAG Test Clock Output JTAG Test Clock Input JTAG Test Serial Data Input JTAG Test Data Serial Output POWER AND GROUND (GND) NOTES 2 VDD Power I/O Ring VDD VSS Power I/O Ring VSS VDDC VSSC LINREGEN VSSA_PLL VDDA_PLL VSSA_ADC VDDA_ADC Power Power Input Power Power Power Power Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input) Core VSS Linear Regulator Enable PLL Analog VSS PLL Analog VDD Supply A-to-D converter Analog VSS A-to-D converter Analog VDD Supply Preliminary data sheet Rev. 01 — 16 July 2007 23 LH75401/LH75411 NXP Semiconductors System-on-Chip LCD TOUCH SCREEN CAN TRANSCEIVER CAN NETWORK CAN 2.0B STN/TFT, AD-TFT/HR-TFT A/D FLASH LH75401 SRAM A/D UART SENSOR ARRAY GPIO SSP BOOT ROM 1 4 7 2 5 8 0 3 6 9 # * SERIAL EEPROM KEY MATRIX LH754xx-2A Figure 4. LH75401 System Application Example FUNCTIONAL OVERVIEW ARM7TDMI-S Processor The LH75401/LH75411 microcontrollers feature the ARM7TDMI-S core with an Advanced High-Performance Bus (AHB) 2.0 interface. The ARM7TDMI-S is a 16/32-bit embedded RISC processor and a member of the ARM7 Thumb family of processors. For more information, visit the ARM Web site at www.arm.com. Power Supplies Five-Volt-tolerant 3.3 V I/Os are employed. The LH75401/LH75411 microcontrollers require a single 3.3 V supply. The core logic requires 1.8 V, supplied by an on-chip linear regulator. Core logic power may also be supplied externally to achieve higher system speeds. See the Electrical Specifications. Clock Sources The LH75401/LH75411 microcontrollers may use two crystal oscillators, or an externally supplied clock. There are two clock trees: • One clock tree drives an internal Phase Lock Loop (PLL) and the three UARTs. It supports a crystal oscillator frequency range from 14 MHz to 20 MHz. • The other is a 32.768 kHz oscillator that generates a 1 Hz clock for the RTC. (Use of the 32.768 kHz crystal for the Real Time Clock is optional. If not using the crystal, tie XTAL32IN to VSS and allow XTAL32OUT to float.) The 14-to-20 MHz crystal oscillator drives the UART clocks, so an oscillator frequency of 14.7456 MHz is recommended to achieve modem baud rates. The PLL may be bypassed and an external clock supplied at XTALIN; the SoC will operate to DC with the PLL disabled. When doing so, allow XTALOUT to float. The input clock with the PLL bypassed will be twice the desired system operating frequency, and care must be taken not to exceed the maximum input clock voltage. Maximum values for system speeds and input voltages are given in the Electrical Specifications. Bus Architecture The LH75401/LH75411 microcontrollers use the ARM Advanced Microcontroller Bus Architecture (AMBA) 2.0 internal bus protocol. Three AHB masters control access to external memory and on-chip peripherals: • The ARM processor fetches instructions and transfers data • The Direct Memory Access Controller (DMAC) transfers from memory to memory, from peripheral to memory, and from memory to peripheral • The LCDC refreshes an LCD panel with data from the external memory or from internal memory if the frame buffer is 16 kB or less. The ARM7TDMI-S processor is the default bus master. An Advanced Peripheral Bus (APB) bridge is provided to access to the various APB peripherals. Generally, APB peripherals are serviced by the ARM core. However, if they are DMA-enabled, they are also serviced by the DMAC to increase system performance while the ARM core runs from local internal memory. 24 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Reset Generation EXTERNAL RESETS Two external signals generate resets to the ARM7TDMI-S core: • nPOR sets all internal registers to their default state when asserted. It is used as a Power-On Reset. • nRESETIN sets all internal registers, except the JTAG circuitry, to their default state when asserted. When nPOR is asserted, nRESETIN defines the microcontroller Test Mode. When nPOR is released, nRESETIN behaves during Reset as described previously. INTERNAL RESETS There are two types of Internal Resets generated: • System Reset • RTC Reset. System and RTC Resets are asserted by: • An External Reset (a logic LOW signal on the external nRESETIN or nPOR input pin) • A signal from the internal Watchdog Timer • A Soft Reset. The reset latency depends on the PLL lock state. Memory Interface Architecture The LH75401/LH75411 microcontrollers provide the following data-path management resources on chip: • AHB and APB data buses • 16 kB of zero-wait-state TCM SRAM accessible via processor • 16 kB of internal SRAM accessible via processor, DMAC, and LCDC • A Static Memory Controller (SMC) that controls access to external memory • A 4-stream general-purpose DMAC. All external and internal system resources are memory-mapped. This memory map partition has three views, based on the setting of the REMAP bits in the Reset, Clock, and Power Controller (RCPC). The second partitioning of memory space is the dividing of the segments into sections. The external memory segment is divided into eight 64 MB sections, of which the first four are used, each having a chip select associated with it. Access to any of the last four sections does not result in an external bus access and does not cause a memory abort. The peripheral register segment is divided into 4 kB peripheral sections, 21 of which are assigned to peripherals. Table 7. Memory Mapping ADDRESS 0x00000000 0x20000000 0x40000000 0x60000000 REMAP = 00 REMAP = 01 REMAP = 10 (DEFAULT) External Memory Reserved External Memory Internal SRAM TCM SRAM Reserved Reserved Reserved Internal SRAM Reserved External Memory Internal SRAM TCM SRAM Reserved Reserved Reserved TCM SRAM Reserved External Memory Internal SRAM TCM SRAM Reserved Reserved Reserved AHB Master Priority and Arbitration The LH75401/LH75411 microcontrollers have three AHB masters: • ARM processor • DMAC • LCD Controller. Each AHB master has a priority level that is permanent and cannot change. Table 6. Bus Master Priority PRIORITY 1 (Highest) 2 3 (Lowest) BUS MASTER PRIORITY Color LCDC (LH75401 and LH75411) DMAC ARM7TDMI-S Core (Default) 0x80000000 0xA0000000 0xC0000000 0xE0000000 0xFFFBFFFF Preliminary data sheet Rev. 01 — 16 July 2007 25 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 8. APB Peripheral Register Mapping ADDRESS RANGE DEVICE • Supports memory-mapped devices, including Random Access Memory (RAM), Read Only Memory (ROM), Flash, and burst ROM • Supports external bus and external device widths of 8 and 16 bits • Supports Asynchronous Burst Mode read access for Burst Mode ROM devices, with up to 32 independent wait states for read and write accesses • Supports indefinite extended wait states via an external hardware pin (nWAIT) • Supports varied bus turnaround cycles (1 to 16) between a read and write operation 0xFFFC0000 - 0xFFFC0FFF UART0 (16550) 0xFFFC1000 - 0xFFFC1FFF UART1 (16550) 0xFFFC2000 - 0xFFFC2FFF UART2 (82510) 0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Converter 0xFFFC4000 - 0xFFFC4FFF Timer Module 0xFFFC5000 - 0xFFFC5FFF CAN (LH75401) Reserved (LH75411) 0xFFFC6000 - 0xFFFC6FFF Synchronous Serial Port 0xFFFC7000 - 0xFFFDAFFF Reserved 0xFFFDB000 - 0xFFFDBFFF GPIO4 0xFFFDC000 - 0xFFFDCFFF GPIO3 0xFFFDD000 - 0xFFFDDFFF GPIO2 0xFFFDE000 - 0xFFFDEFFF GPIO1 0xFFFDF000 - 0xFFFDFFFF GPIO0 0xFFFE0000 - 0xFFFE0FFF Real Time Clock 0xFFFE1000 - 0xFFFE1FFF DMAC 0xFFFE2000 - 0xFFFE2FFF Reset Clock and Power Controller Direct Memory Access Controller (DMAC) One central DMAC services all peripheral DMA requirements for the DMA-capable peripherals listed in Table 9. The DMA is controlled by the system clock. It has an APB slave port for programming of its registers and an AHB port for data transfers. Table 9. DMAC Stream Assignments DMA REQUEST SOURCE UART1RX (highest priority) UART1TX UART0RX/External Request (DREQ) UART0TX (lowest priority) DMA STREAM Stream0 Stream1 Stream2 Stream3 0xFFFE3000 - 0xFFFE3FFF Watchdog Timer 0xFFFE4000 - 0xFFFE4FFF Advanced LCD Interface 0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral 0xFFFE6000 - 0xFFFEFFFF Reserved Static Random Access Memory Controller The LH75401/LH75411 microcontrollers have 32 kB of Static Random Access Memory (SRAM) organized into two 16 kB blocks: • 16 kB of TCM 0 Wait State SRAM is available to the processor as an ARM7TDMI-S bus slave. • 16 kB of internal SRAM is available as an AHB slave and accessible via processor, DMAC, and LCDC. Each memory segment is 512 MB, though the TCM and internal SRAMs are 16 kB each in size. Any access beyond the first 16 kB is mapped to the lower 16 kB, but does not cause a data or prefetch abort. DMAC FEATURES • Four data streams that can be used to service: – Four peripheral data streams (peripheral-tomemory or memory-to-peripheral) – Three peripheral data streams and one memoryto-memory data stream. • Three transfer modes: – Memory to Memory (selectable on Stream3) – Peripheral to Memory (all streams) – Memory to Peripheral (all streams). • Built-in data stream arbiter • Seven programmable registers for each stream • Ability for each stream to indicate a transfer error via an interrupt • 16-word First-In, First Out (FIFO) array, with pack and unpack logic to handle all input/output combinations of byte, half-word, and word transfers • APB slave port allows the ARM core to program DMAC registers • AHB port for data transfers. Static Memory Controller (SMC) The Static Memory Controller (SMC) is an AMBA AHB slave peripheral that provides the interface between the LH75401/LH75411 microcontrollers and external memory devices. SMC FEATURES • Provides four banks of external memory, each with a maximum size of 16 MB. 26 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Color LCD Controller (CLCDC) The CLCDC is an AMBA master-slave module that connects to the AHB. It translates pixel-coded data into the required formats and timings to drive single/dual monochrome and color LCD panels. Packets of pixelcoded data are fed, via the AHB interface, to two independently programmable, 32-bit-wide DMA FIFOs. Each FIFO is 16 words deep by 32 bits wide. The CLCDC generates a single combined interrupt to the Vectored Interrupt Controller (VIC) when an interrupt condition becomes true for upper/lower panel DMA FIFO underflow, base address update signification, vertical compare, or bus error. NOTE: LH75401 and LH75411 microcontrollers support full-color operation. ADVANCED LCD INTERFACE The Advanced LCD Interface (ALI) allows for direct connection to ultra-thin panels that do not include a timing ASIC. It converts TFT signals from the Color LCD controller to provide the proper signals, timing and levels for direct connection to a panel’s Row and Column drivers for AD-TFT, HR-TFT, or any technology of panel that allows for a connection of this type. The ALI also provides a bypass mode that allows interfacing to the builtin timing ASIC in standard TFT and STN panels. NOTES: 1. The Advanced LCD Interface pertains to the LH75401 and LH75411 microcontrollers. 2. VGA and XGA modes require 66 MHz core speed. CLCDC FEATURES • STN, Color STN, TFT, HR-TFT, and AD-TFT – Fully Programmable Timing Controls – Advanced LCD Interface for displays with a low level of integration, such as HR-TFT and AD-TFT • Programmable Resolution – Up to VGA (640 × 480 DPI), 12-bit Direct Mode Color – Up to SVGA (800 × 600 DPI), 8-bit Direct/Palettized Color – Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/ Grayscale – Direct or Palettized Colors • Single and Dual Panels • Supports Sharp and non-Sharp Panels • CLCDC Outputs Available as General Purpose Inputs/Outputs (GPIOs) if LCDC is Not Needed • Additional Features – Fully programmable horizontal and vertical timing for different display panels – 256-entry, 16-bit palette RAM physically arranged as a 128 × 32-bit RAM – AC bias signal for STN panels and a data-enable signal for TFT panels. • Programmable Panel-related Parameters – STN mono/color or TFT display – Bits-per-pixel – STN 4- or 8-bit Interface Mode – STN Dual or Single Panel Mode – AC panel bias – Panel clock frequency – Number of panel clocks per line – Signal polarity, active HIGH or LOW – Little Endian data format – Interrupt-generation event. Universal Asynchronous Receiver Transmitters (UARTs) The LH75401/LH75411 microcontrollers incorporate three UARTs, designated UART0, UART1, and UART2. UART 0 AND 1 FEATURES • Similar functionality to the industry-standard 16C550 • Supported baud rates up to 921,600 baud (given an external crystal frequency of 14.756 MHz) • Supported character formats: – Data bits per character: 5, 6, 7, or 8 – Parity generation and detection: Even, odd, stick, or none – Stop bit generation: 1 or 2 • Full-duplex operation • Separate transmit and receive FIFOs, with: – Programmable depth (1 to 16) – Programmable-service ‘trigger levels’ (1/8, 1/4, 1/2, 3/4, and 7/8) – Overrun protection. • Programmable baud-rate generator that: – Enables the UART input clock to be divided by 16 to 65,535 × 16 – Generates an internal clock common to both transmit and receive portions of the UART. • DMA support • Support for generating and detecting breaks during UART transactions • Loopback testing. Preliminary data sheet Rev. 01 — 16 July 2007 27 LH75401/LH75411 NXP Semiconductors System-on-Chip UART 2 FEATURES • Similar functionality to the industry-standard 82510 • Supported baud rates up to 3,225,600 baud (given a system clock of 51.6096 MHz) • 5, 6, 7, 8, or 9 data bits per character • Even, odd, HIGH, LOW, software, or no parity-bit generation and detection • 3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation • µLAN address flag • Full-duplex operation • Separate transmit and receive FIFOs, with programmable depth (1 or 4). Each FIFO has overrun protection and: – Programmable receive trigger levels: 1/4, 1/2, 3/4, or full – Programmable transmit trigger levels: empty, 1/4, 1/2, 3/4. • Two 16-bit baud-rate generators. • One interrupt that can be triggered by transmit and receive FIFO thresholds, receive errors, control character or address marker reception, or timer timeout • Generation and detection of breaks during UART transactions • Support for local loopback, remote loopback, and auto-echo modes • µLAN Address Mode. The timers support a PWM Mode that uses the two Timer Compare Registers associated with a timer to create a PWM. Each timer can generate a separate interrupt. The interrupt becomes active if any enabled compare, capture, or overflow interrupt condition occurs. The interrupt remains active until all compare, capture, and overflow interrupts are cleared. Real Time Clock (RTC) The RTC is an AMBA slave module that connects to the APB. The RTC provides basic alarm functions or acts as a long-time base counter by generating an interrupt signal after counting for a programmed number of cycles of an RTC input. Counting in 1-second intervals is achieved using a 1 Hz clock input to the RTC. RTC FEATURES • 32-bit up-counter with programmable load • Programmable 32-bit match Compare Register • Software-maskable interrupt that is set when the Counter and Compare Registers have identical values. Controller Area Network (CAN) The CAN 2.0B Controller is an AMBA-compliant peripheral that connects as a slave to the APB. The CAN Controller is located between the processor core and a CAN Transceiver, and is accessed through the AMBA port. CAN communications are performed serially, at a maximum frequency of 1 MB/s, using the TX (transmit) and RX (receive) lines. The TX and RX signals for data transmission and reception provide the communications interface between the CAN Controller and the CAN bus. All peripherals share the TX and RX lines, and always see the common incoming and outgoing data. Bus arbitration follows the CAN 2.0A and CAN 2.0B specifications. The bus is always controlled by the node with the highest priority (lowest ID). Only after the bus has been released can the next highest priority node control it. Transmit and receive errors are handled according to the CAN protocol. Bus timing is critical to the CAN protocol. Therefore, the CAN Controller has two programmable Bus Timing Registers that define timing parameters. NOTE: The CAN Controller pertains to the LH75401 microcontrollers. Timers The LH75401/LH75411 microcontrollers have three 16-bit timers. The timers are clocked by the system clock, but have an internal scaled-down system clock that is used for the Pulse Width Modulator (PWM) and compare functions. All counters are incremented by an internal prescaled counter clock or external clock and can generate an overflow interrupt. All three timers have separate internal prescaled counter clocks, with either a common external clock or a prescaled version of the system clock. • Timer 0 has five Capture Registers and two Compare Registers. • Timer 1 and Timer 2 have two Capture and two Compare Registers each. The Capture Registers have edge-selectable inputs and can generate an interrupt. The Compare Registers can force the compare output pin either HIGH or LOW upon a match. 28 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 CAN 2.0B FEATURES • Full compliance with 2.0A and 2.0B Bosch specifications • Supports 11-bit and 29-bit identifiers • Supports bit rates up to 1Mbit/s • 64-byte receive FIFO • Software-driven bit-rate detection for hot plug-in support • Single-shot transmission option • Acceptance filtering • Listen Only Mode • Reception of ‘own’ messages • Error interrupt generated for each CAN bus error • Arbitration-lost interrupt with record of bit position • Read/write error counters • Last error register • Programmable error-limit warning. • Touch-pressure sensing circuits • Pen-down sensing circuit and interrupt generator • Voltage-reference generator that is independently controlled • Conversion automation function to minimize controller interrupt overhead • Brownout Detector. Synchronous Serial Port (SSP) The SSP is a master-only interface for synchronous serial communication with slave peripheral devices that have a Motorola SPI, National Semiconductor Microwire, or Texas Instruments DSP-compatible Synchronous Serial Interface (SSI). The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories. These memories store eight 16-bit values independently in both transmit and receive modes. During transmission: • Data writes to the transmit FIFO via the APB interface. • The transmit data is queued for parallel-to-serial conversion onto the transmit interface. • The transmit logic formats the data into the appropriate frame type: – Motorola SPI – National Semiconductor Microwire – Texas Instruments DSP-compatible SSI. SSP FEATURES • SSI in Master Only Mode. The SSP performs serial communications as a master device in one of three modes: – Motorola SPI – Texas Instruments DSP-compatible synchronous serial interface – National Semiconductor Microwire. • Two 16-bit-wide, 8-entry-deep FIFOs, one for data transmission and one for data reception. • Supports interrupt-driven data transfers that are greater than the FIFO watermark. • Programmable clock bit rate. • Programmable data frame size, from 4 to 16 bits long, depending on the size of data programmed. Each frame transmits starting with the most-significant bit. • Four interrupts, each of which can be individually enabled or disabled using the SSP Control Register bits. A combined interrupt is also generated as an OR function of the individual interrupt requests. • Loopback Test Mode. Analog-to-Digital Converter (ADC)/ Brownout Detector The ADC is an AMBA-compliant peripheral that connects as a slave to the APB. The ADC block consists of an 8-channel, 10-bit Analog-to-Digital Converter with integrated Touch Screen Controller. The complete Touch Screen interface is achieved by combining the front-end biasing, control circuitry with analog-to-digital conversion, reference generation, and digital control. The ADC also has a programmable measurement clock derived from the system clock. The clock drives the measurement sequencer and the successiveapproximation circuitry. The ADC includes a Brownout Detector. The Brownout Detector is an asynchronous comparator that compares a divided version of the 3.3 V supply and a bandgap-derived reference voltage. If the supply dips below a Trip point, the Brownout Detector sets a status register bit. The status bit is wired to the VIC and can interrupt the processor core. This allows the Host Controller to warn users of an impending shutdown and may provide the ADC with sufficient time to save its state. ADC/BROWNOUT DETECTOR FEATURES • 10-bit fully differential Successive Approximation Register (SAR) with integrated sample/hold • 8-channel multiplexer for routing user-selected inputs to the ADC in Single Ended and Differential Modes • 16-entry × 16-bit-wide FIFO that holds the 10-bit ADC output and a 4-bit tag number • Front bias-and-control network for Touch Screen interface and support functions compatible with industry-standard 4- and 5-wire touch-sensitive panels Preliminary data sheet Rev. 01 — 16 July 2007 29 LH75401/LH75411 NXP Semiconductors System-on-Chip Table 10. SSP Modes MODE Motorola SPI SSI DESCRIPTION DATA TRANSFERS For communications with Motorola SPI-compatible Full-duplex, 4-wire devices. Clock polarity and phase are programmable. synchronous For communications with Texas Instruments DSPcompatible Serial Synchronous Interface devices. Full-duplex, 4-wire synchronous Half-duplex synchronous, using 8-bit control messages National Semiconductor For communications with National Semiconductor Microwire Microwire-compatible devices. Watchdog Timer (WDT) The WDT consists of a 32-bit down-counter that allows a selectable time-out interval to detect malfunctions. The timer must be reset by software periodically. Otherwise, a time-out occurs, interrupting the system. If the interrupt is not serviced within the timeout period, the WDT triggers the RCPC to generate a System Reset. If the WDT times out, it sets a bit in the RCPC Reset Status Register. The WDT supports 16 selectable time intervals, for a time-out of 216 through 231 system clock cycles. All Control and Status Registers for the Watchdog Timer are accessed through the APB. WDT FEATURES • Counter generates an interrupt at a set interval and the count reloads from the pre-set value after reaching zero. • Default timeout period is set to the minimum timeout of 216 system clock cycles. • WDT is driven by the APB. • Built-in protection mechanism interrupt-service failure. guards against • WDT can be programmed to trigger a System Reset on a timeout. • WDT can be programmed to trigger an interrupt on the first timeout; then, if the service routine fails to clear the interrupt, the next WDT timeout triggers a System Reset. 30 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Vectored Interrupt Controller (VIC) All internal and external interrupts are routed to the VIC, where hardware determines the interrupt priority (see Table 11). The VIC is also where the appropriate signal to the processor (IRQ or FIQ) is generated. The processor services the interrupt as either a vectored interrupt or a default-vectored interrupt. The VIC accepts inputs from 32 interrupt source lines: • Seven external • Twenty-three internal • Two used as software interrupts. All 32 interrupt source lines can be enabled, disabled, and cleared individually, and individual status can be determined. On reset, all interrupts are disabled. The VIC also accepts software-generated interrupts. Software-generated interrupts use the same enabling control as hardware-generated interrupts. The VIC provides 32 interrupts: • 16 vectored interrupts • 16 or more default-vectored interrupts. Any of the 32 interrupt source lines can be assigned to any of the 16 interrupt vectors. Any line not explicitly assigned to an interrupt vector is processed as a default-vectored interrupt. At reset, all 32 lines become default-vectored interrupts. Each interrupt line can be explicitly identified as an IRQ (default) or FIQ interrupt. Vectored-interrupt servicing is only available for IRQ interrupts. Table 11. Interrupt Channels POSITION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DESCRIPTION WDT Not Used ARM7 DBGCOMMRX ARM7 DBGCOMMTX Timer0 Combined Timer1 Combined Timer2 Combined External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 Not Used RTC_ALARM ADC TSCIRQ (combined) ADC BrownOutINTR ADC PenIRQ LCD SSPTXINTR SSPRXINTR SSPRORINTR SSPRXTOINTR SSPINTR UART1 UARTRXINTR UART1 UARTTXINTR UART1 UARTINTR UART0 UARTINTR UART2 Interrupt DMA CAN SOURCE Watchdog Timer Available as a software interrupt Sourced by the ARM7TDMI-S Core Sourced by the ARM7TDMI-S Core Timer0 Timer1 Timer2 Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Available as a software interrupt Real Time Clock Analog-to-Digital Converter Brown Out Detector Analog-to-Digital Converter LCD Controller Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port UART1 UART1 UART1 UART0 UART2 DMA CAN (LH75401) Reserved (LH75411) Preliminary data sheet Rev. 01 — 16 July 2007 31 LH75401/LH75411 NXP Semiconductors System-on-Chip Reset, Clock, and Power Controller (RCPC) The RCPC lets users control System Reset, clocks, power management, and external interrupt conditioning via the AMBA APB interface. This control includes: • Enabling and disabling various clocks • Managing power-down sequencing • Selecting the sources for various clocks. The RCPC provides for an orderly start-up until the crystal oscillator stabilizes and the PLL acquires lock. If users want to change the system clock frequency during normal operation, the RCPC ensures a seamless transition between the old and new frequencies. RCPC FEATURES • Manages five Power Modes for minimizing power consumption: Active, Standby, Sleep, Stop1, and Stop2 • Generates the system clock (HCLK) from either the PLL clock or the PLL-bypassed (oscillator) clock, divided by 2, 4, 6, 8, … 30 • Generates three UART clocks from oscillator clock • Generates the 1 Hz RTC clock • Generates the SSP and LCD clocks from HCLK, divided by 1, 2, 4, 8, 16, 32, or 64 • Provides a selectable external clock output • Generates system and RTC Resets based on an external reset, Watchdog Timer reset, or soft reset • Configures seven HIGH/LOW-level or rising/falling edge-trigger external interrupts and converts them to HIGH-level trigger interrupt outputs required by the VIC • Generates remap outputs used by the memory map decoder • Provides an identification register • Supports external or watchdog reset status. The state of the TEST1, TEST2, and nRESETIN signals determines the operating mode entered at Poweron Reset (see Table 12). Table 12. Device Operating Modes OPERATING MODE Reserved PLL Bypass Reserved Reserved EmbeddedICE Normal TEST2 0 0 0 1 1 1 TEST1 0 0 1 0 0 1 nRESETIN 0 1 x 0 1 x NOTE: TEST1, TEST2, and nRESETIN are latched on the rising edge of nPOR. The microcontroller stays in that operating mode until power is removed or nPOR transitions from LOW to HIGH. General Purpose Input/Output (GPIO) The LH75401/LH75411 microcontrollers have 10 GPIO ports: • Seven 8-bit ports • Two 7-bit ports • One 6-bit port. The GPIO ports are designated A through J and provide 76 bits of programmable input/output (see Table 13). Pins of all ports, except Port J, can be configured as inputs or outputs. Port J is input only. Upon System Reset, all ports default to inputs. Table 13. GPIO Ports PORT A B C D E F G H I J PROGRAMMABLE PINS 8 Input/Output Pins 6 Input/Output Pins 8 Input/Output Pins 7 Input/Output Pins 8 Input/Output Pins 7 Input/Output Pins 8 Input/Output Pins 8 Input/Output Pins 8 Input/Output Pins 8 Input Pins Operating Modes The LH75401/LH75411 microcontrollers support three operating modes: • Normal Mode • PLL Bypass Mode, where the internal PLL is bypassed and an external clock source is used; otherwise the chip operates normally • EmbeddedICE Mode, where the JTAG port accesses the TAP Controller in the core and the core is placed in Debug Mode. 32 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Device Pin Multiplexing Table 14. LCD Panel Signal Multiplexing EXTERNAL PIN LVCVD11 LVCVD10 LVCVD9 LVCVD8 LVCVD7 LVCVD6 LVCVD5 LVCVD4 LVCVD3 LVCVD2 LVCVD1 LVCVD0 4-BIT STN (MONOCHROME) SINGLE PANEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MUSTN3 MUSTN2 MUSTN1 MUSTN0 DUAL PANEL MLSTN3 MLSTN2 MLSTN1 MLSTN0 Reserved Reserved Reserved Reserved MUSTN3 MUSTN2 MUSTN1 MUSTN0 8-BIT STN SINGLE PANEL (MONOCHROME) Reserved Reserved Reserved Reserved MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 NOTES: 1. MUSTN = Mono upper panel STN, dual and/or single panel. 2. MLSTN = Mono lower panel STN, dual panel only. Table 15. LCD External Pin Multiplexing (LH75401 and LH75411) EXTERNAL PIN PG4/LCDVEEEN/LCDMOD PG3/LCDVDDEN PG2/LCDDSPLEN/LCDREV PG1/LCDCLS PG0/LCDPS PH7/LCDDCLK PH6/LCDLP/LCDHRLP PH5/LCDFP/LCDSPS PH4/LCDEN/LCDEN PH3/LCDVD11 PH2/LCDVD10 PH1/LCDVD9 PH0/LCDVD8 PI7/LCDVD7 PI6/LCDVD6 PI5/LCDVD5 PI4/LCDVD4 PI3/LCDVD3 PI2/LCDVD2 PI1/LCDVD1 PI0/LCDVD0 DEFAULT MODE (NO LCD) PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 4-BIT MONO STN MODE SINGLE LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 DUAL LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN MLSTN3 MLSTN2 MLSTN1 MLSTN0 PI7 PI6 PI5 PI4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 8-BIT STN MODE LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN PH3 PH2 PH1 PH0 STN7 STN6 STN5 STN4 STN3 STN2 STN1 STN0 TFT MODE LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 ALI MODE LCDMOD LCDVDDEN LCDREV LCDCLS LCDPS LCDDCLK LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 Preliminary data sheet Rev. 01 — 16 July 2007 33 LH75401/LH75411 NXP Semiconductors System-on-Chip ELECTRICAL SPECIFICATIONS Table 16. Absolute Maximum Ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage for ADC (VDDA0) DC Analog Supply Voltage for PLL (VDDA1) Storage Temperature (TSTG) MINIMUM MAXIMUM -0.3 V -0.3 V -0.3 V -0.3 V -55°C 2.4 V 4.6 V 4.6 V 2.4 V 125°C NOTE: These ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Table 17. Recommended Operating Conditions PARAMETER DC Core Supply Voltage (VDDC) (Linear Regulator disabled) DC Analog Supply Voltage for ADC (VDDA0) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage for PLL (VDDA1) Clock Frequency (ƒHCLK) Clock Period (tHCLK) Crystal Frequency Industrial Operating Temperature MINIMUM 1.7 V 3.0 V 3.0 V 1.7 V 4.375 MHz 11.9047 ns 14 MHz −40°C 25°C TYP. 1.8 V 3.3 V 3.3 V 1.8 V MAXIMUM 1.98 V 3.6 V 3.6 V 1.98 V 84 MHz 228.571 ns 20 MHz 85°C 1 2 3, 4, 5 3, 4, 5 4, 5 NOTES 1 NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See the section titled ‘Power Supply Sequencing’. 2. Connect VDDA1 to VDDC when using the on-chip linear regulator. 3. On-chip Linear regulator enabled. When the on-chip linear regulator is enabled, Core power is drawn from VDD – allow VDDC pins to float. 4. Will operate to DC with PLL disabled. Core frequencies greater than 84 MHz require external clock and VDDC. Core frequencies faster than 70 MHz require an externally-supplied clock. 5. Processor is functional at minimum frequency, but not all peripherals may be enabled. 6. The maximum operating frequency is the crystal frequency × 3.5. Table 18. Clock Frequency vs. Voltages (VDDC) vs. Temperature PARAMETER 25°C 70°C 85°C Clock Frequency (ƒHCLK) Clock Period (tHCLK) Clock Frequency (ƒHCLK) Clock Period (tHCLK) Clock Frequency (ƒHCLK) Clock Period (tHCLK) 1.7 V 91.3 MHz 10.952 ns 86 MHz 11.627 ns 84 MHz 11.9047 ns 1.8 V 97 MHz 10.309 ns 92 MHz 10.869 ns 90 MHz 11.111 ns 1.9 V 103.7 MHz 9.643 ns 97.4 MHz 10.266 ns 95.2 MHz 10.504 ns NOTES: 1. On-chip Linear regulator and PLL disabled; VDDC supplied externally. 2. Core speeds greater than 84 MHz require external VDDC and may not yield proper UART baud rates. 3. Core speeds greater than 70 MHz require an external clock. 4. Additional performance may be achieved in accordance with Figure 5. 34 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 110 105 100 2V Frequency (MHz) 95 1.95 V 1.9 V 90 1.85 V 1.8 V 85 1.75 V 1.7 V 80 1.65 V 1.6 V 75 70 25 35 45 55 65 75 85 Temp (˚Celsius) LH754xx-106 Figure 5. Maximum Core Frequency versus Voltage and Temperature Very Low Operating Temperatures and Noise Immunity The junction temperature, Tj, is the operating temperature of the transistors in the integrated circuit. The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating temperature, the faster the CMOS circuits will switch. Increased switching noise generated by faster switching circuits could affect the overall system stability. The amount of switching noise is directly affected by the application executed on the SoC. NXP recommends that users implementing a system to meet low industrial temperature standards should use an external oscillator rather than a crystal to drive the system clock input of the System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC. Preliminary data sheet Rev. 01 — 16 July 2007 35 LH75401/LH75411 NXP Semiconductors System-on-Chip DC Characteristics All characteristics are specified over an operating temperature of −40°C to +85°C, and at minimum and maximum supply voltages. Table 19. DC Characteristics SYMBOL VIH VIL VT+ VTVhst PARAMETER CMOS Input HIGH Voltage CMOS Input LOW Voltage Schmitt Trigger Positive Going Threshold Schmitt Trigger Negative Going Threshold Schmitt Trigger Hysteresis Output Drive 1 VOH Output Drive 2 Output Drive 3 Output Drive 4 Output Drive 1 VOL Output Drive 2 Output Drive 3 Output Drive 4 XTAL32IN XTALIN IIN IACTIVE ISLEEP ISTOP1 ISTOP2 ISTOP2 External Clock Input External Clock Input Input Leakage Current Active Current Sleep Current Stop1 Current Stop2 Current (RTC ON) Stop2 Current (RTC OFF) 1.62 1.62 -10 50 45 4.0 3.0 35 120 23 100 1.8 1.8 0.35 2.6 2.6 2.6 2.6 0.4 0.4 0.4 0.4 1.98 1.98 10 70 2.0 0.8 MIN. TYP. MAX. UNIT 2.0 0.8 V V V V V V V V V V V V V V V µA mA mA mA mA µA µA µA µA 3 4 3 4 IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA Externally supplied Externally supplied VIN = VDD or GND 2 2 1 CONDITIONS NOTES ISTANDBY Standby Current NOTES: 1. VIL MAX. = 0.5 V for pin TCK with 50 pF load. 2. Running a Typical Application at 51.6 MHz. 3. Using external 1.8 V supply, internal regulator disabled. 4. Using Internal linear regulator. Table 20. Linear Regulator DC Characteristics SYMBOL IQUIESCENT ISLEEPLR IOLR VOLR RPULL PARAMETER Quiescent Current Current when Regulator is Disabled Output Current Range Output Voltage Pull-up Resistor 0.0 1.84 0 MIN. TYP. 75 8 100 MAX. UNIT µA µA mA V Ω 36 Rev. 01 — 16 July 2007 Preliminary data sheet System-on-Chip NXP Semiconductors LH75401/LH75411 Analog-To-Digital Converter Electrical Characteristics Table 21 shows the derated specifications for extended temperature operation. See Figure 6 for the ADC transfer characteristics. Table 21. ADC Electrical Characteristics at Industrial Operating Range PARAMETER A/D Resolution Throughput Conversion Acquisition Time Clk Period Differential Non-Linearity Integral Non-Linearity Offset Error Gain Error On-chip Voltage Reference (VREF) Negative Reference Input (VREF-) Positive Reference Input (VREF+) Crosstalk between channels Analog Input Voltage Range Analog Input Current Reference Input Current Analog input capacitance Operating Supply Voltage Operating Current, VDDA Standby Current Stop Current, VDDA Brown Out Trip Point Brown Out Hysterisis Operating Temperature −40 3.0 590 180