NX3DV3899GU

NX3DV3899 Dual double-pole double-throw analog switch Rev. 2 — 23 November 2010 Product data sheet 1. General description The NX3DV3899 is a dual double-pole double-throw analog data-switch suitable for use as an analog or digital multiplexer/demultiplexer. It consists of four switches, each with two independent input/outputs (nY0 and nY1) and a common input/output (nZ). The two digital inputs (1S and 2S) are used to select the switch position. Schmitt trigger action at the select input (nS) makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 1.4 V to 4.3 V. A low input voltage threshold allows pin nS to be driven by lower level logic signals without a significant increase in supply current ICC. This makes it possible for the NX3DV3899 to switch 4.3 V signals with a 1.8 V digital controller, eliminating the need for logic level translation. The NX3DV3899 allows signals with amplitude up to VCC to be transmitted from nZ to nY0 or nY1; or from nY0 or nY1 to nZ. 2. Features and benefits Wide supply voltage range from 1.4 V to 4.3 V Very low ON resistance (peak): 7.2 Ω (typical) at VCC = 1.4 V 5.4 Ω (typical) at VCC = 1.65 V 2.9 Ω (typical) at VCC = 2.5 V 2.4 Ω (typical) at VCC = 3.0 V 2.3 Ω (typical) at VCC = 3.6 V 2.2 Ω (typical) at VCC = 4.3 V Break-before-make switching High noise immunity ESD protection: HBM JESD22-A114F Class 2A exceeds 2000 V (all pins) HBM JESD22-A114F Class 3A exceeds 5000 V (I/O pins to GND) MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V CMOS low-power consumption Latch-up performance exceeds 100 mA per JESD 78B Class II Level A 1.8 V control logic at VCC = 3.6 V Control input accepts voltages above supply voltage Very low supply current, even when input is below VCC High current handling capability (350 mA continuous current under 3.3 V supply) Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 3. Applications Data switch Cell phone PDA Portable media player 4. Ordering information Table 1. Ordering information Package Temperature range NX3DV3899HR −40 °C to +125 °C Name Description Version SOT1039-1 HXQFN16U plastic thermal enhanced extremely thin quad flat package; no leads; 16 terminals; UTLP based; body 3 × 3 × 0.5 mm XQFN16 plastic, extremely thin quad flat package; no leads; 16 terminals; body 1.80 × 2.60 × 0.50 mm Type number NX3DV3899GU −40 °C to +125 °C SOT1161-1 5. Marking Table 2. Marking codes Marking code ×99 ×9 Type number NX3DV3899HR NX3DV3899GU 6. Functional diagram 1Y0 1Z 1Y1 2Y0 2Z 2Y1 1S 3Y0 3Z 3Y1 4Y0 4Z 4Y1 2S 001aak174 Fig 1. Logic symbol NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 2 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 1Y1 3Y1 1Z 3Z 1Y0 1S 3Y0 2S 2Y1 4Y1 2Z 4Z 2Y0 4Y0 001aam785 Fig 2. Logic diagram 7. Pinning information 7.1 Pinning 14 VCC 16 1Z terminal 1 index area 15 1Y1 13 4Y0 12 4Z 11 4Y1 10 2S 9 3Y0 3Z 8 001aam787 © NXP B.V. 2010. All rights reserved. terminal 1 index area VCC 14 1Y1 16 15 13 4Y0 1Z 1Y0 1S 2Y1 2Z 1 2 12 11 4Z 4Y1 2S 3Y0 1Y0 1 1S 2 NX3DV3899 3 4 5 GND(1) 6 7 8 10 9 2Y1 3 2Z 4 NX3DV3899 2Y0 5 GND 6 001aam786 Transparent top view Transparent top view (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to GND. Fig 3. Pin configuration SOT1039-1 (HXQFN16U) Fig 4. Pin configuration SOT1161-1 (XQFN16) NX3DV3899 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 23 November 2010 3Y1 7 2Y0 GND 3Y1 3Z 3 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 7.2 Pin description Table 3. Symbol 1Y0, 2Y0, 3Y0, 4Y0 1S, 2S 1Y1, 2Y1, 3Y1, 4Y1 1Z, 2Z, 3Z, 4Z GND VCC Pin description Pin 1, 5, 9, 13 2, 10 15, 3, 7, 11 16, 4, 8, 12 6 14 Description independent input or output select input independent input or output common output or input ground (0 V) supply voltage 8. Functional description Table 4. Input nS L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Channel on nY0 nY1 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VSW IIK ISK ISW Parameter supply voltage input voltage switch voltage input clamping current switch clamping current switch current VI < −0.5 V VI < −0.5 V or VI > VCC + 0.5 V VSW > −0.5 V or VSW < VCC + 0.5 V; source or sink current VSW > −0.5 V or VSW < VCC + 0.5 V; pulsed at 1 ms duration, < 10 % duty cycle; peak current Tstg Ptot storage temperature total power dissipation Tamb = −40 °C to +125 °C HXQFN16U XQFN16 [1] [2] [3] [4] The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not exceed 4.6 V. For HXQFN16U package: above 135 °C the value of Ptot derates linearly with 16.9 mW/K. For XQFN16 package: above 133 °C the value of Ptot derates linearly with 14.5 mW/K. [3] [4] Conditions select input nS [1] [2] Min −0.5 −0.5 −0.5 −50 - Max +4.6 +4.6 ±50 ±350 ±500 Unit V V mA mA mA mA VCC + 0.5 V −65 - +150 250 250 °C mW mW NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 4 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 10. Recommended operating conditions Table 6. VCC VI VSW Tamb Δt/ΔV [1] Recommended operating conditions Conditions select input nS [1] Symbol Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate Min 1.4 0 0 −40 - Max 4.3 4.3 VCC +125 200 Unit V V V °C ns/V VCC = 1.4 V to 4.3 V [2] To avoid sinking GND current from terminal nZ when switch current flows in terminal nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nYn. In this case, there is no limit for the voltage drop across the switch. Applies to control signal levels. [2] 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions Min VIH HIGH-level input voltage VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V VIL LOW-level input voltage VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V II input leakage current OFF-state leakage current ON-state leakage current select input nS; VI = GND to 4.3 V; VCC = 1.4 V to 4.3 V nY0 and nY1 port; see Figure 5 VCC = 1.4 V to 4.3 V nZ port; see Figure 6 VCC = 1.4 V to 4.3 V ±5 ±50 ±500 nA ±5 ±50 ±500 nA 0.9 0.9 1.1 1.3 1.4 Tamb = 25 °C Typ Max 0.3 0.4 0.4 0.5 0.6 Tamb = −40 °C to +125 °C Min 0.9 0.9 1.1 1.3 1.4 Max Max (85 °C) (125 °C) 0.3 0.4 0.4 0.5 0.6 ±0.5 0.3 0.3 0.4 0.5 0.6 ±1 V V V V V V V V V V μA Unit IS(OFF) IS(ON) ICC supply current VI = VCC or GND; VSW = GND or VCC VCC = 3.6 V VCC = 4.3 V 100 150 500 800 5000 6000 nA nA NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 5 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions Min ΔICC additional VSW = GND or VCC supply current VI = 2.6 V; VCC = 4.3 V VI = 2.6 V; VCC = 3.6 V VI = 1.8 V; VCC = 4.3 V VI = 1.8 V; VCC = 3.6 V VI = 1.8 V; VCC = 2.5 V CI CS(OFF) CS(ON) input capacitance OFF-state capacitance ON-state capacitance Tamb = 25 °C Typ Max Tamb = −40 °C to +125 °C Min Max Max (85 °C) (125 °C) 7 1 15 5 300 7 1 15 5 500 μA μA μA μA nA pF pF pF Unit - 2.0 0.35 7.0 2.5 50 1.0 8 30 4.0 0.7 10.0 4.0 200 - - 11.1 Test circuits switch 1 VIL or VIH nS nZ nY0 nY1 1 2 2 switch IS nS VIH VIL VCC VI VO GND 012aaa000 VI = 0.3 V or VCC − 0.3 V; VO = VCC − 0.3 V or 0.3 V. Fig 5. Test circuit for measuring OFF-state leakage current VCC nS nZ nY0 1 nY1 2 switch 1 nS VIH VIL VIL or VIH IS VI 2 switch VO GND 012aaa001 VI = 0.3 V or VCC − 0.3 V; VO = VCC − 0.3 V or 0.3 V. Fig 6. Test circuit for measuring ON-state leakage current NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 6 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 11.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 8 to Figure 14. Symbol Parameter Conditions VI = GND to VCC; ISW = 100 mA; see Figure 7 VCC = 1.4 V VCC = 1.65 V VCC = 2.5 V VCC = 3.0 V VCC = 3.6 V VCC = 4.3 V ΔRON ON resistance mismatch between channels ON resistance (flatness) VI = GND to VCC; ISW = 100 mA VCC = 3.0 V VCC = 4.3 V VI = GND to VCC; ISW = 100 mA VCC = 1.4 V VCC = 1.65 V VCC = 2.5 V VCC = 3.0 V VCC = 3.6 V VCC = 4.3 V [1] [2] [3] Typical values are measured at Tamb = 25 °C. Measured at identical VCC, temperature and input voltage. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. [3] [2] Tamb = −40 °C to +85 °C Tamb = −40 °C to +125 °C Unit Min Typ[1] Max Min Max RON(peak) ON resistance (peak) - 7.2 5.4 2.9 2.4 2.3 2.2 9.3 7.3 3.9 3.4 3.3 3.3 - 10 8 4.5 4.5 4.2 4.2 Ω Ω Ω Ω Ω Ω - 0.8 0.7 - - - Ω Ω RON(flat) - 4.4 2.8 1.0 0.8 0.9 1.0 - - - Ω Ω Ω Ω Ω Ω NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 7 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 11.3 ON resistance test circuit and graphs 8 RON (Ω) 7 (1) 001aam788 6 5 (2) VSW V VCC nS nZ VI switch 1 nS VIL VIH 4 (3) VIL or VIH nY0 1 switch nY1 2 2 3 2 (4) (5) (6) ISW GND 012aaa002 1 0 1 2 3 4 VI (V) 5 RON = VSW / ISW. (1) VCC = 1.4 V. (2) VCC = 1.65 V. (3) VCC = 2.5 V. (4) VCC = 3.0 V. (5) VCC = 3.6 V. (6) VCC = 4.3 V. Measured at Tamb = 25 °C. Fig 7. Test circuit for measuring ON resistance Fig 8. Typical ON resistance as a function of input voltage NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 8 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 8 RON (Ω) 6 001aam789 6.5 RON (Ω) 5.5 (4) (3) (2) 001aam790 (4) (3) (2) (1) 4.5 (1) 3.5 4 2.5 2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VI (V) 1.4 1.5 0.0 0.4 0.8 1.2 1.6 VI (V) 2.0 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 9. ON resistance as a function of input voltage; VCC = 1.4 V Fig 10. ON resistance as a function of input voltage; VCC = 1.65 V 3.75 RON (Ω) 3.25 (4) (3) 001aam791 3.5 RON (Ω) 3.0 (4) (3) 001aam792 2.75 (2) (1) 2.5 (2) (1) 2.25 2.0 1.75 1.5 1.25 0.0 1.0 0.5 1.0 1.5 2.0 VI (V) 2.5 0 1 2 VI (V) 3 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 11. ON resistance as a function of input voltage; VCC = 2.5 V Fig 12. ON resistance as a function of input voltage; VCC = 3.0 V NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 9 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 3.0 RON (Ω) 2.5 (4) (3) (2) 001aam793 3.0 RON (Ω) 2.5 001aam794 2.0 (4) (3) 2.0 (1) (2) 1.5 (1) 1.5 1.0 1.0 0 1 2 3 VI (V) 4 0.5 0 1 2 3 4 VI (V) 5 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 13. ON resistance as a function of input voltage; VCC = 3.6 V Fig 14. ON resistance as a function of input voltage; VCC = 4.3 V 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 17. Symbol Parameter Conditions Tamb = 25 °C Min ten enable time nS to nZ or nYn; see Figure 15 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V tdis disable time nS to nZ or nYn; see Figure 15 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V 24 15 9 8 8 70 55 25 20 20 80 60 30 25 25 90 65 35 30 30 ns ns ns ns ns 41 30 20 19 19 90 70 45 40 40 120 80 50 45 45 120 90 55 50 50 ns ns ns ns ns Typ[1] Max Tamb = −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 10 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch Table 9. Dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 17. Symbol Parameter Conditions Tamb = 25 °C Min tb-m break-before-make see Figure 16 time VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V [1] [2] [2] Tamb = −40 °C to +125 °C Min Max (85 °C) Max (125 °C) - Unit Typ[1] Max - 20 17 13 11 11 - 9 7 4 3 2 ns ns ns ns ns Typical values are measured at Tamb = 25 °C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively. Break-before-make guaranteed by design. 12.1 Waveform and test circuits VI nS input GND ten VOH nZ output nY1 connected to VEXT OFF to HIGH HIGH to OFF GND tdis nZ output nY0 connected to VEXT HIGH to OFF OFF to HIGH VOH VX ten VX 012aaa003 VM tdis VX VX GND Measurement points are given in Table 10. Logic level: VOH is typical output voltage level that occurs with the output load. Fig 15. Enable and disable times Table 10. VCC 1.4 V to 4.3 V Measurement points Input VM 0.5VCC Output VX 0.9VOH Supply voltage NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 11 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch VCC nS nZ nY0 nY1 VEXT = 1.5 V G VI V VO RL CL GND 012aaa004 a. Test circuit VI 0.5VI 0.9VO VO tb-m 0.9VO 001aag572 b. Input and output measurement points Fig 16. Test circuit for measuring break-before-make timing VCC nS nZ nY0 nY1 1 2 switch G VI V VO RL CL VEXT = 1.5 V GND 012aaa005 Test data is given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. Fig 17. Test circuit for measuring switching times Table 11. VCC 1.4 V to 4.3 V Test data Input VI VCC tr, tf ≤ 2.5 ns Load CL 35 pF RL 50 Ω Supply voltage NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 12 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf ≤ 2.5 ns; Tamb = 25 °C. Symbol Parameter THD total harmonic distortion Conditions fi = 20 Hz to 20 kHz; RL = 600 Ω; see Figure 18 VCC = 1.4 V; VI = 1 V (p-p) VCC = 1.65 V; VI = 1.2 V (p-p) VCC = 2.3 V; VI = 1.5 V (p-p) VCC = 2.7 V; VI = 2 V (p-p) VCC = 3.6 V; VI = 2 V (p-p) VCC = 4.3 V; VI = 2 V (p-p) f(−3dB) αiso Vct −3 dB frequency response isolation (OFF-state) crosstalk voltage RL = 50 Ω; see Figure 19 VCC = 1.4 V to 4.3 V fi = 1 MHz; RL = 50 Ω; see Figure 20 VCC = 1.4 V to 4.3 V between digital inputs and switch; fi = 1 MHz; CL = 50 pF; RL = 50 Ω; see Figure 21 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V Xtalk crosstalk between switches; fi = 1 MHz; RL = 50 Ω; see Figure 22 VCC = 1.4 V to 4.3 V Qinj charge injection fi = 1 MHz; CL = 0.1 nF; RL = 1 MΩ; Vgen = 0 V; Rgen = 0 Ω; see Figure 23 VCC = 1.4 V VCC = 1.65 V VCC = 2.5 V VCC = 3.0 V VCC = 3.6 V VCC = 4.3 V [1] fi is biased at 0.5VCC. [1] [1] [1] [1] Min - Typ 0.05 0.02 0.01 0.01 0.01 0.01 200 −70 Max - Unit % % % % % % MHz dB - 210 300 - V V - −90 - dB - 0.5 0.7 1.6 2.1 2.9 4.0 - pC pC pC pC pC pC NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 13 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 12.3 Test circuits VCC 0.5VCC RL switch 1 nS VIL VIH VIL or VIH nS nZ nY0 1 switch nY1 2 2 fi D GND 012aaa006 Fig 18. Test circuit for measuring total harmonic distortion VCC 0.5VCC RL switch 1 nS VIL VIH VIL or VIH nS nZ nY0 1 switch nY1 2 2 fi dB GND 012aaa007 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB. Fig 19. Test circuit for measuring the frequency response when channel is in ON-state 0.5VCC RL VCC 0.5VCC RL switch 1 nS VIH VIL VIL or VIH nS nZ nY0 1 switch nY1 2 2 fi dB GND 012aaa008 Adjust fi voltage to obtain 0 dBm level at input. Fig 20. Test circuit for measuring isolation (OFF-state) NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 14 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch switch VCC 1 2 nS nZ G logic input nY0 1 nY1 2 switch nS VIL VIH VI RL RL CL V VO 0.5VCC 0.5VCC 012aaa009 a. Test circuit logic input (nS) off on off VO Vct 012aaa010 b. Input and output pulse definitions Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch 0.5VCC CHANNEL ON nY0 or nZ fi 50 Ω RL nZ or nY0 V VO1 VIL nS 0.5VCC RL nY0 or nZ Ri 50 Ω nZ or nY0 CHANNEL OFF V VO2 001aak178 20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2). Fig 22. Test circuit for measuring crosstalk between switches NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 15 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch VCC nS nZ nY0 1 nY1 2 Rgen VI switch G VO RL CL Vgen GND 012aaa011 a. Test circuit logic (nS) off input on off VO ΔVO 012aaa012 b. Input and output pulse definitions Definition: Qinj = ΔVO × CL. ΔVO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 23. Test circuit for measuring charge injection NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 16 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 13. Package outline HXQFN16U: plastic thermal enhanced extremely thin quad flat package; no leads; 16 terminals; UTLP based; body 3 x 3 x 0.5 mm SOT1039-1 D B A terminal 1 index area E A A1 detail X e1 e 1/2 e L1 5 b 8 v w M M CAB C C y1 C y L 4 9 e Eh 1/2 e 1 12 e2 terminal 1 index area 16 13 Dh 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.25 D 3.1 2.9 Dh 1.95 1.75 E 3.1 2.9 Eh 1.95 1.75 e 0.5 e1 1.5 e2 1.5 L 0.35 0.25 L1 0.1 0.0 v 0.1 w 0.05 y 0.05 5 mm X y1 0.1 OUTLINE VERSION SOT1039-1 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-01 Fig 24. Package outline SOT1039-1 (HXQFN16U) NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 17 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch XQFN16: plastic, extremely thin quad flat package; no leads; 16 terminals; body 1.80 x 2.60 x 0.50 mm SOT1161-1 X D B A terminal 1 index area E A A1 A3 detail X e1 e 5 L 4 9 e e2 b 8 v w CAB C y1 C C y 1 terminal 1 index area 16 L1 13 12 0 Dimensions Unit(1) mm max nom min A 0.5 A1 0.05 A3 b D 1.9 1.8 1.7 E 2.7 2.6 2.5 e 0.4 e1 1.2 e2 1.2 1 scale L L1 v 2 mm w y y1 0.25 0.127 0.20 0.00 0.15 0.45 0.55 0.40 0.50 0.35 0.45 0.1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT1161-1 References IEC --JEDEC --JEITA --European projection sot1161-1_po Issue date 09-12-28 09-12-29 Fig 25. Package outline SOT1161-1 (XQFN16) NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 18 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 14. Abbreviations Table 13. Acronym CDM CMOS ESD HBM MM PDA Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Personal Digital Assistant 15. Revision history Table 14. Revision history Release date 20101123 Data sheet status Product data sheet Change notice Supersedes NX3DV3899 v.1 Document ID NX3DV3899 v.2 Modifications: NX3DV3899 v.1 • Table 7: conditions for ON-state leakage current (IS(ON)) and supply current (ICC) have changed. Product data sheet - 20101021 NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 23 November 2010 19 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2. — 23 November 2010 20 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NX3DV3899 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2. — 23 November 2010 21 of 22 NXP Semiconductors NX3DV3899 Dual double-pole double-throw analog switch 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveform and test circuits . . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 November 2010 Document identifier: NX3DV3899