PBLS2003D

PBLS2003D 20 V PNP BISS loadswitch Rev. 02 — 27 August 2009 Product data sheet 1. Product profile 1.1 General description PNP low VCEsat Breakthrough in Small Signal (BISS) transistor and NPN ResistorEquipped Transistor (RET) in a SOT457 (SC-74) small Surface Mounted Device (SMD) plastic package. 1.2 Features I I I I I Low VCEsat (BISS) and resistor-equipped transistor in one package Low threshold voltage (< 1 V) compared to MOSFET Low drive power required Space-saving solution Reduction of component count 1.3 Applications I I I I Supply line switches Battery charger switches High-side switches for LEDs, drivers and backlights Portable equipment 1.4 Quick reference data Table 1. Symbol VCEO IC RCEsat Quick reference data Parameter collector-emitter voltage collector current (DC) collector-emitter saturation resistance collector-emitter voltage output current bias resistor 1 (input) bias resistor ratio IC = −1 A; IB = −100 mA open base [1] Conditions open base Min - Typ 185 Max −20 −1 280 Unit V A mΩ TR1; PNP low VCEsat transistor TR2; NPN resistor-equipped transistor VCEO IO R1 R2/R1 [1] 7 0.8 10 1 50 100 13 1.2 V mA kΩ Pulse test: tp ≤ 300 µs; δ ≤ 0.02 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 2. Pinning information Table 2. Pin 1 2 3 4 5 6 Pinning Description emitter TR1 base TR1 output (collector) TR2 GND (emitter) TR2 input (base) TR2 collector TR1 1 2 3 sym036 Simplified outline 6 5 4 Symbol 6 5 4 1 2 3 R1 R2 TR2 TR1 3. Ordering information Table 3. Ordering information Package Name PBLS2003D SC-74 Description plastic surface mounted package; 6 leads Version SOT457 Type number 4. Marking Table 4. Marking codes Marking code F8 Type number PBLS2003D 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCBO VCEO VEBO IC ICM IB IBM Ptot Parameter collector-base voltage collector-emitter voltage emitter-base voltage collector current (DC) peak collector current base current (DC) peak base current total power dissipation tp ≤ 300 µs Tamb ≤ 25 °C [1] [2] [3] Conditions open emitter open base open collector tp ≤ 300 µs Min - Max −20 −20 −5 −1 −2 −0.3 −0.6 250 350 400 Unit V V V A A A A mW mW mW TR1; PNP low VCEsat transistor PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 2 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCBO VCEO VEBO VI Parameter collector-base voltage collector-emitter voltage emitter-base voltage input voltage positive negative IO ICM Ptot Ptot output current peak collector current total power dissipation total power dissipation tp ≤ 300 µs Tamb ≤ 25 °C [1] Conditions open emitter open base open collector Min −65 −65 Max 50 50 10 +40 −10 100 100 200 400 530 600 +150 150 +150 Unit V V V V V mA mA mW mW mW mW °C °C °C TR2; NPN resistor-equipped transistor Per device [1] [2] [3] Tstg Tj Tamb [1] [2] [3] storage temperature junction temperature ambient temperature Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1cm2. Device mounted on a ceramic PCB, Al2O3, standard footprint. 0.8 Ptot (W) (1) 006aaa414 0.6 (2) (3) 0.4 0.2 0 0 40 80 120 160 Tamb (°C) (1) Ceramic PCB, Al2O3, standard footprint (2) FR4 PCB, mounting pad for collector 1cm2 (3) FR4 PCB, standard footprint Fig 1. PBLS2003D_2 Power derating curves © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 3 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 6. Thermal characteristics Table 6. Symbol Per device Rth(j-a) thermal resistance from junction to ambient in free air [1] [2] [3] Thermal characteristics Parameter Conditions Min Typ Max 315 236 210 Unit K/W K/W K/W [1] [2] [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1cm2. Device mounted on a ceramic PCB, Al2O3, standard footprint. duty cycle = 1 Zth(j-a) 0.75 (K/W) 0.5 0.33 102 0.2 0.1 0.05 10 0.02 0.01 103 006aaa415 1 0 10−1 10−5 10−4 10−3 10−2 10−1 1 10 102 t p (s) 103 FR4 PCB, standard footprint Fig 2. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse time; typical values PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 4 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 103 Zth(j-a) (K/W) 102 δ=1 0.75 0.5 0.33 0.2 0.1 0.05 10 0.02 0.01 0 1 10−5 10−4 10−3 10−2 10−1 006aaa463 1 10 102 tp (s) 103 FR4 PCB, mounting pad for collector 1cm2 Fig 3. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse time; typical values 006aaa464 103 Zth(j-a) (K/W) δ = 1 0.75 0.5 2 10 0.33 0.2 0.1 0.05 10 0.02 0.01 0 1 10−5 10−4 10−3 10−2 10−1 1 10 102 tp (s) 103 Ceramic PCB, Al2O3, standard footprint Fig 4. TR1 (PNP): Transient thermal impedance from junction to ambient as a function of pulse time; typical values PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 5 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 7. Characteristics Table 7. Characteristics Tamb = 25 °C unless otherwise specified Symbol ICBO Parameter collector-base cut-off current collector-emitter cut-off current emitter-base cut-off current DC current gain Conditions VCB = −20 V; IE = 0 A VCB = −20 V; IE = 0 A; Tj = 150 °C VCE = −20 V; VBE = 0 V VEB = −5 V; IC = 0 A VCE = −2 V; IC = −1 mA VCE = −2 V; IC = −100 mA VCE = −2 V; IC = −500 mA VCE = −2 V; IC = −1 A VCE = −2 V; IC = −2 A VCEsat collector-emitter saturation voltage IC = −100 mA; IB = −1 mA IC = −500 mA; IB = −50 mA IC = −1 A; IB = −50 mA IC = −1 A; IB = −100 mA RCEsat VBEsat VBEon td tr ton ts tf toff fT Cc collector-emitter saturation resistance base-emitter saturation voltage base-emitter turn-on voltage delay time rise time turn-on time storage time fall time turn-off time transition frequency collector capacitance IC = −50 mA; VCE = −10 V; f = 100 MHz VCB = −10 V; IE = ie = 0 A; f = 1 MHz IC = −1 A; IB = −100 mA IC = −1 A; IB = −50 mA IC = −1 A; IB = −100 mA VCE = −5 V; IC = −1 A IC = −1 A; IBon = −50 mA; IBoff = 50 mA [1] [1] [1] [1] [1] [1] [1] Min 220 220 220 155 60 150 - Typ 495 440 310 220 120 −55 −100 −200 −185 185 −0.95 −1 −0.85 8 34 42 140 45 185 185 15 Max −0.1 −50 −0.1 −0.1 −90 −150 −300 −280 280 −1.1 −1.1 −1.1 20 Unit µA µA µA µA TR1; PNP low VCEsat transistor ICES IEBO hFE mV mV mV mV mΩ V V V ns ns ns ns ns ns MHz pF [1] [1] [1] PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 6 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch Table 7. Characteristics …continued Tamb = 25 °C unless otherwise specified Symbol ICBO ICEO Parameter collector-base cut-off current collector-emitter cut-off current emitter-base cut-off current DC current gain collector-emitter saturation voltage Conditions VCB = 50 V; IE = 0 A VCE = 30 V; IB = 0 A VCE = 30 V; IB = 0 A; Tj = 150 °C VEB = 5 V; IC = 0 A VCE = 5 V; IC = 5 mA IC = 10 mA; IB = 0.5 mA Min 30 2.5 7 0.8 VCB = 10 V; IE = ie = 0 A; f = 1 MHz Typ 1.1 1.8 10 1 Max 100 1 50 400 150 0.8 13 1.2 2.5 pF mV V V kΩ Unit nA µA µA µA TR2; NPN resistor-equipped transistor IEBO hFE VCEsat VI(off) VI(on) R1 R2/R1 Cc off-state input voltage VCE = 5 V; IC = 100 µA on-state input voltage VCE = 0.3 V; IC = 10 mA bias resistor 1 (input) bias resistor ratio collector capacitance [1] Pulse test: tp ≤ 300 µs; δ ≤ 0.02 PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 7 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 1000 hFE 800 (1) 006aaa416 −1 VCEsat (V) −10−1 006aaa417 600 (2) (1) (2) (3) 400 −10−2 (3) 200 0 −10−1 −1 −10 −102 −103 −104 IC (mA) −10−3 −10−1 −1 −10 −102 −103 −104 IC (mA) VCE = −2 V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 5. TR1 (PNP): DC current gain as a function of collector current; typical values Fig 6. TR1 (PNP): Collector-emitter saturation voltage as a function of collector current; typical values 006aaa419 −1.0 VBE (V) −0.8 (1) 006aaa418 −1.2 VBEsat (V) −1.0 (1) (2) −0.8 (2) −0.6 (3) −0.6 (3) −0.4 −0.4 −0.2 −10−1 −1 −10 −102 −103 −104 IC (mA) −0.2 −10−1 −1 −10 −102 −103 −104 IC (mA) VCE = −5 V (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C IC/IB = 20 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 7. TR1 (PNP): Base-emitter voltage as a function of collector current; typical values Fig 8. TR1 (PNP): Base-emitter saturation voltage as a function of collector current; typical values PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 8 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch −2.0 IC (A) −1.6 IB = −13 mA 006aaa420 −11.7 mA −10.4 mA −9.1 mA −7.8 mA −6.5 mA −5.2 mA −3.9 mA 102 RCEsat (Ω) 10 006aaa421 −1.2 −0.8 −2.6 mA 1 −1.3 mA (1) (2) (3) −0.4 −0 −0 −2 −4 VCE (V) −6 10−1 −10−1 −1 −10 −102 −103 −104 IC (mA) Tamb = 25 °C IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 9. TR1 (PNP): Collector current as a function of collector-emitter voltage; typical values Fig 10. TR1 (PNP): Collector-emitter saturation resistance as a function of collector current; typical values 103 RCEsat (Ω) 102 006aaa423 −1 VCEsat (V) −10−1 006aaa422 (1) (2) 10 −10−2 (3) 1 (1) (2) (3) −10−3 −10−1 −1 −10 −102 −103 −104 IC (mA) 10−1 −10−1 −1 −10 −102 −103 −104 IC (mA) Tamb = 25 °C (1) IC/IB = 100 (2) IC/IB = 50 (3) IC/IB = 10 Tamb = 25 °C (1) IC/IB = 100 (2) IC/IB = 50 (3) IC/IB = 10 Fig 11. TR1 (PNP): Collector-emitter saturation voltage as a function of collector current; typical values Fig 12. TR1 (PNP): Collector-emitter saturation resistance as a function of collector current; typical values PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 9 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 103 hFE (1) (2) (3) 006aaa034 1 006aaa035 VCEsat (V) 102 10−1 (1) (2) (3) 10 1 10−1 1 10 IC (mA) 102 10−2 1 10 IC (mA) 102 VCE = 5 V (1) Tamb = 150 °C (2) Tamb = 25 °C (3) Tamb = −40 °C IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −40 °C Fig 13. TR2 (NPN): DC current gain as a function of collector current; typical values Fig 14. TR2 (NPN): Collector-emitter saturation voltage as a function of collector current; typical values 10 006aaa037 10 006aaa036 VI(on) (V) (1) (2) VI(off) (V) (1) 1 (3) 1 (2) (3) 10−1 10−1 1 10 IC (mA) 102 10−1 10−2 10−1 1 IC (mA) 10 VCE = 0.3 V (1) Tamb = −40 °C (2) Tamb = 25 °C (3) Tamb = 100 °C VCE = 5 V (1) Tamb = −40 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 15. TR2 (NPN): On-state input voltage as a function of collector current; typical values Fig 16. TR2 (NPN): Off-state input voltage as a function of collector current; typical values PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 10 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 8. Test information − IB 90 % input pulse (idealized waveform) − I Bon (100 %) 10 % − I Boff − IC 90 % output pulse (idealized waveform) − I C (100 %) 10 % t td t on tr ts t off tf 006aaa266 Fig 17. BISS transistor switching time definition VBB VCC RB (probe) oscilloscope 450 Ω VI R1 R2 RC Vo (probe) 450 Ω DUT oscilloscope mgd624 IC = −1 A; IBon = −50 mA; IBoff = 50 mA; R1 = open; R2 = 45 Ω; RB = 145 Ω; RC = 10 Ω Fig 18. Test circuit for switching times PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 11 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 9. Package outline 3.1 2.7 6 5 4 0.6 0.2 1.1 0.9 3.0 2.5 1.7 1.3 pin 1 index 1 0.95 1.9 Dimensions in mm 2 3 0.40 0.25 0.26 0.10 04-11-08 Fig 19. Package outline SOT457 (SC-74) 10. Packing information Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number PBLS2003D Package SOT457 Description 4 mm pitch, 8 mm tape and reel; T1 4 mm pitch, 8 mm tape and reel; T2 [1] [2] [3] For further information and the availability of packing methods, see Section 14. T1: normal taping T2: reverse taping [2] [3] Packing quantity 3000 -115 -125 10000 -135 -165 PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 12 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 11. Soldering 3.45 1.95 solder lands 0.95 3.30 2.825 0.45 0.55 occupied area solder paste solder resist 1.60 1.70 3.10 3.20 msc422 Dimensions in mm Fig 20. Reflow soldering footprint 5.30 solder lands 5.05 0.45 1.45 4.45 solder resist occupied area 1.40 4.30 msc423 Dimensions in mm Fig 21. Wave soldering footprint PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 13 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 12. Revision history Table 9. Revision history Release date 20090827 Data sheet status Product data sheet Change notice Supersedes PBLS2003D_1 Document ID PBLS2003D_2 Modifications: • • This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content. Figure 21 “Wave soldering footprint”: updated Product data sheet - PBLS2003D_1 20050624 PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 14 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 13. Legal information 13.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PBLS2003D_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 27 August 2009 15 of 16 NXP Semiconductors PBLS2003D 20 V PNP BISS loadswitch 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Packing information. . . . . . . . . . . . . . . . . . . . . 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 August 2009 Document identifier: PBLS2003D_2