PH2625L,115

PH2625L N-channel TrenchMOS™ logic level FET Rev. 02 — 24 February 2005 Preliminary data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology. 1.2 Features ■ Optimized for use in DC-to-DC converters ■ Low threshold voltage ■ Very low switching and conduction losses ■ Low thermal resistance. 1.3 Applications ■ DC-to-DC converters ■ Voltage regulators ■ Switched-mode power supplies ■ Notebook computers. 1.4 Quick reference data ■ VDS ≤ 25 V ■ Qgd = 7.3 nC (typ) ■ RDSon ≤ 2.8 mΩ (VGS = 10 V) ■ ID ≤ 100 A ■ Qg(tot) = 32 nC (typ) ■ RDSon ≤ 4.1 mΩ (VGS = 4.5 V). 2. Pinning information Table 1: Pin Pinning Description 1, 2, 3 source 4 gate mb mounting base; connected to drain Simplified outline Symbol D mb G mbb076 1 2 3 4 SOT669 (LFPAK) S PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 3. Ordering information Table 2: Ordering information Type number PH2625L Package Name Description Version LFPAK plastic single-ended surface mounted package; 4 leads SOT669 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Conditions Min Max Unit VDS Symbol Parameter drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 25 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage - ±20 V ID drain current (DC) Tmb = 25 °C; VGS = 10 V; Figure 2 and 3 - 100 A Tmb = 100 °C; VGS = 10 V; Figure 2 - 63 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 300 A Ptot total power dissipation Tmb = 25 °C; Figure 1 - 62.5 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C - 52 A Tmb = 25 °C; pulsed; tp ≤ 10 µs - 156 A EDS(AL)S non-repetitive drain-source avalanche energy unclamped inductive load; ID = 71 A; tp = 0.1 ms; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; starting at Tj = 25 °C - 250 mJ EDS(AL)R repetitive drain-source avalanche energy unclamped inductive load; ID = 7.1 A; tp = 0.01 ms; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V - 2.5 mJ Source-drain diode IS source (diode forward) current (DC) Tmb = 25 °C ISM peak source (diode forward) current Avalanche ruggedness [1] [2] [1] Duty cycle is limited by the maximum junction temperature. [2] Repetitive avalanche failure is not determined simply by thermal effects. Repetitive avalanche transients should only be applied for short bursts, not every switching cycle. 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 2 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 03aa15 120 03aa23 120 Pder Ider (%) (%) 80 80 40 40 0 0 0 50 100 50 0 200 150 100 150 Tmb (°C) P tot P der = ------------------------ × 100 % P ° 200 Tmb (°C) ID I der = --------------------- × 100 % I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature Fig 2. Normalized continuous drain current as a function of mounting base temperature 003aaa551 103 ID (A) Limit RDSon = VDS / ID 102 tp = 10 µs 100 µs DC 1 ms 10 10 ms 100 ms 1 10-1 1 10 VDS (V) 102 Tmb = 25 °C; IDM is single pulse; VGS = 10 V Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 3 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Rth(j-mb) Conditions thermal resistance from junction to mounting base Figure 4 Min Typ Max Unit - - 2 K/W 003aaa552 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 0.05 0.02 δ= P single pulse 10-1 tp T t tp T 10-2 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 4 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 25 - - V Tj = 25 °C 1 1.5 2 V Tj = 150 °C 0.5 - - V Tj = −55 °C - - 2.2 V Tj = 25 °C - 0.06 1 µA Tj = 150 °C - - 500 µA Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 and 10 IDSS drain-source leakage current VDS = 25 V; VGS = 0 V RG gate resistance f = 1 MHz - 1.5 - Ω IGSS gate-source leakage current VGS = ±16 V; VDS = 0 V - 10 100 nA RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Figure 6 and 8 Tj = 25 °C - 2 2.8 mΩ Tj = 150 °C - 3.2 4.3 mΩ Tj = 25 °C - 3 4.1 mΩ Tj = 150 °C - 4.8 6.6 mΩ - 32 - nC - 9.6 - nC VGS = 4.5 V; ID = 25 A; Figure 6 and 8 Dynamic characteristics Qg(tot) total gate charge ID = 25 A; VDS = 12 V; VGS = 4.5 V; Figure 11 and 12 Qgs gate-source charge Qgs1 pre-VGS(th) gate-source charge - 6 - nC Qgs2 post-VGS(th) gate-source charge - 3.6 - nC Qgd gate-drain (Miller) charge - 7.3 - nC Vplat plateau voltage - 2.2 - V Qg(tot) total gate charge ID = 0 A; VDS = 0 V; VGS = 4.5 V - 26 - nC VGS = 0 V; VDS = 12 V; f = 1 MHz; Figure 13 and 14 - 4308 - pF - 1137 - pF - 439 - pF 4830 - pF Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance Ciss input capacitance VGS = 0 V; VDS = 0 V; f = 1 MHz - VDS = 12 V; RL = 0.48 Ω; VGS = 4.5 V; RG = 4.7 Ω - 41 - ns - 52 - ns td(on) turn-on delay time tr rise time td(off) turn-off delay time - 67 - ns tf fall time - 30 - ns - 0.85 1.2 V - 47 - ns - 22 - nC Source-drain diode VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 15 trr reverse recovery time Qr recovered charge IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V; VR = 25 V 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 5 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 40 003aaa553 10 4.5 003aaa555 20 2.4 2.5 ID (A) RDSon (mΩ) 15 VGS (V) = 2.3 30 2.1 VGS (V) = 2 2.2 2.2 2.3 10 20 2.1 1.9 10 5 4.5 1.8 10 1.7 0 0 0 1 0.5 1.5 VDS (V) 0 2 Tj = 25 °C 10 20 30 ID (A) 40 Tj = 25 °C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function of drain current; typical values ID 03af18 2 003aaa554 40 a (A) 1.5 30 Tj = 150 °C 25 °C 1 20 0.5 10 0 0 1 2 VGS (V) 3 Tj = 25 °C and 150 °C; VDS > ID × RDSon 0 -60 0 120 Tj (°C) 180 R DSon a = ----------------------------R DSon ( 25 °C ) Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature 9397 750 14324 Preliminary data sheet 60 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 6 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 03aa33 2.5 VGS(th) (V) 2 1.5 03aa36 10-1 ID (A) max 10-2 typ 10-3 min max 10-4 min 1 typ 10-5 0.5 0 -60 10-6 0 60 120 180 Tj (°C) 0 1 2 VGS (V) 3 Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature Fig 10. Sub-threshold drain current as a function of gate-source voltage 003aaa558 10 VGS (V) VDS (V) = 4.5 12 19 8 VDS ID 6 Vplat 4 VGS(th) VGS 2 Qgs1 Qgs2 Qgs 0 0 20 40 60 QG (nC) 80 Qgd Qg(tot) 003aaa508 ID = 25 A; VDS = 4.5 V, 12 V and 19 V Fig 11. Gate-source voltage as a function of gate charge; typical values Fig 12. Gate charge waveform definitions 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 7 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 003aaa556 104 003aaa632 8000 C C (pF) Ciss (pF) Ciss 6000 103 4000 Coss Crss Crss 102 10-1 1 2000 0 102 10 0 2 4 6 8 10 VGS (V) VDS (V) VGS = 0 V; f = 1 MHz VDS = 0 V; f = 1 MHz Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig 14. Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003aaa557 40 IS (A) 30 Tj = 150 °C 25 °C 20 10 0 0.2 0.4 0.6 0.8 VSD (V) 1 Tj = 25 °C and 150 °C; VGS = 0 V Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 8 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 7. Package outline Plastic single-ended surface mounted package (LFPAK); 4 leads A2 A E SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b X c 1/2 e A (A 3) A1 C θ L detail X y C 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 mm b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-09-15 04-10-13 MO-235 Fig 16. Package outline SOT669 (LFPAK) 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 9 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 8. Soldering 5.70 4.70 solder lands 4.60 0.075 3.70 solder resist 2.50 occupied area 2.00 0.90 (3×) solder paste 0.25 (2×) 0.25 (2×) 2.00 2.05 3.45 3.50 3.68 3.30 3.48 2.50 0.60 (3×) 0.85 1.10 2.15 MSD864 1.27 3.81 0.70 (4×) 0.05 around (4×) All dimensions in mm Fig 17. Optimized soldering footprint SOT669 (LFPAK) 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 10 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 9. Revision history Table 6: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes PH2625L_2 20050224 Preliminary data sheet 9397 750 14324 PH2625L-01 Modifications: PH2625L-01 - • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • RDSon data revised in Section 1.4 “Quick reference data” and Section 6 “Characteristics” 20040428 Preliminary data sheet - 9397 750 14324 Preliminary data sheet 9397 750 12306 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 11 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 10. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 11. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 13. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 12. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 14. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 9397 750 14324 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 February 2005 12 of 13 PH2625L Philips Semiconductors N-channel TrenchMOS™ logic level FET 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information . . . . . . . . . . . . . . . . . . . . 12 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 24 February 2005 Document number: 9397 750 14324 Published in The Netherlands